clock.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra114 Clock control functions */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sysctr.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <asm/arch-tegra/timer.h>
  16. #include <div64.h>
  17. #include <fdtdec.h>
  18. #include <linux/delay.h>
  19. /*
  20. * Clock types that we can use as a source. The Tegra114 has muxes for the
  21. * peripheral clocks, and in most cases there are four options for the clock
  22. * source. This gives us a clock 'type' and exploits what commonality exists
  23. * in the device.
  24. *
  25. * Letters are obvious, except for T which means CLK_M, and S which means the
  26. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  27. * datasheet) and PLL_M are different things. The former is the basic
  28. * clock supplied to the SOC from an external oscillator. The latter is the
  29. * memory clock PLL.
  30. *
  31. * See definitions in clock_id in the header file.
  32. */
  33. enum clock_type_id {
  34. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  35. CLOCK_TYPE_MCPA, /* and so on */
  36. CLOCK_TYPE_MCPT,
  37. CLOCK_TYPE_PCM,
  38. CLOCK_TYPE_PCMT,
  39. CLOCK_TYPE_PCMT16,
  40. CLOCK_TYPE_PDCT,
  41. CLOCK_TYPE_ACPT,
  42. CLOCK_TYPE_ASPTE,
  43. CLOCK_TYPE_PMDACD2T,
  44. CLOCK_TYPE_PCST,
  45. CLOCK_TYPE_COUNT,
  46. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  47. };
  48. enum {
  49. CLOCK_MAX_MUX = 8 /* number of source options for each clock */
  50. };
  51. /*
  52. * Clock source mux for each clock type. This just converts our enum into
  53. * a list of mux sources for use by the code.
  54. *
  55. * Note:
  56. * The extra column in each clock source array is used to store the mask
  57. * bits in its register for the source.
  58. */
  59. #define CLK(x) CLOCK_ID_ ## x
  60. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  61. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
  62. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  63. MASK_BITS_31_30},
  64. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
  65. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  66. MASK_BITS_31_30},
  67. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  68. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  69. MASK_BITS_31_30},
  70. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
  71. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  72. MASK_BITS_31_30},
  73. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  74. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  75. MASK_BITS_31_30},
  76. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  77. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  78. MASK_BITS_31_30},
  79. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
  80. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  81. MASK_BITS_31_30},
  82. { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  83. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  84. MASK_BITS_31_30},
  85. { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
  86. CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
  87. MASK_BITS_31_29},
  88. { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
  89. CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
  90. MASK_BITS_31_29},
  91. { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
  92. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  93. MASK_BITS_31_28}
  94. };
  95. /*
  96. * Clock type for each peripheral clock source. We put the name in each
  97. * record just so it is easy to match things up
  98. */
  99. #define TYPE(name, type) type
  100. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  101. /* 0x00 */
  102. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  103. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  104. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  105. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
  106. TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
  107. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  108. TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
  109. TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
  110. /* 0x08 */
  111. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  112. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
  113. TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
  114. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  115. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  116. TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
  117. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
  118. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
  119. /* 0x10 */
  120. TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
  121. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  122. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  123. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  124. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
  125. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
  126. TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
  127. TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
  128. /* 0x18 */
  129. TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
  130. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
  131. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
  132. TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
  133. TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
  134. TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
  135. TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
  136. TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
  137. /* 0x20 */
  138. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
  139. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  140. TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
  141. TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
  142. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  143. TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
  144. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
  145. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
  146. /* 0x28 */
  147. TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
  148. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  149. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  150. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  151. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  152. TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
  153. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
  154. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
  155. /* 0x30 */
  156. TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
  157. TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
  158. TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
  159. TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
  160. TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
  161. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
  162. TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
  163. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  164. /* 0x38h */ /* Jumps to reg offset 0x3B0h */
  165. TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
  166. TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
  167. TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
  168. TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
  169. TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
  170. TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
  171. TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
  172. TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
  173. /* 0x40 */
  174. TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
  175. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  176. TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
  177. TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
  178. TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
  179. TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
  180. TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
  181. TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
  182. /* 0x48 */
  183. TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
  184. TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
  185. TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
  186. TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
  187. TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
  188. TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
  189. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  190. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  191. /* 0x50 */
  192. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  193. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  194. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  195. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  196. TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
  197. TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
  198. TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
  199. };
  200. /*
  201. * This array translates a periph_id to a periphc_internal_id
  202. *
  203. * Not present/matched up:
  204. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  205. * SPDIF - which is both 0x08 and 0x0c
  206. *
  207. */
  208. #define NONE(name) (-1)
  209. #define OFFSET(name, value) PERIPHC_ ## name
  210. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  211. /* Low word: 31:0 */
  212. NONE(CPU),
  213. NONE(COP),
  214. NONE(TRIGSYS),
  215. NONE(RESERVED3),
  216. NONE(RTC),
  217. NONE(TMR),
  218. PERIPHC_UART1,
  219. PERIPHC_UART2, /* and vfir 0x68 */
  220. /* 8 */
  221. NONE(GPIO),
  222. PERIPHC_SDMMC2,
  223. NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
  224. PERIPHC_I2S1,
  225. PERIPHC_I2C1,
  226. PERIPHC_NDFLASH,
  227. PERIPHC_SDMMC1,
  228. PERIPHC_SDMMC4,
  229. /* 16 */
  230. NONE(RESERVED16),
  231. PERIPHC_PWM,
  232. PERIPHC_I2S2,
  233. PERIPHC_EPP,
  234. PERIPHC_VI,
  235. PERIPHC_G2D,
  236. NONE(USBD),
  237. NONE(ISP),
  238. /* 24 */
  239. PERIPHC_G3D,
  240. NONE(RESERVED25),
  241. PERIPHC_DISP2,
  242. PERIPHC_DISP1,
  243. PERIPHC_HOST1X,
  244. NONE(VCP),
  245. PERIPHC_I2S0,
  246. NONE(CACHE2),
  247. /* Middle word: 63:32 */
  248. NONE(MEM),
  249. NONE(AHBDMA),
  250. NONE(APBDMA),
  251. NONE(RESERVED35),
  252. NONE(RESERVED36),
  253. NONE(STAT_MON),
  254. NONE(RESERVED38),
  255. NONE(RESERVED39),
  256. /* 40 */
  257. NONE(KFUSE),
  258. NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
  259. PERIPHC_NOR,
  260. NONE(RESERVED43),
  261. PERIPHC_SBC2,
  262. NONE(RESERVED45),
  263. PERIPHC_SBC3,
  264. PERIPHC_I2C5,
  265. /* 48 */
  266. NONE(DSI),
  267. PERIPHC_TVO, /* also CVE 0x40 */
  268. PERIPHC_MIPI,
  269. PERIPHC_HDMI,
  270. NONE(CSI),
  271. PERIPHC_TVDAC,
  272. PERIPHC_I2C2,
  273. PERIPHC_UART3,
  274. /* 56 */
  275. NONE(RESERVED56),
  276. PERIPHC_EMC,
  277. NONE(USB2),
  278. NONE(USB3),
  279. PERIPHC_MPE,
  280. PERIPHC_VDE,
  281. NONE(BSEA),
  282. NONE(BSEV),
  283. /* Upper word 95:64 */
  284. PERIPHC_SPEEDO,
  285. PERIPHC_UART4,
  286. PERIPHC_UART5,
  287. PERIPHC_I2C3,
  288. PERIPHC_SBC4,
  289. PERIPHC_SDMMC3,
  290. NONE(PCIE),
  291. PERIPHC_OWR,
  292. /* 72 */
  293. NONE(AFI),
  294. PERIPHC_CSITE,
  295. NONE(PCIEXCLK),
  296. NONE(AVPUCQ),
  297. NONE(RESERVED76),
  298. NONE(RESERVED77),
  299. NONE(RESERVED78),
  300. NONE(DTV),
  301. /* 80 */
  302. PERIPHC_NANDSPEED,
  303. PERIPHC_I2CSLOW,
  304. NONE(DSIB),
  305. NONE(RESERVED83),
  306. NONE(IRAMA),
  307. NONE(IRAMB),
  308. NONE(IRAMC),
  309. NONE(IRAMD),
  310. /* 88 */
  311. NONE(CRAM2),
  312. NONE(RESERVED89),
  313. NONE(MDOUBLER),
  314. NONE(RESERVED91),
  315. NONE(SUSOUT),
  316. NONE(RESERVED93),
  317. NONE(RESERVED94),
  318. NONE(RESERVED95),
  319. /* V word: 31:0 */
  320. NONE(CPUG),
  321. NONE(CPULP),
  322. PERIPHC_G3D2,
  323. PERIPHC_MSELECT,
  324. PERIPHC_TSENSOR,
  325. PERIPHC_I2S3,
  326. PERIPHC_I2S4,
  327. PERIPHC_I2C4,
  328. /* 08 */
  329. PERIPHC_SBC5,
  330. PERIPHC_SBC6,
  331. PERIPHC_AUDIO,
  332. NONE(APBIF),
  333. PERIPHC_DAM0,
  334. PERIPHC_DAM1,
  335. PERIPHC_DAM2,
  336. PERIPHC_HDA2CODEC2X,
  337. /* 16 */
  338. NONE(ATOMICS),
  339. NONE(RESERVED17),
  340. NONE(RESERVED18),
  341. NONE(RESERVED19),
  342. NONE(RESERVED20),
  343. NONE(RESERVED21),
  344. NONE(RESERVED22),
  345. PERIPHC_ACTMON,
  346. /* 24 */
  347. NONE(RESERVED24),
  348. NONE(RESERVED25),
  349. NONE(RESERVED26),
  350. NONE(RESERVED27),
  351. PERIPHC_SATA,
  352. PERIPHC_HDA,
  353. NONE(RESERVED30),
  354. NONE(RESERVED31),
  355. /* W word: 31:0 */
  356. NONE(HDA2HDMICODEC),
  357. NONE(RESERVED1_SATACOLD),
  358. NONE(RESERVED2_PCIERX0),
  359. NONE(RESERVED3_PCIERX1),
  360. NONE(RESERVED4_PCIERX2),
  361. NONE(RESERVED5_PCIERX3),
  362. NONE(RESERVED6_PCIERX4),
  363. NONE(RESERVED7_PCIERX5),
  364. /* 40 */
  365. NONE(CEC),
  366. NONE(PCIE2_IOBIST),
  367. NONE(EMC_IOBIST),
  368. NONE(HDMI_IOBIST),
  369. NONE(SATA_IOBIST),
  370. NONE(MIPI_IOBIST),
  371. NONE(EMC1_IOBIST),
  372. NONE(XUSB),
  373. /* 48 */
  374. NONE(CILAB),
  375. NONE(CILCD),
  376. NONE(CILE),
  377. NONE(DSIA_LP),
  378. NONE(DSIB_LP),
  379. NONE(RESERVED21_ENTROPY),
  380. NONE(RESERVED22_W),
  381. NONE(RESERVED23_W),
  382. /* 56 */
  383. NONE(RESERVED24_W),
  384. NONE(AMX0),
  385. NONE(ADX0),
  386. NONE(DVFS),
  387. NONE(XUSB_SS),
  388. NONE(EMC_DLL),
  389. NONE(MC1),
  390. NONE(EMC1),
  391. };
  392. /*
  393. * PLL divider shift/mask tables for all PLL IDs.
  394. */
  395. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  396. /*
  397. * T114: some deviations from T2x/T30.
  398. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
  399. * If lock_ena or lock_det are >31, they're not used in that PLL.
  400. */
  401. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
  402. .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
  403. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  404. .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  405. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  406. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
  407. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  408. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
  409. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
  410. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
  411. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  412. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
  413. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
  414. .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
  415. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  416. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  417. { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  418. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
  419. };
  420. /*
  421. * Get the oscillator frequency, from the corresponding hardware configuration
  422. * field. Note that T30/T114 support 3 new higher freqs, but we map back
  423. * to the old T20 freqs. Support for the higher oscillators is TBD.
  424. */
  425. enum clock_osc_freq clock_get_osc_freq(void)
  426. {
  427. struct clk_rst_ctlr *clkrst =
  428. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  429. u32 reg;
  430. reg = readl(&clkrst->crc_osc_ctrl);
  431. reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  432. if (reg & 1) /* one of the newer freqs */
  433. printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
  434. return reg >> 2; /* Map to most common (T20) freqs */
  435. }
  436. /* Returns a pointer to the clock source register for a peripheral */
  437. u32 *get_periph_source_reg(enum periph_id periph_id)
  438. {
  439. struct clk_rst_ctlr *clkrst =
  440. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  441. enum periphc_internal_id internal_id;
  442. /* Coresight is a special case */
  443. if (periph_id == PERIPH_ID_CSI)
  444. return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
  445. assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
  446. internal_id = periph_id_to_internal_id[periph_id];
  447. assert(internal_id != -1);
  448. if (internal_id >= PERIPHC_VW_FIRST) {
  449. internal_id -= PERIPHC_VW_FIRST;
  450. return &clkrst->crc_clk_src_vw[internal_id];
  451. } else
  452. return &clkrst->crc_clk_src[internal_id];
  453. }
  454. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  455. int *divider_bits, int *type)
  456. {
  457. enum periphc_internal_id internal_id;
  458. if (!clock_periph_id_isvalid(periph_id))
  459. return -1;
  460. internal_id = periph_id_to_internal_id[periph_id];
  461. if (!periphc_internal_id_isvalid(internal_id))
  462. return -1;
  463. *type = clock_periph_type[internal_id];
  464. if (!clock_type_id_isvalid(*type))
  465. return -1;
  466. *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
  467. if (*type == CLOCK_TYPE_PCMT16)
  468. *divider_bits = 16;
  469. else
  470. *divider_bits = 8;
  471. return 0;
  472. }
  473. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  474. {
  475. enum periphc_internal_id internal_id;
  476. int type;
  477. if (!clock_periph_id_isvalid(periph_id))
  478. return CLOCK_ID_NONE;
  479. internal_id = periph_id_to_internal_id[periph_id];
  480. if (!periphc_internal_id_isvalid(internal_id))
  481. return CLOCK_ID_NONE;
  482. type = clock_periph_type[internal_id];
  483. if (!clock_type_id_isvalid(type))
  484. return CLOCK_ID_NONE;
  485. return clock_source[type][source];
  486. }
  487. /**
  488. * Given a peripheral ID and the required source clock, this returns which
  489. * value should be programmed into the source mux for that peripheral.
  490. *
  491. * There is special code here to handle the one source type with 5 sources.
  492. *
  493. * @param periph_id peripheral to start
  494. * @param source PLL id of required parent clock
  495. * @param mux_bits Set to number of bits in mux register: 2 or 4
  496. * @param divider_bits Set to number of divider bits (8 or 16)
  497. * @return mux value (0-4, or -1 if not found)
  498. */
  499. int get_periph_clock_source(enum periph_id periph_id,
  500. enum clock_id parent, int *mux_bits, int *divider_bits)
  501. {
  502. enum clock_type_id type;
  503. int mux, err;
  504. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  505. assert(!err);
  506. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  507. if (clock_source[type][mux] == parent)
  508. return mux;
  509. /* if we get here, either us or the caller has made a mistake */
  510. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  511. parent);
  512. return -1;
  513. }
  514. void clock_set_enable(enum periph_id periph_id, int enable)
  515. {
  516. struct clk_rst_ctlr *clkrst =
  517. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  518. u32 *clk;
  519. u32 reg;
  520. /* Enable/disable the clock to this peripheral */
  521. assert(clock_periph_id_isvalid(periph_id));
  522. if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
  523. clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  524. else
  525. clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
  526. reg = readl(clk);
  527. if (enable)
  528. reg |= PERIPH_MASK(periph_id);
  529. else
  530. reg &= ~PERIPH_MASK(periph_id);
  531. writel(reg, clk);
  532. }
  533. void reset_set_enable(enum periph_id periph_id, int enable)
  534. {
  535. struct clk_rst_ctlr *clkrst =
  536. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  537. u32 *reset;
  538. u32 reg;
  539. /* Enable/disable reset to the peripheral */
  540. assert(clock_periph_id_isvalid(periph_id));
  541. if (periph_id < PERIPH_ID_VW_FIRST)
  542. reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  543. else
  544. reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
  545. reg = readl(reset);
  546. if (enable)
  547. reg |= PERIPH_MASK(periph_id);
  548. else
  549. reg &= ~PERIPH_MASK(periph_id);
  550. writel(reg, reset);
  551. }
  552. #if CONFIG_IS_ENABLED(OF_CONTROL)
  553. /*
  554. * Convert a device tree clock ID to our peripheral ID. They are mostly
  555. * the same but we are very cautious so we check that a valid clock ID is
  556. * provided.
  557. *
  558. * @param clk_id Clock ID according to tegra114 device tree binding
  559. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  560. */
  561. enum periph_id clk_id_to_periph_id(int clk_id)
  562. {
  563. if (clk_id > PERIPH_ID_COUNT)
  564. return PERIPH_ID_NONE;
  565. switch (clk_id) {
  566. case PERIPH_ID_RESERVED3:
  567. case PERIPH_ID_RESERVED16:
  568. case PERIPH_ID_RESERVED24:
  569. case PERIPH_ID_RESERVED35:
  570. case PERIPH_ID_RESERVED43:
  571. case PERIPH_ID_RESERVED45:
  572. case PERIPH_ID_RESERVED56:
  573. case PERIPH_ID_RESERVED76:
  574. case PERIPH_ID_RESERVED77:
  575. case PERIPH_ID_RESERVED78:
  576. case PERIPH_ID_RESERVED83:
  577. case PERIPH_ID_RESERVED89:
  578. case PERIPH_ID_RESERVED91:
  579. case PERIPH_ID_RESERVED93:
  580. case PERIPH_ID_RESERVED94:
  581. case PERIPH_ID_RESERVED95:
  582. return PERIPH_ID_NONE;
  583. default:
  584. return clk_id;
  585. }
  586. }
  587. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  588. void clock_early_init(void)
  589. {
  590. struct clk_rst_ctlr *clkrst =
  591. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  592. struct clk_pll_info *pllinfo;
  593. u32 data;
  594. tegra30_set_up_pllp();
  595. /* clear IDDQ before accessing any other PLLC registers */
  596. pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
  597. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
  598. udelay(2);
  599. /*
  600. * PLLC output frequency set to 600Mhz
  601. * PLLD output frequency set to 925Mhz
  602. */
  603. switch (clock_get_osc_freq()) {
  604. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  605. clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
  606. clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
  607. break;
  608. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  609. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  610. clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
  611. break;
  612. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  613. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  614. clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
  615. break;
  616. case CLOCK_OSC_FREQ_19_2:
  617. default:
  618. /*
  619. * These are not supported. It is too early to print a
  620. * message and the UART likely won't work anyway due to the
  621. * oscillator being wrong.
  622. */
  623. break;
  624. }
  625. /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
  626. writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
  627. /* PLLC_MISC: Set LOCK_ENABLE */
  628. pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
  629. setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
  630. udelay(2);
  631. /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
  632. pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
  633. data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
  634. data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
  635. writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
  636. udelay(2);
  637. }
  638. void arch_timer_init(void)
  639. {
  640. struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
  641. u32 freq, val;
  642. freq = clock_get_rate(CLOCK_ID_CLK_M);
  643. debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
  644. /* ARM CNTFRQ */
  645. asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
  646. /* Only T114 has the System Counter regs */
  647. debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
  648. writel(freq, &sysctr->cntfid0);
  649. val = readl(&sysctr->cntcr);
  650. val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
  651. writel(val, &sysctr->cntcr);
  652. debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
  653. }
  654. struct periph_clk_init periph_clk_init_table[] = {
  655. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  656. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  657. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  658. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  659. { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
  660. { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
  661. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  662. { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
  663. { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
  664. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  665. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  666. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  667. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  668. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  669. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  670. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  671. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  672. { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
  673. { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
  674. { -1, },
  675. };