clock.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. /* Tegra SoC common clock control functions */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/tegra.h>
  15. #include <asm/arch-tegra/ap.h>
  16. #include <asm/arch-tegra/clk_rst.h>
  17. #include <asm/arch-tegra/pmc.h>
  18. #include <asm/arch-tegra/timer.h>
  19. #include <linux/delay.h>
  20. /*
  21. * This is our record of the current clock rate of each clock. We don't
  22. * fill all of these in since we are only really interested in clocks which
  23. * we use as parents.
  24. */
  25. static unsigned pll_rate[CLOCK_ID_COUNT];
  26. /*
  27. * The oscillator frequency is fixed to one of four set values. Based on this
  28. * the other clocks are set up appropriately.
  29. */
  30. static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
  31. 13000000,
  32. 19200000,
  33. 12000000,
  34. 26000000,
  35. 38400000,
  36. 48000000,
  37. };
  38. /* return 1 if a peripheral ID is in range */
  39. #define clock_type_id_isvalid(id) ((id) >= 0 && \
  40. (id) < CLOCK_TYPE_COUNT)
  41. char pllp_valid = 1; /* PLLP is set up correctly */
  42. /* return 1 if a periphc_internal_id is in range */
  43. #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
  44. (id) < PERIPHC_COUNT)
  45. /* number of clock outputs of a PLL */
  46. static const u8 pll_num_clkouts[] = {
  47. 1, /* PLLC */
  48. 1, /* PLLM */
  49. 4, /* PLLP */
  50. 1, /* PLLA */
  51. 0, /* PLLU */
  52. 0, /* PLLD */
  53. };
  54. int clock_get_osc_bypass(void)
  55. {
  56. struct clk_rst_ctlr *clkrst =
  57. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  58. u32 reg;
  59. reg = readl(&clkrst->crc_osc_ctrl);
  60. return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
  61. }
  62. /* Returns a pointer to the registers of the given pll */
  63. static struct clk_pll *get_pll(enum clock_id clkid)
  64. {
  65. struct clk_rst_ctlr *clkrst =
  66. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  67. assert(clock_id_is_pll(clkid));
  68. if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
  69. debug("%s: Invalid PLL %d\n", __func__, clkid);
  70. return NULL;
  71. }
  72. return &clkrst->crc_pll[clkid];
  73. }
  74. __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
  75. {
  76. return NULL;
  77. }
  78. int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
  79. u32 *divp, u32 *cpcon, u32 *lfcon)
  80. {
  81. struct clk_pll *pll = get_pll(clkid);
  82. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  83. u32 data;
  84. assert(clkid != CLOCK_ID_USB);
  85. /* Safety check, adds to code size but is small */
  86. if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
  87. return -1;
  88. data = readl(&pll->pll_base);
  89. *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
  90. *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
  91. *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
  92. data = readl(&pll->pll_misc);
  93. /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
  94. *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
  95. *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
  96. return 0;
  97. }
  98. unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
  99. u32 divp, u32 cpcon, u32 lfcon)
  100. {
  101. struct clk_pll *pll = NULL;
  102. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  103. struct clk_pll_simple *simple_pll = NULL;
  104. u32 misc_data, data;
  105. if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
  106. pll = get_pll(clkid);
  107. } else {
  108. simple_pll = clock_get_simple_pll(clkid);
  109. if (!simple_pll) {
  110. debug("%s: Uknown simple PLL %d\n", __func__, clkid);
  111. return 0;
  112. }
  113. }
  114. /*
  115. * pllinfo has the m/n/p and kcp/kvco mask and shift
  116. * values for all of the PLLs used in U-Boot, with any
  117. * SoC differences accounted for.
  118. *
  119. * Preserve EN_LOCKDET, etc.
  120. */
  121. if (pll)
  122. misc_data = readl(&pll->pll_misc);
  123. else
  124. misc_data = readl(&simple_pll->pll_misc);
  125. misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  126. misc_data |= cpcon << pllinfo->kcp_shift;
  127. misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
  128. misc_data |= lfcon << pllinfo->kvco_shift;
  129. data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
  130. data |= divp << pllinfo->p_shift;
  131. data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
  132. if (pll) {
  133. writel(misc_data, &pll->pll_misc);
  134. writel(data, &pll->pll_base);
  135. } else {
  136. writel(misc_data, &simple_pll->pll_misc);
  137. writel(data, &simple_pll->pll_base);
  138. }
  139. /* calculate the stable time */
  140. return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
  141. }
  142. void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
  143. unsigned divisor)
  144. {
  145. u32 *reg = get_periph_source_reg(periph_id);
  146. u32 value;
  147. value = readl(reg);
  148. value &= ~OUT_CLK_SOURCE_31_30_MASK;
  149. value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
  150. value &= ~OUT_CLK_DIVISOR_MASK;
  151. value |= divisor << OUT_CLK_DIVISOR_SHIFT;
  152. writel(value, reg);
  153. }
  154. int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
  155. unsigned source)
  156. {
  157. u32 *reg = get_periph_source_reg(periph_id);
  158. switch (mux_bits) {
  159. case MASK_BITS_31_30:
  160. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
  161. source << OUT_CLK_SOURCE_31_30_SHIFT);
  162. break;
  163. case MASK_BITS_31_29:
  164. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
  165. source << OUT_CLK_SOURCE_31_29_SHIFT);
  166. break;
  167. case MASK_BITS_31_28:
  168. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
  169. source << OUT_CLK_SOURCE_31_28_SHIFT);
  170. break;
  171. default:
  172. return -1;
  173. }
  174. return 0;
  175. }
  176. static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
  177. {
  178. u32 *reg = get_periph_source_reg(periph_id);
  179. u32 val = readl(reg);
  180. switch (mux_bits) {
  181. case MASK_BITS_31_30:
  182. val >>= OUT_CLK_SOURCE_31_30_SHIFT;
  183. val &= OUT_CLK_SOURCE_31_30_MASK;
  184. return val;
  185. case MASK_BITS_31_29:
  186. val >>= OUT_CLK_SOURCE_31_29_SHIFT;
  187. val &= OUT_CLK_SOURCE_31_29_MASK;
  188. return val;
  189. case MASK_BITS_31_28:
  190. val >>= OUT_CLK_SOURCE_31_28_SHIFT;
  191. val &= OUT_CLK_SOURCE_31_28_MASK;
  192. return val;
  193. default:
  194. return -1;
  195. }
  196. }
  197. void clock_ll_set_source(enum periph_id periph_id, unsigned source)
  198. {
  199. clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
  200. }
  201. /**
  202. * Given the parent's rate and the required rate for the children, this works
  203. * out the peripheral clock divider to use, in 7.1 binary format.
  204. *
  205. * @param divider_bits number of divider bits (8 or 16)
  206. * @param parent_rate clock rate of parent clock in Hz
  207. * @param rate required clock rate for this clock
  208. * @return divider which should be used
  209. */
  210. static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
  211. unsigned long rate)
  212. {
  213. u64 divider = parent_rate * 2;
  214. unsigned max_divider = 1 << divider_bits;
  215. divider += rate - 1;
  216. do_div(divider, rate);
  217. if ((s64)divider - 2 < 0)
  218. return 0;
  219. if ((s64)divider - 2 >= max_divider)
  220. return -1;
  221. return divider - 2;
  222. }
  223. int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
  224. {
  225. struct clk_pll *pll = get_pll(clkid);
  226. int data = 0, div = 0, offset = 0;
  227. if (!clock_id_is_pll(clkid))
  228. return -1;
  229. if (pllout + 1 > pll_num_clkouts[clkid])
  230. return -1;
  231. div = clk_get_divider(8, pll_rate[clkid], rate);
  232. if (div < 0)
  233. return -1;
  234. /* out2 and out4 are in the high part of the register */
  235. if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
  236. offset = 16;
  237. data = (div << PLL_OUT_RATIO_SHIFT) |
  238. PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
  239. clrsetbits_le32(&pll->pll_out[pllout >> 1],
  240. PLL_OUT_RATIO_MASK << offset, data << offset);
  241. return 0;
  242. }
  243. /**
  244. * Given the parent's rate and the divider in 7.1 format, this works out the
  245. * resulting peripheral clock rate.
  246. *
  247. * @param parent_rate clock rate of parent clock in Hz
  248. * @param divider which should be used in 7.1 format
  249. * @return effective clock rate of peripheral
  250. */
  251. static unsigned long get_rate_from_divider(unsigned long parent_rate,
  252. int divider)
  253. {
  254. u64 rate;
  255. rate = (u64)parent_rate * 2;
  256. do_div(rate, divider + 2);
  257. return rate;
  258. }
  259. unsigned long clock_get_periph_rate(enum periph_id periph_id,
  260. enum clock_id parent)
  261. {
  262. u32 *reg = get_periph_source_reg(periph_id);
  263. unsigned parent_rate = pll_rate[parent];
  264. int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
  265. switch (periph_id) {
  266. case PERIPH_ID_UART1:
  267. case PERIPH_ID_UART2:
  268. case PERIPH_ID_UART3:
  269. case PERIPH_ID_UART4:
  270. case PERIPH_ID_UART5:
  271. #ifdef CONFIG_TEGRA20
  272. /* There's no divider for these clocks in this SoC. */
  273. return parent_rate;
  274. #else
  275. /*
  276. * This undoes the +2 in get_rate_from_divider() which I
  277. * believe is incorrect. Ideally we would fix
  278. * get_rate_from_divider(), but... Removing the +2 from
  279. * get_rate_from_divider() would probably require remove the -2
  280. * from the tail of clk_get_divider() since I believe that's
  281. * only there to invert get_rate_from_divider()'s +2. Observe
  282. * how find_best_divider() uses those two functions together.
  283. * However, doing so breaks other stuff, such as Seaboard's
  284. * display, likely due to clock_set_pllout()'s call to
  285. * clk_get_divider(). Attempting to fix that by making
  286. * clock_set_pllout() subtract 2 from clk_get_divider()'s
  287. * return value doesn't help. In summary this clock driver is
  288. * quite broken but I'm afraid I have no idea how to fix it
  289. * without completely replacing it.
  290. *
  291. * Be careful to avoid a divide by zero error.
  292. */
  293. if (div >= 1)
  294. div -= 2;
  295. break;
  296. #endif
  297. default:
  298. break;
  299. }
  300. return get_rate_from_divider(parent_rate, div);
  301. }
  302. /**
  303. * Find the best available 7.1 format divisor given a parent clock rate and
  304. * required child clock rate. This function assumes that a second-stage
  305. * divisor is available which can divide by powers of 2 from 1 to 256.
  306. *
  307. * @param divider_bits number of divider bits (8 or 16)
  308. * @param parent_rate clock rate of parent clock in Hz
  309. * @param rate required clock rate for this clock
  310. * @param extra_div value for the second-stage divisor (not set if this
  311. * function returns -1.
  312. * @return divider which should be used, or -1 if nothing is valid
  313. *
  314. */
  315. static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
  316. unsigned long rate, int *extra_div)
  317. {
  318. int shift;
  319. int best_divider = -1;
  320. int best_error = rate;
  321. /* try dividers from 1 to 256 and find closest match */
  322. for (shift = 0; shift <= 8 && best_error > 0; shift++) {
  323. unsigned divided_parent = parent_rate >> shift;
  324. int divider = clk_get_divider(divider_bits, divided_parent,
  325. rate);
  326. unsigned effective_rate = get_rate_from_divider(divided_parent,
  327. divider);
  328. int error = rate - effective_rate;
  329. /* Given a valid divider, look for the lowest error */
  330. if (divider != -1 && error < best_error) {
  331. best_error = error;
  332. *extra_div = 1 << shift;
  333. best_divider = divider;
  334. }
  335. }
  336. /* return what we found - *extra_div will already be set */
  337. return best_divider;
  338. }
  339. /**
  340. * Adjust peripheral PLL to use the given divider and source.
  341. *
  342. * @param periph_id peripheral to adjust
  343. * @param source Source number (0-3 or 0-7)
  344. * @param mux_bits Number of mux bits (2 or 4)
  345. * @param divider Required divider in 7.1 or 15.1 format
  346. * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
  347. * for this peripheral)
  348. */
  349. static int adjust_periph_pll(enum periph_id periph_id, int source,
  350. int mux_bits, unsigned divider)
  351. {
  352. u32 *reg = get_periph_source_reg(periph_id);
  353. clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
  354. divider << OUT_CLK_DIVISOR_SHIFT);
  355. udelay(1);
  356. /* work out the source clock and set it */
  357. if (source < 0)
  358. return -1;
  359. clock_ll_set_source_bits(periph_id, mux_bits, source);
  360. udelay(2);
  361. return 0;
  362. }
  363. enum clock_id clock_get_periph_parent(enum periph_id periph_id)
  364. {
  365. int err, mux_bits, divider_bits, type;
  366. int source;
  367. err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);
  368. if (err)
  369. return CLOCK_ID_NONE;
  370. source = clock_ll_get_source_bits(periph_id, mux_bits);
  371. return get_periph_clock_id(periph_id, source);
  372. }
  373. unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
  374. enum clock_id parent, unsigned rate, int *extra_div)
  375. {
  376. unsigned effective_rate;
  377. int mux_bits, divider_bits, source;
  378. int divider;
  379. int xdiv = 0;
  380. /* work out the source clock and set it */
  381. source = get_periph_clock_source(periph_id, parent, &mux_bits,
  382. &divider_bits);
  383. divider = find_best_divider(divider_bits, pll_rate[parent],
  384. rate, &xdiv);
  385. if (extra_div)
  386. *extra_div = xdiv;
  387. assert(divider >= 0);
  388. if (adjust_periph_pll(periph_id, source, mux_bits, divider))
  389. return -1U;
  390. debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
  391. get_periph_source_reg(periph_id),
  392. readl(get_periph_source_reg(periph_id)));
  393. /* Check what we ended up with. This shouldn't matter though */
  394. effective_rate = clock_get_periph_rate(periph_id, parent);
  395. if (extra_div)
  396. effective_rate /= *extra_div;
  397. if (rate != effective_rate)
  398. debug("Requested clock rate %u not honored (got %u)\n",
  399. rate, effective_rate);
  400. return effective_rate;
  401. }
  402. unsigned clock_start_periph_pll(enum periph_id periph_id,
  403. enum clock_id parent, unsigned rate)
  404. {
  405. unsigned effective_rate;
  406. reset_set_enable(periph_id, 1);
  407. clock_enable(periph_id);
  408. udelay(2);
  409. effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
  410. NULL);
  411. reset_set_enable(periph_id, 0);
  412. return effective_rate;
  413. }
  414. void clock_enable(enum periph_id clkid)
  415. {
  416. clock_set_enable(clkid, 1);
  417. }
  418. void clock_disable(enum periph_id clkid)
  419. {
  420. clock_set_enable(clkid, 0);
  421. }
  422. void reset_periph(enum periph_id periph_id, int us_delay)
  423. {
  424. /* Put peripheral into reset */
  425. reset_set_enable(periph_id, 1);
  426. udelay(us_delay);
  427. /* Remove reset */
  428. reset_set_enable(periph_id, 0);
  429. udelay(us_delay);
  430. }
  431. void reset_cmplx_set_enable(int cpu, int which, int reset)
  432. {
  433. struct clk_rst_ctlr *clkrst =
  434. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  435. u32 mask;
  436. /* Form the mask, which depends on the cpu chosen (2 or 4) */
  437. assert(cpu >= 0 && cpu < MAX_NUM_CPU);
  438. mask = which << cpu;
  439. /* either enable or disable those reset for that CPU */
  440. if (reset)
  441. writel(mask, &clkrst->crc_cpu_cmplx_set);
  442. else
  443. writel(mask, &clkrst->crc_cpu_cmplx_clr);
  444. }
  445. unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
  446. {
  447. return parent_rate;
  448. }
  449. unsigned clock_get_rate(enum clock_id clkid)
  450. {
  451. struct clk_pll *pll;
  452. u32 base, divm;
  453. u64 parent_rate, rate;
  454. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  455. parent_rate = osc_freq[clock_get_osc_freq()];
  456. if (clkid == CLOCK_ID_OSC)
  457. return parent_rate;
  458. if (clkid == CLOCK_ID_CLK_M)
  459. return clk_m_get_rate(parent_rate);
  460. pll = get_pll(clkid);
  461. if (!pll)
  462. return 0;
  463. base = readl(&pll->pll_base);
  464. rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
  465. divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
  466. /*
  467. * PLLU uses p_mask/p_shift for VCO on all but T210,
  468. * T210 uses normal DIVP. Handled in pllinfo table.
  469. */
  470. #ifdef CONFIG_TEGRA210
  471. /*
  472. * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
  473. * not applied. pllP_out2 does have divp applied. All other pllP_outN
  474. * are divided down from pllP_out0. We only support pllP_out0 in
  475. * U-Boot at the time of writing this comment.
  476. */
  477. if (clkid != CLOCK_ID_PERIPH)
  478. #endif
  479. divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
  480. do_div(rate, divm);
  481. return rate;
  482. }
  483. /**
  484. * Set the output frequency you want for each PLL clock.
  485. * PLL output frequencies are programmed by setting their N, M and P values.
  486. * The governing equations are:
  487. * VCO = (Fi / m) * n, Fo = VCO / (2^p)
  488. * where Fo is the output frequency from the PLL.
  489. * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
  490. * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
  491. * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
  492. *
  493. * @param n PLL feedback divider(DIVN)
  494. * @param m PLL input divider(DIVN)
  495. * @param p post divider(DIVP)
  496. * @param cpcon base PLL charge pump(CPCON)
  497. * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
  498. * be overridden), 1 if PLL is already correct
  499. */
  500. int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
  501. {
  502. u32 base_reg, misc_reg;
  503. struct clk_pll *pll;
  504. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  505. pll = get_pll(clkid);
  506. base_reg = readl(&pll->pll_base);
  507. /* Set BYPASS, m, n and p to PLL_BASE */
  508. base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
  509. base_reg |= m << pllinfo->m_shift;
  510. base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
  511. base_reg |= n << pllinfo->n_shift;
  512. base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
  513. base_reg |= p << pllinfo->p_shift;
  514. if (clkid == CLOCK_ID_PERIPH) {
  515. /*
  516. * If the PLL is already set up, check that it is correct
  517. * and record this info for clock_verify() to check.
  518. */
  519. if (base_reg & PLL_BASE_OVRRIDE_MASK) {
  520. base_reg |= PLL_ENABLE_MASK;
  521. if (base_reg != readl(&pll->pll_base))
  522. pllp_valid = 0;
  523. return pllp_valid ? 1 : -1;
  524. }
  525. base_reg |= PLL_BASE_OVRRIDE_MASK;
  526. }
  527. base_reg |= PLL_BYPASS_MASK;
  528. writel(base_reg, &pll->pll_base);
  529. /* Set cpcon (KCP) to PLL_MISC */
  530. misc_reg = readl(&pll->pll_misc);
  531. misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  532. misc_reg |= cpcon << pllinfo->kcp_shift;
  533. writel(misc_reg, &pll->pll_misc);
  534. /* Enable PLL */
  535. base_reg |= PLL_ENABLE_MASK;
  536. writel(base_reg, &pll->pll_base);
  537. /* Disable BYPASS */
  538. base_reg &= ~PLL_BYPASS_MASK;
  539. writel(base_reg, &pll->pll_base);
  540. return 0;
  541. }
  542. void clock_ll_start_uart(enum periph_id periph_id)
  543. {
  544. /* Assert UART reset and enable clock */
  545. reset_set_enable(periph_id, 1);
  546. clock_enable(periph_id);
  547. clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
  548. /* wait for 2us */
  549. udelay(2);
  550. /* De-assert reset to UART */
  551. reset_set_enable(periph_id, 0);
  552. }
  553. #if CONFIG_IS_ENABLED(OF_CONTROL)
  554. int clock_decode_periph_id(struct udevice *dev)
  555. {
  556. enum periph_id id;
  557. u32 cell[2];
  558. int err;
  559. err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
  560. if (err)
  561. return -1;
  562. id = clk_id_to_periph_id(cell[1]);
  563. assert(clock_periph_id_isvalid(id));
  564. return id;
  565. }
  566. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  567. int clock_verify(void)
  568. {
  569. struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
  570. u32 reg = readl(&pll->pll_base);
  571. if (!pllp_valid) {
  572. printf("Warning: PLLP %x is not correct\n", reg);
  573. return -1;
  574. }
  575. debug("PLLP %x is correct\n", reg);
  576. return 0;
  577. }
  578. void clock_init(void)
  579. {
  580. int i;
  581. pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
  582. pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
  583. pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
  584. pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
  585. pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
  586. pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
  587. pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
  588. pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
  589. pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
  590. debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
  591. debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
  592. debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
  593. debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
  594. debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
  595. debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
  596. debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
  597. debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
  598. for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
  599. enum periph_id periph_id;
  600. enum clock_id parent;
  601. int source, mux_bits, divider_bits;
  602. periph_id = periph_clk_init_table[i].periph_id;
  603. parent = periph_clk_init_table[i].parent_clock_id;
  604. source = get_periph_clock_source(periph_id, parent, &mux_bits,
  605. &divider_bits);
  606. clock_ll_set_source_bits(periph_id, mux_bits, source);
  607. }
  608. }
  609. static void set_avp_clock_source(u32 src)
  610. {
  611. struct clk_rst_ctlr *clkrst =
  612. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  613. u32 val;
  614. val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
  615. (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
  616. (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
  617. (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
  618. (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
  619. writel(val, &clkrst->crc_sclk_brst_pol);
  620. udelay(3);
  621. }
  622. /*
  623. * This function is useful on Tegra30, and any later SoCs that have compatible
  624. * PLLP configuration registers.
  625. * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
  626. */
  627. void tegra30_set_up_pllp(void)
  628. {
  629. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  630. u32 reg;
  631. /*
  632. * Based on the Tegra TRM, the system clock (which is the AVP clock) can
  633. * run up to 275MHz. On power on, the default sytem clock source is set
  634. * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
  635. * 408MHz which is beyond system clock's upper limit.
  636. *
  637. * The fix is to set the system clock to CLK_M before initializing PLLP,
  638. * and then switch back to PLLP_OUT4, which has an appropriate divider
  639. * configured, after PLLP has been configured
  640. */
  641. set_avp_clock_source(SCLK_SOURCE_CLKM);
  642. /*
  643. * PLLP output frequency set to 408Mhz
  644. * PLLC output frequency set to 228Mhz
  645. */
  646. switch (clock_get_osc_freq()) {
  647. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  648. clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
  649. clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
  650. break;
  651. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  652. clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
  653. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  654. break;
  655. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  656. clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
  657. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  658. break;
  659. case CLOCK_OSC_FREQ_19_2:
  660. default:
  661. /*
  662. * These are not supported. It is too early to print a
  663. * message and the UART likely won't work anyway due to the
  664. * oscillator being wrong.
  665. */
  666. break;
  667. }
  668. /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
  669. /* OUT1, 2 */
  670. /* Assert RSTN before enable */
  671. reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
  672. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  673. /* Set divisor and reenable */
  674. reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
  675. | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
  676. | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
  677. | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
  678. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  679. /* OUT3, 4 */
  680. /* Assert RSTN before enable */
  681. reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
  682. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  683. /* Set divisor and reenable */
  684. reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
  685. | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
  686. | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
  687. | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
  688. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  689. set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
  690. }
  691. int clock_external_output(int clk_id)
  692. {
  693. u32 val;
  694. if (clk_id >= 1 && clk_id <= 3) {
  695. val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
  696. pmc_clk_out_cntrl));
  697. val |= 1 << (2 + (clk_id - 1) * 8);
  698. tegra_pmc_writel(val,
  699. offsetof(struct pmc_ctlr,
  700. pmc_clk_out_cntrl));
  701. } else {
  702. printf("%s: Unknown output clock id %d\n", __func__, clk_id);
  703. return -EINVAL;
  704. }
  705. return 0;
  706. }
  707. __weak bool clock_early_init_done(void)
  708. {
  709. return true;
  710. }