dram_sun8i_a83t.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Sun8i a33 platform dram controller init.
  4. *
  5. * (C) Copyright 2007-2015 Allwinner Technology Co.
  6. * Jerry Wang <wangflord@allwinnertech.com>
  7. * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
  8. * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/dram.h>
  16. #include <asm/arch/prcm.h>
  17. #include <linux/delay.h>
  18. #define DRAM_CLK_MUL 2
  19. #define DRAM_CLK_DIV 1
  20. struct dram_para {
  21. u8 cs1;
  22. u8 seq;
  23. u8 bank;
  24. u8 rank;
  25. u8 rows;
  26. u8 bus_width;
  27. u8 dram_type;
  28. u16 page_size;
  29. };
  30. static void mctl_set_cr(struct dram_para *para)
  31. {
  32. struct sunxi_mctl_com_reg * const mctl_com =
  33. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  34. writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
  35. MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
  36. (para->seq ? MCTL_CR_SEQUENCE : 0) |
  37. ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
  38. MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
  39. MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
  40. &mctl_com->cr);
  41. }
  42. static void auto_detect_dram_size(struct dram_para *para)
  43. {
  44. u8 orig_rank = para->rank;
  45. int rows, columns;
  46. /* Row detect */
  47. para->page_size = 512;
  48. para->seq = 1;
  49. para->rows = 16;
  50. para->rank = 1;
  51. mctl_set_cr(para);
  52. for (rows = 11 ; rows < 16 ; rows++) {
  53. if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
  54. break;
  55. }
  56. /* Column (page size) detect */
  57. para->rows = 11;
  58. para->page_size = 8192;
  59. mctl_set_cr(para);
  60. for (columns = 9 ; columns < 13 ; columns++) {
  61. if (mctl_mem_matches(1 << columns))
  62. break;
  63. }
  64. para->seq = 0;
  65. para->rank = orig_rank;
  66. para->rows = rows;
  67. para->page_size = 1 << columns;
  68. mctl_set_cr(para);
  69. }
  70. static inline int ns_to_t(int nanoseconds)
  71. {
  72. const unsigned int ctrl_freq =
  73. CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
  74. return (ctrl_freq * nanoseconds + 999) / 1000;
  75. }
  76. static void auto_set_timing_para(struct dram_para *para)
  77. {
  78. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  79. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  80. u32 reg_val;
  81. u8 tccd = 2;
  82. u8 tfaw = ns_to_t(50);
  83. u8 trrd = max(ns_to_t(10), 4);
  84. u8 trcd = ns_to_t(15);
  85. u8 trc = ns_to_t(53);
  86. u8 txp = max(ns_to_t(8), 3);
  87. u8 twtr = max(ns_to_t(8), 4);
  88. u8 trtp = max(ns_to_t(8), 4);
  89. u8 twr = max(ns_to_t(15), 3);
  90. u8 trp = ns_to_t(15);
  91. u8 tras = ns_to_t(38);
  92. u16 trefi = ns_to_t(7800) / 32;
  93. u16 trfc = ns_to_t(350);
  94. /* Fixed timing parameters */
  95. u8 tmrw = 0;
  96. u8 tmrd = 4;
  97. u8 tmod = 12;
  98. u8 tcke = 3;
  99. u8 tcksrx = 5;
  100. u8 tcksre = 5;
  101. u8 tckesr = 4;
  102. u8 trasmax = 24;
  103. u8 tcl = 6; /* CL 12 */
  104. u8 tcwl = 4; /* CWL 8 */
  105. u8 t_rdata_en = 4;
  106. u8 wr_latency = 2;
  107. u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
  108. u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
  109. u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
  110. u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
  111. u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
  112. u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
  113. u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
  114. /* Set work mode register */
  115. mctl_set_cr(para);
  116. /* Set mode register */
  117. if (para->dram_type == DRAM_TYPE_DDR3) {
  118. writel(MCTL_MR0, &mctl_ctl->mr0);
  119. writel(MCTL_MR1, &mctl_ctl->mr1);
  120. writel(MCTL_MR2, &mctl_ctl->mr2);
  121. writel(MCTL_MR3, &mctl_ctl->mr3);
  122. } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
  123. writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
  124. writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
  125. writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
  126. writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
  127. /* timing parameters for LPDDR3 */
  128. tfaw = max(ns_to_t(50), 4);
  129. trrd = max(ns_to_t(10), 2);
  130. trcd = max(ns_to_t(24), 2);
  131. trc = ns_to_t(70);
  132. txp = max(ns_to_t(8), 2);
  133. twtr = max(ns_to_t(8), 2);
  134. trtp = max(ns_to_t(8), 2);
  135. trp = max(ns_to_t(27), 2);
  136. tras = ns_to_t(42);
  137. trefi = ns_to_t(3900) / 32;
  138. trfc = ns_to_t(210);
  139. tmrw = 5;
  140. tmrd = 5;
  141. tckesr = 5;
  142. tcwl = 3; /* CWL 8 */
  143. t_rdata_en = 5;
  144. tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
  145. tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
  146. tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
  147. tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
  148. twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
  149. twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
  150. trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
  151. }
  152. /* Set dram timing */
  153. reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
  154. writel(reg_val, &mctl_ctl->dramtmg0);
  155. reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
  156. writel(reg_val, &mctl_ctl->dramtmg1);
  157. reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
  158. writel(reg_val, &mctl_ctl->dramtmg2);
  159. reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
  160. writel(reg_val, &mctl_ctl->dramtmg3);
  161. reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
  162. writel(reg_val, &mctl_ctl->dramtmg4);
  163. reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
  164. writel(reg_val, &mctl_ctl->dramtmg5);
  165. /* Set two rank timing and exit self-refresh timing */
  166. reg_val = readl(&mctl_ctl->dramtmg8);
  167. reg_val &= ~(0xff << 8);
  168. reg_val &= ~(0xff << 0);
  169. reg_val |= (0x33 << 8);
  170. reg_val |= (0x8 << 0);
  171. writel(reg_val, &mctl_ctl->dramtmg8);
  172. /* Set phy interface time */
  173. reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
  174. | (wr_latency << 0);
  175. /* PHY interface write latency and read latency configure */
  176. writel(reg_val, &mctl_ctl->pitmg0);
  177. /* Set phy time PTR0-2 use default */
  178. writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
  179. writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
  180. /* Set refresh timing */
  181. reg_val = (trefi << 16) | (trfc << 0);
  182. writel(reg_val, &mctl_ctl->rfshtmg);
  183. }
  184. static void mctl_set_pir(u32 val)
  185. {
  186. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  187. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  188. writel(val, &mctl_ctl->pir);
  189. mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
  190. }
  191. static void mctl_data_train_cfg(struct dram_para *para)
  192. {
  193. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  194. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  195. if (para->rank == 2)
  196. clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
  197. else
  198. clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
  199. }
  200. static int mctl_train_dram(struct dram_para *para)
  201. {
  202. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  203. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  204. mctl_data_train_cfg(para);
  205. mctl_set_pir(0x5f3);
  206. return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
  207. }
  208. static void set_master_priority(void)
  209. {
  210. writel(0x00a0000d, MCTL_MASTER_CFG0(0));
  211. writel(0x00500064, MCTL_MASTER_CFG1(0));
  212. writel(0x07000009, MCTL_MASTER_CFG0(1));
  213. writel(0x00000600, MCTL_MASTER_CFG1(1));
  214. writel(0x01000009, MCTL_MASTER_CFG0(3));
  215. writel(0x00000064, MCTL_MASTER_CFG1(3));
  216. writel(0x08000009, MCTL_MASTER_CFG0(4));
  217. writel(0x00000640, MCTL_MASTER_CFG1(4));
  218. writel(0x20000308, MCTL_MASTER_CFG0(8));
  219. writel(0x00001000, MCTL_MASTER_CFG1(8));
  220. writel(0x02800009, MCTL_MASTER_CFG0(9));
  221. writel(0x00000100, MCTL_MASTER_CFG1(9));
  222. writel(0x01800009, MCTL_MASTER_CFG0(5));
  223. writel(0x00000100, MCTL_MASTER_CFG1(5));
  224. writel(0x01800009, MCTL_MASTER_CFG0(7));
  225. writel(0x00000100, MCTL_MASTER_CFG1(7));
  226. writel(0x00640009, MCTL_MASTER_CFG0(6));
  227. writel(0x00000032, MCTL_MASTER_CFG1(6));
  228. writel(0x0100000d, MCTL_MASTER_CFG0(2));
  229. writel(0x00500080, MCTL_MASTER_CFG1(2));
  230. }
  231. static int mctl_channel_init(struct dram_para *para)
  232. {
  233. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  234. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  235. struct sunxi_mctl_com_reg * const mctl_com =
  236. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  237. u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
  238. u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
  239. u32 i, rval;
  240. auto_set_timing_para(para);
  241. /* Set dram master access priority */
  242. writel(0x000101a0, &mctl_com->bwcr);
  243. /* set cpu high priority */
  244. writel(0x1, &mctl_com->mapr);
  245. set_master_priority();
  246. udelay(250);
  247. /* Disable dram VTC */
  248. clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
  249. clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
  250. writel(0x94be6fa3, MCTL_PROTECT);
  251. udelay(100);
  252. clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
  253. writel(0x0, MCTL_PROTECT);
  254. udelay(100);
  255. /* Set ODT */
  256. if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
  257. rval = 0x0;
  258. else
  259. rval = 0x2;
  260. for (i = 0 ; i < 11 ; i++) {
  261. clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
  262. rval << 24);
  263. clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
  264. rval << 24);
  265. clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
  266. rval << 24);
  267. clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
  268. rval << 24);
  269. }
  270. for (i = 0; i < 31; i++)
  271. clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
  272. /* set PLL configuration */
  273. if (CONFIG_DRAM_CLK >= 480)
  274. setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
  275. else
  276. setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
  277. /* Auto detect dram config, set 2 rank and 16bit bus-width */
  278. para->cs1 = 0;
  279. para->rank = 2;
  280. para->bus_width = 16;
  281. mctl_set_cr(para);
  282. /* Open DQS gating */
  283. clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
  284. clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
  285. if (para->dram_type == DRAM_TYPE_LPDDR3)
  286. clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
  287. 0x1 << 31);
  288. if (readl(&mctl_com->cr) & 0x1)
  289. writel(0x00000303, &mctl_ctl->odtmap);
  290. else
  291. writel(0x00000201, &mctl_ctl->odtmap);
  292. mctl_data_train_cfg(para);
  293. /* ZQ calibration */
  294. clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
  295. clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
  296. /* CA calibration */
  297. if (para->dram_type == DRAM_TYPE_DDR3)
  298. mctl_set_pir(0x0201f3 | 0x1<<10);
  299. else
  300. mctl_set_pir(0x020173 | 0x1<<10);
  301. /* DQS gate training */
  302. if (mctl_train_dram(para) != 0) {
  303. low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
  304. high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
  305. if (low_data_lines_status == 0x3)
  306. return -EIO;
  307. /* DRAM has only one rank */
  308. para->rank = 1;
  309. mctl_set_cr(para);
  310. if (low_data_lines_status == high_data_lines_status)
  311. goto done; /* 16 bit bus, 1 rank */
  312. if (!(low_data_lines_status & high_data_lines_status)) {
  313. /* Retry 16 bit bus-width with CS1 set */
  314. para->cs1 = 1;
  315. mctl_set_cr(para);
  316. if (mctl_train_dram(para) == 0)
  317. goto done;
  318. }
  319. /* Try 8 bit bus-width */
  320. writel(0x0, DXnGCR0(1)); /* Disable high DQ */
  321. para->cs1 = 0;
  322. para->bus_width = 8;
  323. mctl_set_cr(para);
  324. if (mctl_train_dram(para) != 0)
  325. return -EIO;
  326. }
  327. done:
  328. /* Check the dramc status */
  329. mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
  330. /* Close DQS gating */
  331. setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
  332. /* set PGCR3,CKE polarity */
  333. writel(0x00aa0060, &mctl_ctl->pgcr3);
  334. /* Enable master access */
  335. writel(0xffffffff, &mctl_com->maer);
  336. return 0;
  337. }
  338. static void mctl_sys_init(struct dram_para *para)
  339. {
  340. struct sunxi_ccm_reg * const ccm =
  341. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  342. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  343. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  344. clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
  345. clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
  346. clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  347. clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  348. clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
  349. udelay(1000);
  350. clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
  351. clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
  352. clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
  353. CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
  354. CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
  355. mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
  356. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  357. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  358. setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
  359. setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
  360. para->rank = 2;
  361. para->bus_width = 16;
  362. mctl_set_cr(para);
  363. /* Set dram master access priority */
  364. writel(0x0000e00f, &mctl_ctl->clken); /* normal */
  365. udelay(250);
  366. }
  367. unsigned long sunxi_dram_init(void)
  368. {
  369. struct sunxi_mctl_com_reg * const mctl_com =
  370. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  371. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  372. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  373. struct dram_para para = {
  374. .cs1 = 0,
  375. .bank = 1,
  376. .rank = 1,
  377. .rows = 15,
  378. .bus_width = 16,
  379. .page_size = 2048,
  380. };
  381. #if defined(CONFIG_MACH_SUN8I_A83T)
  382. #if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
  383. para.dram_type = CONFIG_DRAM_TYPE;
  384. #else
  385. #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
  386. #endif
  387. #endif
  388. setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
  389. writel(0, (SUNXI_PRCM_BASE + 0x1e8));
  390. udelay(10);
  391. mctl_sys_init(&para);
  392. if (mctl_channel_init(&para) != 0)
  393. return 0;
  394. auto_detect_dram_size(&para);
  395. /* Enable master software clk */
  396. writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
  397. /* Set DRAM ODT MAP */
  398. if (para.rank == 2)
  399. writel(0x00000303, &mctl_ctl->odtmap);
  400. else
  401. writel(0x00000201, &mctl_ctl->odtmap);
  402. return para.page_size * (para.bus_width / 8) *
  403. (1 << (para.bank + para.rank + para.rows));
  404. }