dram_sun8i_a23.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Sun8i platform dram controller init.
  4. *
  5. * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  6. */
  7. /*
  8. * Note this code uses a lot of magic hex values, that is because this code
  9. * simply replays the init sequence as done by the Allwinner boot0 code, so
  10. * we do not know what these values mean. There are no symbolic constants for
  11. * these magic values, since we do not know how to name them and making up
  12. * names for them is not useful.
  13. *
  14. * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
  15. * found in the TI Keystone2 documentation:
  16. * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
  17. * "Table4-2 DDR3 PHY Registers"
  18. * This may be used as a (possible) reference for future work / cleanups.
  19. */
  20. #include <common.h>
  21. #include <errno.h>
  22. #include <init.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/clock.h>
  25. #include <asm/arch/dram.h>
  26. #include <asm/arch/prcm.h>
  27. #include <linux/delay.h>
  28. static const struct dram_para dram_para = {
  29. .clock = CONFIG_DRAM_CLK,
  30. .type = 3,
  31. .zq = CONFIG_DRAM_ZQ,
  32. .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
  33. .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
  34. .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
  35. .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
  36. .mr0 = 6736,
  37. .mr1 = 4,
  38. .mr2 = 16,
  39. .mr3 = 0,
  40. /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
  41. .tpr0 = 0x2ab83def,
  42. .tpr1 = 0x18082356,
  43. .tpr2 = 0x00034156,
  44. .tpr3 = 0x448c5533,
  45. .tpr4 = 0x08010d00,
  46. .tpr5 = 0x0340b20f,
  47. .tpr6 = 0x20d118cc,
  48. .tpr7 = 0x14062485,
  49. .tpr8 = 0x220d1d52,
  50. .tpr9 = 0x1e078c22,
  51. .tpr10 = 0x3c,
  52. .tpr11 = 0, /* not used */
  53. .tpr12 = 0, /* not used */
  54. .tpr13 = 0x30000,
  55. };
  56. static void mctl_sys_init(void)
  57. {
  58. struct sunxi_ccm_reg * const ccm =
  59. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  60. /* enable pll5, note the divide by 2 is deliberate! */
  61. clock_set_pll5(dram_para.clock * 1000000 / 2,
  62. dram_para.tpr13 & 0x40000);
  63. /* deassert ahb mctl reset */
  64. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  65. /* enable ahb mctl clock */
  66. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  67. }
  68. static void mctl_apply_odt_correction(u32 *reg, int correction)
  69. {
  70. int val;
  71. val = (readl(reg) >> 8) & 0xff;
  72. val += correction;
  73. /* clamp */
  74. if (val < 0)
  75. val = 0;
  76. else if (val > 255)
  77. val = 255;
  78. clrsetbits_le32(reg, 0xff00, val << 8);
  79. }
  80. static void mctl_init(u32 *bus_width)
  81. {
  82. struct sunxi_ccm_reg * const ccm =
  83. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  84. struct sunxi_mctl_com_reg * const mctl_com =
  85. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  86. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  87. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  88. struct sunxi_mctl_phy_reg * const mctl_phy =
  89. (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  90. if (dram_para.tpr13 & 0x20)
  91. writel(0x40b, &mctl_phy->dcr);
  92. else
  93. writel(0x1000040b, &mctl_phy->dcr);
  94. if (dram_para.clock >= 480)
  95. writel(0x5c000, &mctl_phy->dllgcr);
  96. else
  97. writel(0xdc000, &mctl_phy->dllgcr);
  98. writel(0x0a003e3f, &mctl_phy->pgcr0);
  99. writel(0x03008421, &mctl_phy->pgcr1);
  100. writel(dram_para.mr0, &mctl_phy->mr0);
  101. writel(dram_para.mr1, &mctl_phy->mr1);
  102. writel(dram_para.mr2, &mctl_phy->mr2);
  103. writel(dram_para.mr3, &mctl_phy->mr3);
  104. if (!(dram_para.tpr13 & 0x10000)) {
  105. clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
  106. clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
  107. }
  108. /*
  109. * All the masking and shifting below converts what I assume are DDR
  110. * timing constants from Allwinner dram_para tpr format to the actual
  111. * timing registers format.
  112. */
  113. writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
  114. writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
  115. writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
  116. (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
  117. writel(dram_para.tpr3, &mctl_phy->dtpr0);
  118. writel(dram_para.tpr4, &mctl_phy->dtpr2);
  119. writel(0x01000081, &mctl_phy->dtcr);
  120. if (dram_para.clock <= 240 || !dram_para.odt_en) {
  121. clrbits_le32(&mctl_phy->dx0gcr, 0x600);
  122. clrbits_le32(&mctl_phy->dx1gcr, 0x600);
  123. }
  124. if (dram_para.clock <= 240) {
  125. writel(0, &mctl_phy->odtcr);
  126. writel(0, &mctl_ctl->odtmap);
  127. }
  128. writel(((dram_para.tpr5 & 0x0f00) << 12) |
  129. ((dram_para.tpr5 & 0x00f8) << 9) |
  130. ((dram_para.tpr5 & 0x0007) << 8),
  131. &mctl_ctl->rfshctl0);
  132. writel(((dram_para.tpr5 & 0x0003f000) << 12) |
  133. ((dram_para.tpr5 & 0x00fc0000) >> 2) |
  134. ((dram_para.tpr5 & 0x3f000000) >> 16) |
  135. ((dram_para.tpr6 & 0x0000003f) >> 0),
  136. &mctl_ctl->dramtmg0);
  137. writel(((dram_para.tpr6 & 0x000007c0) << 10) |
  138. ((dram_para.tpr6 & 0x0000f800) >> 3) |
  139. ((dram_para.tpr6 & 0x003f0000) >> 16),
  140. &mctl_ctl->dramtmg1);
  141. writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
  142. ((dram_para.tpr7 & 0x0000001f) << 16) |
  143. ((dram_para.tpr7 & 0x000003e0) << 3) |
  144. ((dram_para.tpr7 & 0x0000fc00) >> 10),
  145. &mctl_ctl->dramtmg2);
  146. writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
  147. ((dram_para.tpr6 & 0xf0000000) >> 16),
  148. &mctl_ctl->dramtmg3);
  149. writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
  150. ((dram_para.tpr8 & 0x00000007) << 16) |
  151. ((dram_para.tpr8 & 0x00000038) << 5) |
  152. ((dram_para.tpr8 & 0x000003c0) >> 6),
  153. &mctl_ctl->dramtmg4);
  154. writel(((dram_para.tpr8 & 0x00003c00) << 14) |
  155. ((dram_para.tpr8 & 0x0003c000) << 2) |
  156. ((dram_para.tpr8 & 0x00fc0000) >> 10) |
  157. ((dram_para.tpr8 & 0x0f000000) >> 24),
  158. &mctl_ctl->dramtmg5);
  159. writel(0x00000008, &mctl_ctl->dramtmg8);
  160. writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
  161. ((dram_para.tpr9 & 0x00007c00) << 6) |
  162. ((dram_para.tpr9 & 0x000003e0) << 3) |
  163. ((dram_para.tpr9 & 0x0000001f) >> 0),
  164. &mctl_ctl->pitmg0);
  165. setbits_le32(&mctl_ctl->pitmg1, 0x80000);
  166. writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
  167. &mctl_ctl->sched);
  168. writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
  169. writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
  170. writel(0x00000000, &mctl_ctl->pimisc);
  171. writel(0x80000000, &mctl_ctl->upd0);
  172. writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
  173. ((dram_para.tpr10 & 0x00000fff) << 16),
  174. &mctl_ctl->rfshtmg);
  175. if (dram_para.tpr13 & 0x20)
  176. writel(0x01040001, &mctl_ctl->mstr);
  177. else
  178. writel(0x01040401, &mctl_ctl->mstr);
  179. if (!(dram_para.tpr13 & 0x20000)) {
  180. writel(0x00000002, &mctl_ctl->pwrctl);
  181. writel(0x00008001, &mctl_ctl->pwrtmg);
  182. }
  183. writel(0x00000001, &mctl_ctl->rfshctl3);
  184. writel(0x00000001, &mctl_ctl->pimisc);
  185. /* deassert dram_clk_cfg reset */
  186. setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
  187. setbits_le32(&mctl_com->ccr, 0x80000);
  188. /* zq stuff */
  189. writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
  190. writel(0x00000003, &mctl_phy->pir);
  191. udelay(10);
  192. mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
  193. writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
  194. writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
  195. /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
  196. writel(0x000005f3, &mctl_phy->pir);
  197. udelay(10);
  198. mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
  199. if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
  200. *bus_width = 8;
  201. writel(0, &mctl_phy->dx1gcr);
  202. writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
  203. writel(0x5f3, &mctl_phy->pir);
  204. udelay(10000);
  205. setbits_le32(&mctl_ctl->mstr, 0x1000);
  206. } else
  207. *bus_width = 16;
  208. if (dram_para.odt_correction) {
  209. mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
  210. dram_para.odt_correction);
  211. mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
  212. dram_para.odt_correction);
  213. }
  214. mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
  215. writel(0x08003e3f, &mctl_phy->pgcr0);
  216. writel(0x00000000, &mctl_ctl->rfshctl3);
  217. }
  218. unsigned long sunxi_dram_init(void)
  219. {
  220. struct sunxi_mctl_com_reg * const mctl_com =
  221. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  222. const u32 columns = 13;
  223. u32 bus, bus_width, offset, page_size, rows;
  224. mctl_sys_init();
  225. mctl_init(&bus_width);
  226. if (bus_width == 16) {
  227. page_size = 8;
  228. bus = 1;
  229. } else {
  230. page_size = 7;
  231. bus = 0;
  232. }
  233. if (!(dram_para.tpr13 & 0x80000000)) {
  234. /* Detect and set rows */
  235. writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
  236. &mctl_com->cr);
  237. setbits_le32(&mctl_com->swonr, 0x0003ffff);
  238. for (rows = 11; rows < 16; rows++) {
  239. offset = 1 << (rows + columns + bus);
  240. if (mctl_mem_matches(offset))
  241. break;
  242. }
  243. clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
  244. MCTL_CR_ROW(rows));
  245. } else {
  246. rows = (dram_para.para1 >> 16) & 0xff;
  247. writel(((dram_para.para2 & 0x000000f0) << 11) |
  248. ((rows - 1) << 4) |
  249. ((dram_para.para1 & 0x0f000000) >> 22) |
  250. 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
  251. &mctl_com->cr);
  252. setbits_le32(&mctl_com->swonr, 0x0003ffff);
  253. }
  254. /* Setup DRAM master priority? If this is left out things still work */
  255. writel(0x00000008, &mctl_com->mcr0_0);
  256. writel(0x0001000d, &mctl_com->mcr1_0);
  257. writel(0x00000004, &mctl_com->mcr0_1);
  258. writel(0x00000080, &mctl_com->mcr1_1);
  259. writel(0x00000004, &mctl_com->mcr0_2);
  260. writel(0x00000019, &mctl_com->mcr1_2);
  261. writel(0x00000004, &mctl_com->mcr0_3);
  262. writel(0x00000080, &mctl_com->mcr1_3);
  263. writel(0x00000004, &mctl_com->mcr0_4);
  264. writel(0x01010040, &mctl_com->mcr1_4);
  265. writel(0x00000004, &mctl_com->mcr0_5);
  266. writel(0x0001002f, &mctl_com->mcr1_5);
  267. writel(0x00000004, &mctl_com->mcr0_6);
  268. writel(0x00010020, &mctl_com->mcr1_6);
  269. writel(0x00000004, &mctl_com->mcr0_7);
  270. writel(0x00010020, &mctl_com->mcr1_7);
  271. writel(0x00000008, &mctl_com->mcr0_8);
  272. writel(0x00000001, &mctl_com->mcr1_8);
  273. writel(0x00000008, &mctl_com->mcr0_9);
  274. writel(0x00000005, &mctl_com->mcr1_9);
  275. writel(0x00000008, &mctl_com->mcr0_10);
  276. writel(0x00000003, &mctl_com->mcr1_10);
  277. writel(0x00000008, &mctl_com->mcr0_11);
  278. writel(0x00000005, &mctl_com->mcr1_11);
  279. writel(0x00000008, &mctl_com->mcr0_12);
  280. writel(0x00000003, &mctl_com->mcr1_12);
  281. writel(0x00000008, &mctl_com->mcr0_13);
  282. writel(0x00000004, &mctl_com->mcr1_13);
  283. writel(0x00000008, &mctl_com->mcr0_14);
  284. writel(0x00000002, &mctl_com->mcr1_14);
  285. writel(0x00000008, &mctl_com->mcr0_15);
  286. writel(0x00000003, &mctl_com->mcr1_15);
  287. writel(0x00010138, &mctl_com->bwcr);
  288. return 1 << (rows + columns + bus);
  289. }