dram_sun50i_h6.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sun50i H6 platform dram controller init
  4. *
  5. * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
  6. *
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/dram.h>
  14. #include <asm/arch/cpu.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/kconfig.h>
  18. /*
  19. * The DRAM controller structure on H6 is similar to the ones on A23/A80:
  20. * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
  21. * /H5/R40 CTL and PHY is composed).
  22. *
  23. * COM is allwinner-specific. On H6, the address mapping function is moved
  24. * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
  25. * controller).
  26. *
  27. * CTL (controller) and PHY is from DesignWare.
  28. *
  29. * The CTL part is a bit similar to the one on A23/A80 (because they all
  30. * originate from DesignWare), but gets more registers added.
  31. *
  32. * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
  33. * not seen on other SoCs in U-Boot. The only SoC that is also known to have
  34. * similar PHY is ZynqMP.
  35. */
  36. static void mctl_sys_init(struct dram_para *para);
  37. static void mctl_com_init(struct dram_para *para);
  38. static void mctl_channel_init(struct dram_para *para);
  39. static void mctl_core_init(struct dram_para *para)
  40. {
  41. mctl_sys_init(para);
  42. mctl_com_init(para);
  43. switch (para->type) {
  44. case SUNXI_DRAM_TYPE_LPDDR3:
  45. case SUNXI_DRAM_TYPE_DDR3:
  46. mctl_set_timing_params(para);
  47. break;
  48. default:
  49. panic("Unsupported DRAM type!");
  50. };
  51. mctl_channel_init(para);
  52. }
  53. /* PHY initialisation */
  54. static void mctl_phy_pir_init(u32 val)
  55. {
  56. struct sunxi_mctl_phy_reg * const mctl_phy =
  57. (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  58. writel(val, &mctl_phy->pir);
  59. writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
  60. mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
  61. }
  62. enum {
  63. MBUS_PORT_CPU = 0,
  64. MBUS_PORT_GPU = 1,
  65. MBUS_PORT_MAHB = 2,
  66. MBUS_PORT_DMA = 3,
  67. MBUS_PORT_VE = 4,
  68. MBUS_PORT_CE = 5,
  69. MBUS_PORT_TSC0 = 6,
  70. MBUS_PORT_NDFC0 = 8,
  71. MBUS_PORT_CSI0 = 11,
  72. MBUS_PORT_DI0 = 14,
  73. MBUS_PORT_DI1 = 15,
  74. MBUS_PORT_DE300 = 16,
  75. MBUS_PORT_IOMMU = 25,
  76. MBUS_PORT_VE2 = 26,
  77. MBUS_PORT_USB3 = 37,
  78. MBUS_PORT_PCIE = 38,
  79. MBUS_PORT_VP9 = 39,
  80. MBUS_PORT_HDCP2 = 40,
  81. };
  82. enum {
  83. MBUS_QOS_LOWEST = 0,
  84. MBUS_QOS_LOW,
  85. MBUS_QOS_HIGH,
  86. MBUS_QOS_HIGHEST
  87. };
  88. inline void mbus_configure_port(u8 port,
  89. bool bwlimit,
  90. bool priority,
  91. u8 qos,
  92. u8 waittime,
  93. u8 acs,
  94. u16 bwl0,
  95. u16 bwl1,
  96. u16 bwl2)
  97. {
  98. struct sunxi_mctl_com_reg * const mctl_com =
  99. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  100. const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
  101. | (priority ? (1 << 1) : 0)
  102. | ((qos & 0x3) << 2)
  103. | ((waittime & 0xf) << 4)
  104. | ((acs & 0xff) << 8)
  105. | (bwl0 << 16) );
  106. const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
  107. debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
  108. writel(cfg0, &mctl_com->master[port].cfg0);
  109. writel(cfg1, &mctl_com->master[port].cfg1);
  110. }
  111. #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
  112. mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
  113. MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
  114. static void mctl_set_master_priority(void)
  115. {
  116. struct sunxi_mctl_com_reg * const mctl_com =
  117. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  118. /* enable bandwidth limit windows and set windows size 1us */
  119. writel(399, &mctl_com->tmr);
  120. writel(BIT(16), &mctl_com->bwcr);
  121. MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
  122. MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
  123. MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
  124. MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
  125. MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
  126. MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
  127. MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
  128. MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
  129. MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
  130. MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
  131. MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
  132. MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
  133. MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
  134. MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
  135. MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
  136. MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
  137. MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
  138. }
  139. static void mctl_sys_init(struct dram_para *para)
  140. {
  141. struct sunxi_ccm_reg * const ccm =
  142. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  143. struct sunxi_mctl_com_reg * const mctl_com =
  144. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  145. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  146. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  147. /* Put all DRAM-related blocks to reset state */
  148. clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
  149. clrbits_le32(&ccm->dram_gate_reset, BIT(0));
  150. udelay(5);
  151. writel(0, &ccm->dram_gate_reset);
  152. clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
  153. clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
  154. udelay(5);
  155. /* Set PLL5 rate to doubled DRAM clock rate */
  156. writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
  157. CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
  158. mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
  159. /* Configure DRAM mod clock */
  160. writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
  161. setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
  162. writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
  163. udelay(5);
  164. setbits_le32(&ccm->dram_gate_reset, BIT(0));
  165. /* Disable all channels */
  166. writel(0, &mctl_com->maer0);
  167. writel(0, &mctl_com->maer1);
  168. writel(0, &mctl_com->maer2);
  169. /* Configure MBUS and enable DRAM mod reset */
  170. setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
  171. setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
  172. setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
  173. udelay(5);
  174. /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
  175. writel(0x8000, &mctl_ctl->unk_0x00c);
  176. }
  177. static void mctl_set_addrmap(struct dram_para *para)
  178. {
  179. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  180. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  181. u8 cols = para->cols;
  182. u8 rows = para->rows;
  183. u8 ranks = para->ranks;
  184. if (!para->bus_full_width)
  185. cols -= 1;
  186. /* Ranks */
  187. if (ranks == 2)
  188. mctl_ctl->addrmap[0] = rows + cols - 3;
  189. else
  190. mctl_ctl->addrmap[0] = 0x1F;
  191. /* Banks, hardcoded to 8 banks now */
  192. mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
  193. /* Columns */
  194. mctl_ctl->addrmap[2] = 0;
  195. switch (cols) {
  196. case 7:
  197. mctl_ctl->addrmap[3] = 0x1F1F1F00;
  198. mctl_ctl->addrmap[4] = 0x1F1F;
  199. break;
  200. case 8:
  201. mctl_ctl->addrmap[3] = 0x1F1F0000;
  202. mctl_ctl->addrmap[4] = 0x1F1F;
  203. break;
  204. case 9:
  205. mctl_ctl->addrmap[3] = 0x1F000000;
  206. mctl_ctl->addrmap[4] = 0x1F1F;
  207. break;
  208. case 10:
  209. mctl_ctl->addrmap[3] = 0;
  210. mctl_ctl->addrmap[4] = 0x1F1F;
  211. break;
  212. case 11:
  213. mctl_ctl->addrmap[3] = 0;
  214. mctl_ctl->addrmap[4] = 0x1F00;
  215. break;
  216. case 12:
  217. mctl_ctl->addrmap[3] = 0;
  218. mctl_ctl->addrmap[4] = 0;
  219. break;
  220. default:
  221. panic("Unsupported DRAM configuration: column number invalid\n");
  222. }
  223. /* Rows */
  224. mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
  225. switch (rows) {
  226. case 13:
  227. mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
  228. mctl_ctl->addrmap[7] = 0x0F0F;
  229. break;
  230. case 14:
  231. mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
  232. mctl_ctl->addrmap[7] = 0x0F0F;
  233. break;
  234. case 15:
  235. mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
  236. mctl_ctl->addrmap[7] = 0x0F0F;
  237. break;
  238. case 16:
  239. mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
  240. mctl_ctl->addrmap[7] = 0x0F0F;
  241. break;
  242. case 17:
  243. mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
  244. mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
  245. break;
  246. case 18:
  247. mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
  248. mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
  249. break;
  250. default:
  251. panic("Unsupported DRAM configuration: row number invalid\n");
  252. }
  253. /* Bank groups, DDR4 only */
  254. mctl_ctl->addrmap[8] = 0x3F3F;
  255. }
  256. static void mctl_com_init(struct dram_para *para)
  257. {
  258. struct sunxi_mctl_com_reg * const mctl_com =
  259. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  260. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  261. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  262. struct sunxi_mctl_phy_reg * const mctl_phy =
  263. (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  264. u32 reg_val, tmp;
  265. mctl_set_addrmap(para);
  266. setbits_le32(&mctl_com->cr, BIT(31));
  267. /* The bonding ID seems to be always 7. */
  268. if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
  269. clrbits_le32(&mctl_com->cr, BIT(27));
  270. else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
  271. setbits_le32(&mctl_com->cr, BIT(27));
  272. if (para->clk > 408)
  273. reg_val = 0xf00;
  274. else if (para->clk > 246)
  275. reg_val = 0x1f00;
  276. else
  277. reg_val = 0x3f00;
  278. clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
  279. /* TODO: DDR4 */
  280. reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
  281. if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
  282. reg_val |= MSTR_DEVICETYPE_LPDDR3;
  283. if (para->type == SUNXI_DRAM_TYPE_DDR3)
  284. reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
  285. if (para->bus_full_width)
  286. reg_val |= MSTR_BUSWIDTH_FULL;
  287. else
  288. reg_val |= MSTR_BUSWIDTH_HALF;
  289. writel(reg_val | BIT(31), &mctl_ctl->mstr);
  290. if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
  291. reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
  292. if (para->type == SUNXI_DRAM_TYPE_DDR3)
  293. reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
  294. writel(reg_val | 0x400, &mctl_phy->dcr);
  295. if (para->ranks == 2)
  296. writel(0x0303, &mctl_ctl->odtmap);
  297. else
  298. writel(0x0201, &mctl_ctl->odtmap);
  299. /* TODO: DDR4 */
  300. if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
  301. tmp = para->clk * 7 / 2000;
  302. reg_val = 0x0400;
  303. reg_val |= (tmp + 7) << 24;
  304. reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
  305. } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
  306. reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
  307. } else {
  308. panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
  309. }
  310. writel(reg_val, &mctl_ctl->odtcfg);
  311. if (!para->bus_full_width) {
  312. writel(0x0, &mctl_phy->dx[2].gcr[0]);
  313. writel(0x0, &mctl_phy->dx[3].gcr[0]);
  314. }
  315. }
  316. static void mctl_bit_delay_set(struct dram_para *para)
  317. {
  318. struct sunxi_mctl_phy_reg * const mctl_phy =
  319. (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  320. int i, j;
  321. u32 val;
  322. for (i = 0; i < 4; i++) {
  323. val = readl(&mctl_phy->dx[i].bdlr0);
  324. for (j = 0; j < 4; j++)
  325. val += para->dx_write_delays[i][j] << (j * 8);
  326. writel(val, &mctl_phy->dx[i].bdlr0);
  327. val = readl(&mctl_phy->dx[i].bdlr1);
  328. for (j = 0; j < 4; j++)
  329. val += para->dx_write_delays[i][j + 4] << (j * 8);
  330. writel(val, &mctl_phy->dx[i].bdlr1);
  331. val = readl(&mctl_phy->dx[i].bdlr2);
  332. for (j = 0; j < 4; j++)
  333. val += para->dx_write_delays[i][j + 8] << (j * 8);
  334. writel(val, &mctl_phy->dx[i].bdlr2);
  335. }
  336. clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
  337. for (i = 0; i < 4; i++) {
  338. val = readl(&mctl_phy->dx[i].bdlr3);
  339. for (j = 0; j < 4; j++)
  340. val += para->dx_read_delays[i][j] << (j * 8);
  341. writel(val, &mctl_phy->dx[i].bdlr3);
  342. val = readl(&mctl_phy->dx[i].bdlr4);
  343. for (j = 0; j < 4; j++)
  344. val += para->dx_read_delays[i][j + 4] << (j * 8);
  345. writel(val, &mctl_phy->dx[i].bdlr4);
  346. val = readl(&mctl_phy->dx[i].bdlr5);
  347. for (j = 0; j < 4; j++)
  348. val += para->dx_read_delays[i][j + 8] << (j * 8);
  349. writel(val, &mctl_phy->dx[i].bdlr5);
  350. val = readl(&mctl_phy->dx[i].bdlr6);
  351. val += (para->dx_read_delays[i][12] << 8) |
  352. (para->dx_read_delays[i][13] << 16);
  353. writel(val, &mctl_phy->dx[i].bdlr6);
  354. }
  355. setbits_le32(&mctl_phy->pgcr[0], BIT(26));
  356. udelay(1);
  357. if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
  358. return;
  359. for (i = 1; i < 14; i++) {
  360. val = readl(&mctl_phy->acbdlr[i]);
  361. val += 0x0a0a0a0a;
  362. writel(val, &mctl_phy->acbdlr[i]);
  363. }
  364. }
  365. static void mctl_channel_init(struct dram_para *para)
  366. {
  367. struct sunxi_mctl_com_reg * const mctl_com =
  368. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  369. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  370. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  371. struct sunxi_mctl_phy_reg * const mctl_phy =
  372. (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  373. int i;
  374. u32 val;
  375. setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
  376. setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
  377. writel(0x2f05, &mctl_ctl->sched[0]);
  378. setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
  379. setbits_le32(&mctl_ctl->dfimisc, BIT(0));
  380. setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
  381. clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
  382. /* TODO: non-LPDDR3 types */
  383. clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
  384. clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
  385. clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
  386. /* TODO: VT compensation */
  387. clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
  388. clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
  389. for (i = 0; i < 4; i++)
  390. clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
  391. for (i = 0; i < 4; i++)
  392. clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
  393. for (i = 0; i < 4; i++)
  394. clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
  395. udelay(100);
  396. if (para->ranks == 2)
  397. setbits_le32(&mctl_phy->dtcr[1], 0x30000);
  398. else
  399. clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
  400. if (sunxi_dram_is_lpddr(para->type))
  401. clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
  402. if (para->ranks == 2) {
  403. writel(0x00010001, &mctl_phy->rankidr);
  404. writel(0x20000, &mctl_phy->odtcr);
  405. } else {
  406. writel(0x0, &mctl_phy->rankidr);
  407. writel(0x10000, &mctl_phy->odtcr);
  408. }
  409. /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
  410. if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
  411. clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
  412. else
  413. clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
  414. if (para->clk <= 792) {
  415. if (para->clk <= 672) {
  416. if (para->clk <= 600)
  417. val = 0x300;
  418. else
  419. val = 0x400;
  420. } else {
  421. val = 0x500;
  422. }
  423. } else {
  424. val = 0x600;
  425. }
  426. /* FIXME: NOT REVIEWED YET */
  427. clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
  428. clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
  429. CONFIG_DRAM_ZQ & 0xff);
  430. clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
  431. setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
  432. setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
  433. setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
  434. clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
  435. setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
  436. setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
  437. setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
  438. if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
  439. for (i = 1; i < 14; i++)
  440. writel(0x06060606, &mctl_phy->acbdlr[i]);
  441. }
  442. val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
  443. PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
  444. if (para->type == SUNXI_DRAM_TYPE_DDR3)
  445. val |= PIR_DRAMRST | PIR_WL;
  446. mctl_phy_pir_init(val);
  447. /* TODO: DDR4 types ? */
  448. for (i = 0; i < 4; i++)
  449. writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
  450. for (i = 0; i < 4; i++) {
  451. if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
  452. val = 0x0;
  453. else
  454. val = 0xaaaa;
  455. clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
  456. if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
  457. val = 0x0;
  458. else
  459. val = 0x2020;
  460. clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
  461. }
  462. mctl_bit_delay_set(para);
  463. udelay(1);
  464. setbits_le32(&mctl_phy->pgcr[6], BIT(0));
  465. clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
  466. for (i = 0; i < 4; i++)
  467. clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
  468. udelay(10);
  469. if (readl(&mctl_phy->pgsr[0]) & 0x400000)
  470. {
  471. /* Check for single rank and optionally half DQ. */
  472. if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
  473. (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
  474. para->ranks = 1;
  475. if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
  476. (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
  477. para->bus_full_width = 0;
  478. /* Restart DRAM initialization from scratch. */
  479. mctl_core_init(para);
  480. return;
  481. }
  482. /*
  483. * Check for dual rank and half DQ. NOTE: This combination
  484. * is highly unlikely and was not tested. Condition is the
  485. * same as in libdram, though.
  486. */
  487. if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
  488. (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
  489. para->bus_full_width = 0;
  490. /* Restart DRAM initialization from scratch. */
  491. mctl_core_init(para);
  492. return;
  493. }
  494. panic("This DRAM setup is currently not supported.\n");
  495. }
  496. if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
  497. /* Oops! There's something wrong! */
  498. debug("PLL = %x\n", readl(0x3001010));
  499. debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
  500. for (i = 0; i < 4; i++)
  501. debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
  502. panic("Error while initializing DRAM PHY!\n");
  503. }
  504. if (sunxi_dram_is_lpddr(para->type))
  505. clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
  506. clrbits_le32(&mctl_phy->pgcr[1], 0x40);
  507. clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
  508. writel(1, &mctl_ctl->swctl);
  509. mctl_await_completion(&mctl_ctl->swstat, 1, 1);
  510. clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
  511. setbits_le32(&mctl_com->unk_0x014, BIT(31));
  512. writel(0xffffffff, &mctl_com->maer0);
  513. writel(0x7ff, &mctl_com->maer1);
  514. writel(0xffff, &mctl_com->maer2);
  515. }
  516. static void mctl_auto_detect_dram_size(struct dram_para *para)
  517. {
  518. /* TODO: non-(LP)DDR3 */
  519. /* Detect rank number and half DQ by the code in mctl_channel_init. */
  520. mctl_core_init(para);
  521. /* detect row address bits */
  522. para->cols = 8;
  523. para->rows = 18;
  524. mctl_core_init(para);
  525. for (para->rows = 13; para->rows < 18; para->rows++) {
  526. /* 8 banks, 8 bit per byte and 16/32 bit width */
  527. if (mctl_mem_matches((1 << (para->rows + para->cols +
  528. 4 + para->bus_full_width))))
  529. break;
  530. }
  531. /* detect column address bits */
  532. para->cols = 11;
  533. mctl_core_init(para);
  534. for (para->cols = 8; para->cols < 11; para->cols++) {
  535. /* 8 bits per byte and 16/32 bit width */
  536. if (mctl_mem_matches(1 << (para->cols + 1 +
  537. para->bus_full_width)))
  538. break;
  539. }
  540. }
  541. unsigned long mctl_calc_size(struct dram_para *para)
  542. {
  543. u8 width = para->bus_full_width ? 4 : 2;
  544. /* TODO: non-(LP)DDR3 */
  545. /* 8 banks */
  546. return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
  547. }
  548. #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
  549. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  550. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  551. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
  552. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
  553. #define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
  554. {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
  555. { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
  556. { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
  557. { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
  558. #define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
  559. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  560. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  561. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  562. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
  563. #define SUN50I_H6_DDR3_DX_READ_DELAYS \
  564. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  565. { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
  566. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
  567. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
  568. unsigned long sunxi_dram_init(void)
  569. {
  570. struct sunxi_mctl_com_reg * const mctl_com =
  571. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  572. struct dram_para para = {
  573. .clk = CONFIG_DRAM_CLK,
  574. .ranks = 2,
  575. .cols = 11,
  576. .rows = 14,
  577. .bus_full_width = 1,
  578. #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
  579. .type = SUNXI_DRAM_TYPE_LPDDR3,
  580. .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
  581. .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
  582. #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
  583. .type = SUNXI_DRAM_TYPE_DDR3,
  584. .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
  585. .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
  586. #endif
  587. };
  588. unsigned long size;
  589. /* RES_CAL_CTRL_REG in BSP U-boot*/
  590. setbits_le32(0x7010310, BIT(8));
  591. clrbits_le32(0x7010318, 0x3f);
  592. mctl_auto_detect_dram_size(&para);
  593. mctl_core_init(&para);
  594. size = mctl_calc_size(&para);
  595. clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
  596. mctl_set_master_priority();
  597. return size;
  598. };