sdram_rk3036.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * (C) Copyright 2015 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/types.h>
  9. #include <asm/arch-rockchip/cru_rk3036.h>
  10. #include <asm/arch-rockchip/grf_rk3036.h>
  11. #include <asm/arch-rockchip/hardware.h>
  12. #include <asm/arch-rockchip/sdram_rk3036.h>
  13. #include <asm/arch-rockchip/uart.h>
  14. #include <linux/delay.h>
  15. /*
  16. * we can not fit the code to access the device tree in SPL
  17. * (due to 4K SRAM size limits), so these are hard-coded
  18. */
  19. #define CRU_BASE 0x20000000
  20. #define GRF_BASE 0x20008000
  21. #define DDR_PHY_BASE 0x2000a000
  22. #define DDR_PCTL_BASE 0x20004000
  23. #define CPU_AXI_BUS_BASE 0x10128000
  24. struct rk3036_sdram_priv {
  25. struct rk3036_cru *cru;
  26. struct rk3036_grf *grf;
  27. struct rk3036_ddr_phy *phy;
  28. struct rk3036_ddr_pctl *pctl;
  29. struct rk3036_service_sys *axi_bus;
  30. /* ddr die config */
  31. struct rk3036_ddr_config ddr_config;
  32. };
  33. /*
  34. * use integer mode, dpll output 792MHz and ddr get 396MHz
  35. * refdiv, fbdiv, postdiv1, postdiv2
  36. */
  37. const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
  38. /* 396Mhz ddr timing */
  39. const struct rk3036_ddr_timing ddr_timing = {0x18c,
  40. {0x18c, 0xc8, 0x1f4, 0x27, 0x4e,
  41. 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04,
  42. 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03,
  43. 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0},
  44. {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60},
  45. {0x24717315} };
  46. /*
  47. * [7:6] bank(n:n bit bank)
  48. * [5:4] row(13+n)
  49. * [3] cs(0:1 cs, 1:2 cs)
  50. * [2:1] bank(n:n bit bank)
  51. * [0] col(10+n)
  52. */
  53. const char ddr_cfg_2_rbc[] = {
  54. ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1),
  55. ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0),
  56. ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0),
  57. ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0),
  58. ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1),
  59. ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1),
  60. ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1),
  61. ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0),
  62. ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1),
  63. ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0),
  64. ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1),
  65. ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0),
  66. ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1),
  67. ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0),
  68. };
  69. /* DDRPHY REG */
  70. enum {
  71. /* DDRPHY_REG1 */
  72. SOFT_RESET_MASK = 3,
  73. SOFT_RESET_SHIFT = 2,
  74. /* DDRPHY_REG2 */
  75. MEMORY_SELECT_DDR3 = 0 << 6,
  76. DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
  77. DQS_SQU_CAL_START = 1 << 0,
  78. DQS_SQU_NO_CAL = 0 << 0,
  79. /* DDRPHY_REG2A */
  80. CMD_DLL_BYPASS = 1 << 4,
  81. CMD_DLL_BYPASS_DISABLE = 0 << 4,
  82. HIGH_8BIT_DLL_BYPASS = 1 << 3,
  83. HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3,
  84. LOW_8BIT_DLL_BYPASS = 1 << 2,
  85. LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2,
  86. /* DDRPHY_REG19 */
  87. CMD_FEEDBACK_ENABLE = 1 << 5,
  88. CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4,
  89. CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4,
  90. CMD_SLAVE_DLL_ENALBE = 1 << 3,
  91. CMD_TX_SLAVE_DLL_DELAY_MASK = 7,
  92. CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0,
  93. /* DDRPHY_REG6 */
  94. LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
  95. LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
  96. LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
  97. LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
  98. LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
  99. /* DDRPHY_REG8 */
  100. LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
  101. LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
  102. /* DDRPHY_REG9 */
  103. RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
  104. RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
  105. RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
  106. RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
  107. RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
  108. /* DDRPHY_REG11 */
  109. RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
  110. RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
  111. /* DDRPHY_REG62 */
  112. CAL_DONE_MASK = 3,
  113. HIGH_8BIT_CAL_DONE = 1 << 1,
  114. LOW_8BIT_CAL_DONE = 1 << 0,
  115. };
  116. /* PTCL */
  117. enum {
  118. /* PCTL_DFISTCFG0 */
  119. DFI_INIT_START = 1 << 0,
  120. DFI_DATA_BYTE_DISABLE_EN = 1 << 2,
  121. /* PCTL_DFISTCFG1 */
  122. DFI_DRAM_CLK_SR_EN = 1 << 0,
  123. DFI_DRAM_CLK_DPD_EN = 1 << 1,
  124. /* PCTL_DFISTCFG2 */
  125. DFI_PARITY_INTR_EN = 1 << 0,
  126. DFI_PARITY_EN = 1 << 1,
  127. /* PCTL_DFILPCFG0 */
  128. TLP_RESP_TIME_SHIFT = 16,
  129. LP_SR_EN = 1 << 8,
  130. LP_PD_EN = 1 << 0,
  131. /* PCTL_DFIODTCFG */
  132. RANK0_ODT_WRITE_SEL = 1 << 3,
  133. RANK1_ODT_WRITE_SEL = 1 << 11,
  134. /* PCTL_DFIODTCFG1 */
  135. ODT_LEN_BL8_W_SHIFT = 16,
  136. /* PCTL_MCFG */
  137. TFAW_CFG_MASK = 3,
  138. TFAW_CFG_SHIFT = 18,
  139. PD_EXIT_SLOW_MODE = 0 << 17,
  140. PD_ACTIVE_POWER_DOWN = 1 << 16,
  141. PD_IDLE_MASK = 0xff,
  142. PD_IDLE_SHIFT = 8,
  143. MEM_BL4 = 0 << 0,
  144. MEM_BL8 = 1 << 0,
  145. /* PCTL_MCFG1 */
  146. HW_EXIT_IDLE_EN_MASK = 1,
  147. HW_EXIT_IDLE_EN_SHIFT = 31,
  148. SR_IDLE_MASK = 0x1ff,
  149. SR_IDLE_SHIFT = 0,
  150. /* PCTL_SCFG */
  151. HW_LOW_POWER_EN = 1 << 0,
  152. /* PCTL_POWCTL */
  153. POWER_UP_START = 1 << 0,
  154. /* PCTL_POWSTAT */
  155. POWER_UP_DONE = 1 << 0,
  156. /* PCTL_MCMD */
  157. START_CMD = 1 << 31,
  158. BANK_ADDR_MASK = 7,
  159. BANK_ADDR_SHIFT = 17,
  160. CMD_ADDR_MASK = 0x1fff,
  161. CMD_ADDR_SHIFT = 4,
  162. DESELECT_CMD = 0,
  163. PREA_CMD,
  164. REF_CMD,
  165. MRS_CMD,
  166. ZQCS_CMD,
  167. ZQCL_CMD,
  168. RSTL_CMD,
  169. MRR_CMD = 8,
  170. /* PCTL_STAT */
  171. INIT_MEM = 0,
  172. CONFIG,
  173. CONFIG_REQ,
  174. ACCESS,
  175. ACCESS_REQ,
  176. LOW_POWER,
  177. LOW_POWER_ENTRY_REQ,
  178. LOW_POWER_EXIT_REQ,
  179. PCTL_STAT_MASK = 7,
  180. /* PCTL_SCTL */
  181. INIT_STATE = 0,
  182. CFG_STATE = 1,
  183. GO_STATE = 2,
  184. SLEEP_STATE = 3,
  185. WAKEUP_STATE = 4,
  186. };
  187. /* GRF_SOC_CON2 */
  188. #define MSCH4_MAINDDR3 (1 << 7)
  189. #define PHY_DRV_ODT_SET(n) ((n << 4) | n)
  190. #define DDR3_DLL_RESET (1 << 8)
  191. /* CK pull up/down driver strength control */
  192. enum {
  193. PHY_RON_DISABLE = 0,
  194. PHY_RON_309OHM = 1,
  195. PHY_RON_155OHM,
  196. PHY_RON_103OHM = 3,
  197. PHY_RON_63OHM = 5,
  198. PHY_RON_45OHM = 7,
  199. PHY_RON_77OHM,
  200. PHY_RON_62OHM,
  201. PHY_RON_52OHM,
  202. PHY_RON_44OHM,
  203. PHY_RON_39OHM,
  204. PHY_RON_34OHM,
  205. PHY_RON_31OHM,
  206. PHY_RON_28OHM,
  207. };
  208. /* DQ pull up/down control */
  209. enum {
  210. PHY_RTT_DISABLE = 0,
  211. PHY_RTT_861OHM = 1,
  212. PHY_RTT_431OHM,
  213. PHY_RTT_287OHM,
  214. PHY_RTT_216OHM,
  215. PHY_RTT_172OHM,
  216. PHY_RTT_145OHM,
  217. PHY_RTT_124OHM,
  218. PHY_RTT_215OHM,
  219. PHY_RTT_144OHM = 0xa,
  220. PHY_RTT_123OHM,
  221. PHY_RTT_108OHM,
  222. PHY_RTT_96OHM,
  223. PHY_RTT_86OHM,
  224. PHY_RTT_78OHM,
  225. };
  226. /* DQS squelch DLL delay */
  227. enum {
  228. DQS_DLL_NO_DELAY = 0,
  229. DQS_DLL_22P5_DELAY,
  230. DQS_DLL_45_DELAY,
  231. DQS_DLL_67P5_DELAY,
  232. DQS_DLL_90_DELAY,
  233. DQS_DLL_112P5_DELAY,
  234. DQS_DLL_135_DELAY,
  235. DQS_DLL_157P5_DELAY,
  236. };
  237. /* GRF_OS_REG1 */
  238. enum {
  239. /*
  240. * 000: lpddr
  241. * 001: ddr
  242. * 010: ddr2
  243. * 011: ddr3
  244. * 100: lpddr2-s2
  245. * 101: lpddr2-s4
  246. * 110: lpddr3
  247. */
  248. DDR_TYPE_MASK = 7,
  249. DDR_TYPE_SHIFT = 13,
  250. /* 0: 1 chn, 1: 2 chn */
  251. DDR_CHN_CNT_SHIFT = 12,
  252. /* 0: 1 rank, 1: 2 rank */
  253. DDR_RANK_CNT_MASK = 1,
  254. DDR_RANK_CNT_SHIFT = 11,
  255. /*
  256. * 00: 9col
  257. * 01: 10col
  258. * 10: 11col
  259. * 11: 12col
  260. */
  261. DDR_COL_MASK = 3,
  262. DDR_COL_SHIFT = 9,
  263. /* 0: 8 bank, 1: 4 bank*/
  264. DDR_BANK_MASK = 1,
  265. DDR_BANK_SHIFT = 8,
  266. /*
  267. * 00: 13 row
  268. * 01: 14 row
  269. * 10: 15 row
  270. * 11: 16 row
  271. */
  272. DDR_CS0_ROW_MASK = 3,
  273. DDR_CS0_ROW_SHIFT = 6,
  274. DDR_CS1_ROW_MASK = 3,
  275. DDR_CS1_ROW_SHIFT = 4,
  276. /*
  277. * 00: 32 bit
  278. * 01: 16 bit
  279. * 10: 8 bit
  280. * rk3036 only support 16bit
  281. */
  282. DDR_BW_MASK = 3,
  283. DDR_BW_SHIFT = 2,
  284. DDR_DIE_BW_MASK = 3,
  285. DDR_DIE_BW_SHIFT = 0,
  286. };
  287. static void rkdclk_init(struct rk3036_sdram_priv *priv)
  288. {
  289. struct rk3036_pll *pll = &priv->cru->pll[1];
  290. /* pll enter slow-mode */
  291. rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
  292. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  293. /* use integer mode */
  294. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  295. rk_clrsetreg(&pll->con0,
  296. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  297. (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
  298. dpll_init_cfg.fbdiv);
  299. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  300. (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
  301. dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
  302. /* waiting for pll lock */
  303. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  304. udelay(1);
  305. /* PLL enter normal-mode */
  306. rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
  307. DPLL_MODE_NORM << DPLL_MODE_SHIFT);
  308. }
  309. static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  310. {
  311. int i;
  312. for (i = 0; i < n / sizeof(u32); i++) {
  313. writel(*src, dest);
  314. src++;
  315. dest++;
  316. }
  317. }
  318. void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
  319. {
  320. struct rk3036_ddr_phy *ddr_phy = priv->phy;
  321. rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
  322. 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
  323. 1 << DDRPHY_SRST_SHIFT,
  324. 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
  325. 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
  326. udelay(10);
  327. rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
  328. 1 << DDRPHY_SRST_SHIFT);
  329. udelay(10);
  330. rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
  331. 1 << DDRCTRL_SRST_SHIFT);
  332. udelay(10);
  333. clrsetbits_le32(&ddr_phy->ddrphy_reg1,
  334. SOFT_RESET_MASK << SOFT_RESET_SHIFT,
  335. 0 << SOFT_RESET_SHIFT);
  336. udelay(10);
  337. clrsetbits_le32(&ddr_phy->ddrphy_reg1,
  338. SOFT_RESET_MASK << SOFT_RESET_SHIFT,
  339. 3 << SOFT_RESET_SHIFT);
  340. udelay(1);
  341. }
  342. void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
  343. {
  344. struct rk3036_ddr_phy *ddr_phy = priv->phy;
  345. if (freq < ddr_timing.freq) {
  346. writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS |
  347. LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a);
  348. writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 |
  349. LEFT_CHN_TX_DQ_DLL_ENABLE |
  350. (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
  351. LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6);
  352. writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 |
  353. RIGHT_CHN_TX_DQ_DLL_ENABLE |
  354. (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
  355. RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
  356. &ddr_phy->ddrphy_reg9);
  357. } else {
  358. writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE |
  359. LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a);
  360. writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 |
  361. LEFT_CHN_TX_DQ_DLL_ENABLE |
  362. (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
  363. LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT,
  364. &ddr_phy->ddrphy_reg6);
  365. writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 |
  366. RIGHT_CHN_TX_DQ_DLL_ENABLE |
  367. (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
  368. RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
  369. &ddr_phy->ddrphy_reg9);
  370. }
  371. writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE |
  372. (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) <<
  373. CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19);
  374. /* 45 degree delay */
  375. writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) <<
  376. LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8);
  377. writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) <<
  378. RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11);
  379. }
  380. static void send_command(struct rk3036_ddr_pctl *pctl,
  381. u32 rank, u32 cmd, u32 arg)
  382. {
  383. writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
  384. udelay(1);
  385. while (readl(&pctl->mcmd) & START_CMD)
  386. ;
  387. }
  388. static void memory_init(struct rk3036_sdram_priv *priv)
  389. {
  390. struct rk3036_ddr_pctl *pctl = priv->pctl;
  391. send_command(pctl, 3, DESELECT_CMD, 0);
  392. udelay(1);
  393. send_command(pctl, 3, PREA_CMD, 0);
  394. send_command(pctl, 3, MRS_CMD,
  395. (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
  396. (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) <<
  397. CMD_ADDR_SHIFT);
  398. send_command(pctl, 3, MRS_CMD,
  399. (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
  400. (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) <<
  401. CMD_ADDR_SHIFT);
  402. send_command(pctl, 3, MRS_CMD,
  403. (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
  404. (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) <<
  405. CMD_ADDR_SHIFT);
  406. send_command(pctl, 3, MRS_CMD,
  407. (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
  408. (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) <<
  409. CMD_ADDR_SHIFT | DDR3_DLL_RESET);
  410. send_command(pctl, 3, ZQCL_CMD, 0);
  411. }
  412. static void data_training(struct rk3036_sdram_priv *priv)
  413. {
  414. struct rk3036_ddr_phy *ddr_phy = priv->phy;
  415. struct rk3036_ddr_pctl *pctl = priv->pctl;
  416. u32 value;
  417. /* disable auto refresh */
  418. value = readl(&pctl->trefi),
  419. writel(0, &pctl->trefi);
  420. clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
  421. DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
  422. udelay(1);
  423. while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
  424. (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
  425. ;
  426. }
  427. clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
  428. DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL);
  429. /*
  430. * since data training will take about 20us, so send some auto
  431. * refresh(about 7.8us) to complement the lost time
  432. */
  433. send_command(pctl, 3, REF_CMD, 0);
  434. send_command(pctl, 3, REF_CMD, 0);
  435. send_command(pctl, 3, REF_CMD, 0);
  436. writel(value, &pctl->trefi);
  437. }
  438. static void move_to_config_state(struct rk3036_sdram_priv *priv)
  439. {
  440. unsigned int state;
  441. struct rk3036_ddr_pctl *pctl = priv->pctl;
  442. while (1) {
  443. state = readl(&pctl->stat) & PCTL_STAT_MASK;
  444. switch (state) {
  445. case LOW_POWER:
  446. writel(WAKEUP_STATE, &pctl->sctl);
  447. while ((readl(&pctl->stat) & PCTL_STAT_MASK)
  448. != ACCESS)
  449. ;
  450. /*
  451. * If at low power state, need wakeup first, and then
  452. * enter the config, so fallthrough
  453. */
  454. case ACCESS:
  455. /* fallthrough */
  456. case INIT_MEM:
  457. writel(CFG_STATE, &pctl->sctl);
  458. while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
  459. ;
  460. break;
  461. case CONFIG:
  462. return;
  463. default:
  464. break;
  465. }
  466. }
  467. }
  468. static void move_to_access_state(struct rk3036_sdram_priv *priv)
  469. {
  470. unsigned int state;
  471. struct rk3036_ddr_pctl *pctl = priv->pctl;
  472. while (1) {
  473. state = readl(&pctl->stat) & PCTL_STAT_MASK;
  474. switch (state) {
  475. case LOW_POWER:
  476. writel(WAKEUP_STATE, &pctl->sctl);
  477. while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
  478. ;
  479. break;
  480. case INIT_MEM:
  481. writel(CFG_STATE, &pctl->sctl);
  482. while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
  483. ;
  484. /* fallthrough */
  485. case CONFIG:
  486. writel(GO_STATE, &pctl->sctl);
  487. while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
  488. ;
  489. break;
  490. case ACCESS:
  491. return;
  492. default:
  493. break;
  494. }
  495. }
  496. }
  497. static void pctl_cfg(struct rk3036_sdram_priv *priv)
  498. {
  499. struct rk3036_ddr_pctl *pctl = priv->pctl;
  500. u32 burst_len;
  501. u32 reg;
  502. writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
  503. writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
  504. writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
  505. writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
  506. &pctl->dfilpcfg0);
  507. writel(1, &pctl->dfitphyupdtype0);
  508. writel(0x0d, &pctl->dfitphyrdlat);
  509. /* cs0 and cs1 write odt enable */
  510. writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
  511. &pctl->dfiodtcfg);
  512. /* odt write length */
  513. writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
  514. /* phyupd and ctrlupd disabled */
  515. writel(0, &pctl->dfiupdcfg);
  516. if ((ddr_timing.noc_timing.burstlen << 1) == 4)
  517. burst_len = MEM_BL4;
  518. else
  519. burst_len = MEM_BL8;
  520. copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u,
  521. sizeof(struct rk3036_pctl_timing));
  522. reg = readl(&pctl->tcl);
  523. writel(reg - 3, &pctl->dfitrddataen);
  524. reg = readl(&pctl->tcwl);
  525. writel(reg - 1, &pctl->dfitphywrlat);
  526. writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT |
  527. PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN |
  528. (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT,
  529. &pctl->mcfg);
  530. writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2);
  531. setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
  532. }
  533. static void phy_cfg(struct rk3036_sdram_priv *priv)
  534. {
  535. struct rk3036_ddr_phy *ddr_phy = priv->phy;
  536. struct rk3036_service_sys *axi_bus = priv->axi_bus;
  537. writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming);
  538. writel(0x3f, &axi_bus->readlatency);
  539. writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE,
  540. &ddr_phy->ddrphy_reg2);
  541. clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl);
  542. writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a);
  543. writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16);
  544. writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22);
  545. writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25);
  546. writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26);
  547. writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27);
  548. writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28);
  549. }
  550. void dram_cfg_rbc(struct rk3036_sdram_priv *priv)
  551. {
  552. char noc_config;
  553. int i = 0;
  554. struct rk3036_ddr_config config = priv->ddr_config;
  555. struct rk3036_service_sys *axi_bus = priv->axi_bus;
  556. move_to_config_state(priv);
  557. /* 2bit in BIT1, 2 */
  558. if (config.rank == 2) {
  559. noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
  560. 1 << 3 | (config.col - 10);
  561. if (noc_config == ddr_cfg_2_rbc[9]) {
  562. i = 9;
  563. goto finish;
  564. } else if (noc_config == ddr_cfg_2_rbc[10]) {
  565. i = 10;
  566. goto finish;
  567. }
  568. }
  569. noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
  570. (config.col - 10);
  571. for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) {
  572. if (noc_config == ddr_cfg_2_rbc[i])
  573. goto finish;
  574. }
  575. /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */
  576. noc_config = 1 << 6 | (config.cs0_row - 13) << 4 |
  577. 2 << 1 | (config.col - 10);
  578. if (noc_config == ddr_cfg_2_rbc[11]) {
  579. i = 11;
  580. goto finish;
  581. }
  582. /* bank: 2bit in BIT6,7 */
  583. noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 |
  584. (config.col - 10);
  585. if (noc_config == ddr_cfg_2_rbc[0])
  586. i = 0;
  587. else if (noc_config == ddr_cfg_2_rbc[12])
  588. i = 12;
  589. else if (noc_config == ddr_cfg_2_rbc[13])
  590. i = 13;
  591. finish:
  592. writel(i, &axi_bus->ddrconf);
  593. move_to_access_state(priv);
  594. }
  595. static void sdram_all_config(struct rk3036_sdram_priv *priv)
  596. {
  597. u32 os_reg = 0;
  598. u32 cs1_row = 0;
  599. struct rk3036_ddr_config config = priv->ddr_config;
  600. if (config.rank > 1)
  601. cs1_row = config.cs1_row - 13;
  602. os_reg = config.ddr_type << DDR_TYPE_SHIFT |
  603. 0 << DDR_CHN_CNT_SHIFT |
  604. (config.rank - 1) << DDR_RANK_CNT_SHIFT |
  605. (config.col - 9) << DDR_COL_SHIFT |
  606. (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
  607. (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
  608. cs1_row << DDR_CS1_ROW_SHIFT |
  609. 1 << DDR_BW_SHIFT |
  610. (2 >> config.bw) << DDR_DIE_BW_SHIFT;
  611. writel(os_reg, &priv->grf->os_reg[1]);
  612. }
  613. size_t sdram_size(void)
  614. {
  615. u32 size, os_reg, cs0_row, cs1_row, col, bank, rank;
  616. struct rk3036_grf *grf = (void *)GRF_BASE;
  617. os_reg = readl(&grf->os_reg[1]);
  618. cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK);
  619. cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK);
  620. col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK);
  621. bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK);
  622. rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK);
  623. /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */
  624. size = 1 << (cs0_row + col + bank + 1);
  625. if (rank > 1)
  626. size += size >> (cs0_row - cs1_row);
  627. return size;
  628. }
  629. void sdram_init(void)
  630. {
  631. struct rk3036_sdram_priv sdram_priv;
  632. sdram_priv.cru = (void *)CRU_BASE;
  633. sdram_priv.grf = (void *)GRF_BASE;
  634. sdram_priv.phy = (void *)DDR_PHY_BASE;
  635. sdram_priv.pctl = (void *)DDR_PCTL_BASE;
  636. sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE;
  637. get_ddr_config(&sdram_priv.ddr_config);
  638. sdram_all_config(&sdram_priv);
  639. rkdclk_init(&sdram_priv);
  640. phy_pctrl_reset(&sdram_priv);
  641. phy_dll_bypass_set(&sdram_priv, ddr_timing.freq);
  642. pctl_cfg(&sdram_priv);
  643. phy_cfg(&sdram_priv);
  644. writel(POWER_UP_START, &sdram_priv.pctl->powctl);
  645. while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE))
  646. ;
  647. memory_init(&sdram_priv);
  648. move_to_config_state(&sdram_priv);
  649. data_training(&sdram_priv);
  650. move_to_access_state(&sdram_priv);
  651. dram_cfg_rbc(&sdram_priv);
  652. }