pipe3-phy.c 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI PIPE3 PHY
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <sata.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include "pipe3-phy.h"
  16. /* PLLCTRL Registers */
  17. #define PLL_STATUS 0x00000004
  18. #define PLL_GO 0x00000008
  19. #define PLL_CONFIGURATION1 0x0000000C
  20. #define PLL_CONFIGURATION2 0x00000010
  21. #define PLL_CONFIGURATION3 0x00000014
  22. #define PLL_CONFIGURATION4 0x00000020
  23. #define PLL_REGM_MASK 0x001FFE00
  24. #define PLL_REGM_SHIFT 9
  25. #define PLL_REGM_F_MASK 0x0003FFFF
  26. #define PLL_REGM_F_SHIFT 0
  27. #define PLL_REGN_MASK 0x000001FE
  28. #define PLL_REGN_SHIFT 1
  29. #define PLL_SELFREQDCO_MASK 0x0000000E
  30. #define PLL_SELFREQDCO_SHIFT 1
  31. #define PLL_SD_MASK 0x0003FC00
  32. #define PLL_SD_SHIFT 10
  33. #define SET_PLL_GO 0x1
  34. #define PLL_TICOPWDN BIT(16)
  35. #define PLL_LDOPWDN BIT(15)
  36. #define PLL_LOCK 0x2
  37. #define PLL_IDLE 0x1
  38. /* PHY POWER CONTROL Register */
  39. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
  40. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
  41. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
  42. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
  43. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
  44. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
  45. #define PLL_IDLE_TIME 100 /* in milliseconds */
  46. #define PLL_LOCK_TIME 100 /* in milliseconds */
  47. static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
  48. {
  49. return __raw_readl(addr + offset);
  50. }
  51. static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
  52. u32 data)
  53. {
  54. __raw_writel(data, addr + offset);
  55. }
  56. static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
  57. *pipe3)
  58. {
  59. u32 rate;
  60. struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
  61. rate = get_sys_clk_freq();
  62. for (; dpll_map->rate; dpll_map++) {
  63. if (rate == dpll_map->rate)
  64. return &dpll_map->params;
  65. }
  66. printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
  67. __func__, rate);
  68. return NULL;
  69. }
  70. static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
  71. {
  72. u32 val;
  73. int timeout = PLL_LOCK_TIME;
  74. do {
  75. mdelay(1);
  76. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  77. if (val & PLL_LOCK)
  78. break;
  79. } while (--timeout);
  80. if (!(val & PLL_LOCK)) {
  81. printf("%s: DPLL failed to lock\n", __func__);
  82. return -EBUSY;
  83. }
  84. return 0;
  85. }
  86. static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
  87. {
  88. u32 val;
  89. struct pipe3_dpll_params *dpll_params;
  90. dpll_params = omap_pipe3_get_dpll_params(phy);
  91. if (!dpll_params) {
  92. printf("%s: Invalid DPLL parameters\n", __func__);
  93. return -EINVAL;
  94. }
  95. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  96. val &= ~PLL_REGN_MASK;
  97. val |= dpll_params->n << PLL_REGN_SHIFT;
  98. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  99. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  100. val &= ~PLL_SELFREQDCO_MASK;
  101. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  102. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  103. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  104. val &= ~PLL_REGM_MASK;
  105. val |= dpll_params->m << PLL_REGM_SHIFT;
  106. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  107. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
  108. val &= ~PLL_REGM_F_MASK;
  109. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  110. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
  111. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
  112. val &= ~PLL_SD_MASK;
  113. val |= dpll_params->sd << PLL_SD_SHIFT;
  114. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
  115. omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  116. return omap_pipe3_wait_lock(phy);
  117. }
  118. static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
  119. {
  120. u32 val, rate;
  121. val = readl(phy->power_reg);
  122. rate = get_sys_clk_freq();
  123. rate = rate/1000000;
  124. if (on) {
  125. val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  126. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  127. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
  128. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  129. val |= rate <<
  130. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  131. } else {
  132. val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  133. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
  134. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  135. }
  136. writel(val, phy->power_reg);
  137. }
  138. int phy_pipe3_power_on(struct omap_pipe3 *phy)
  139. {
  140. int ret;
  141. u32 val;
  142. /* Program the DPLL only if not locked */
  143. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  144. if (!(val & PLL_LOCK)) {
  145. ret = omap_pipe3_dpll_program(phy);
  146. if (ret)
  147. return ret;
  148. } else {
  149. /* else just bring it out of IDLE mode */
  150. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  151. if (val & PLL_IDLE) {
  152. val &= ~PLL_IDLE;
  153. omap_pipe3_writel(phy->pll_ctrl_base,
  154. PLL_CONFIGURATION2, val);
  155. ret = omap_pipe3_wait_lock(phy);
  156. if (ret)
  157. return ret;
  158. }
  159. }
  160. /* Power up the PHY */
  161. omap_control_phy_power(phy, 1);
  162. return 0;
  163. }
  164. int phy_pipe3_power_off(struct omap_pipe3 *phy)
  165. {
  166. u32 val;
  167. int timeout = PLL_IDLE_TIME;
  168. /* Power down the PHY */
  169. omap_control_phy_power(phy, 0);
  170. /* Put DPLL in IDLE mode */
  171. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  172. val |= PLL_IDLE;
  173. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  174. /* wait for LDO and Oscillator to power down */
  175. do {
  176. mdelay(1);
  177. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  178. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  179. break;
  180. } while (--timeout);
  181. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  182. printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
  183. __func__, val);
  184. return -EBUSY;
  185. }
  186. return 0;
  187. }