clock_ti814x.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * clock_ti814x.c
  4. *
  5. * Clocks for TI814X based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated
  8. */
  9. #include <common.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. /* PRCM */
  16. #define PRCM_MOD_EN 0x2
  17. /* CLK_SRC */
  18. #define OSC_SRC0 0
  19. #define OSC_SRC1 1
  20. #define L3_OSC_SRC OSC_SRC0
  21. #define OSC_0_FREQ 20
  22. #define DCO_HS2_MIN 500
  23. #define DCO_HS2_MAX 1000
  24. #define DCO_HS1_MIN 1000
  25. #define DCO_HS1_MAX 2000
  26. #define SELFREQDCO_HS2 0x00000801
  27. #define SELFREQDCO_HS1 0x00001001
  28. #define MPU_N 0x1
  29. #define MPU_M 0x3C
  30. #define MPU_M2 1
  31. #define MPU_CLKCTRL 0x1
  32. #define L3_N 19
  33. #define L3_M 880
  34. #define L3_M2 4
  35. #define L3_CLKCTRL 0x801
  36. #define DDR_N 19
  37. #define DDR_M 666
  38. #define DDR_M2 2
  39. #define DDR_CLKCTRL 0x801
  40. /* ADPLLJ register values */
  41. #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
  42. #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
  43. #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
  44. #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
  45. #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
  46. #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
  47. #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
  48. #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
  49. #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
  50. #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
  51. #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
  52. #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
  53. ADPLLJ_CLKCTRL_CLKOUTEN | \
  54. ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
  55. ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
  56. #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
  57. #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
  58. #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
  59. ADPLLJ_STATUS_FREQLOCK)
  60. #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
  61. #define ADPLLJ_STATUS_BYPASS (1 << 0)
  62. #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
  63. ADPLLJ_STATUS_BYPASS)
  64. #define ADPLLJ_TENABLE_ENB (1 << 0)
  65. #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
  66. #define ADPLLJ_M2NDIV_M2SHIFT 16
  67. #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
  68. #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
  69. #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
  70. struct ad_pll {
  71. unsigned int pwrctrl;
  72. unsigned int clkctrl;
  73. unsigned int tenable;
  74. unsigned int tenablediv;
  75. unsigned int m2ndiv;
  76. unsigned int mn2div;
  77. unsigned int fracdiv;
  78. unsigned int bwctrl;
  79. unsigned int fracctrl;
  80. unsigned int status;
  81. unsigned int m3div;
  82. unsigned int rampctrl;
  83. };
  84. #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
  85. #define ENET_CLKCTRL_CMPL 0x30000
  86. #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
  87. struct sata_pll {
  88. unsigned int pllcfg0;
  89. unsigned int pllcfg1;
  90. unsigned int pllcfg2;
  91. unsigned int pllcfg3;
  92. unsigned int pllcfg4;
  93. unsigned int pllstatus;
  94. unsigned int rxstatus;
  95. unsigned int txstatus;
  96. unsigned int testcfg;
  97. };
  98. #define SEL_IN_FREQ (0x1 << 31)
  99. #define DIGCLRZ (0x1 << 30)
  100. #define ENDIGLDO (0x1 << 4)
  101. #define APLL_CP_CURR (0x1 << 3)
  102. #define ENBGSC_REF (0x1 << 2)
  103. #define ENPLLLDO (0x1 << 1)
  104. #define ENPLL (0x1 << 0)
  105. #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
  106. #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
  107. #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
  108. #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
  109. ENPLLLDO | ENPLL)
  110. #define PLL_LOCK (0x1 << 0)
  111. #define ENSATAMODE (0x1 << 31)
  112. #define PLLREFSEL (0x1 << 30)
  113. #define MDIVINT (0x4b << 18)
  114. #define EN_CLKAUX (0x1 << 5)
  115. #define EN_CLK125M (0x1 << 4)
  116. #define EN_CLK100M (0x1 << 3)
  117. #define EN_CLK50M (0x1 << 2)
  118. #define SATA_PLLCFG1 (ENSATAMODE | \
  119. PLLREFSEL | \
  120. MDIVINT | \
  121. EN_CLKAUX | \
  122. EN_CLK125M | \
  123. EN_CLK100M | \
  124. EN_CLK50M)
  125. #define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
  126. #define PLLDO_EN_LDO_STABLE (0x1 << 11)
  127. #define PLLDO_EN_BUF_CUR (0x1 << 7)
  128. #define PLLDO_EN_LP (0x1 << 6)
  129. #define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
  130. #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
  131. PLLDO_EN_LDO_STABLE | \
  132. PLLDO_EN_BUF_CUR | \
  133. PLLDO_EN_LP | \
  134. PLLDO_CTRL_TRIM_1_4V)
  135. const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
  136. const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
  137. const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
  138. /*
  139. * Enable the peripheral clock for required peripherals
  140. */
  141. static void enable_per_clocks(void)
  142. {
  143. /* HSMMC1 */
  144. writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
  145. while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
  146. ;
  147. /* Ethernet */
  148. writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
  149. writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
  150. while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
  151. ;
  152. writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
  153. while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
  154. ;
  155. /* RTC clocks */
  156. writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
  157. writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
  158. while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
  159. ;
  160. }
  161. /*
  162. * select the HS1 or HS2 for DCO Freq
  163. * return : CLKCTRL
  164. */
  165. static u32 pll_dco_freq_sel(u32 clkout_dco)
  166. {
  167. if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
  168. return SELFREQDCO_HS2;
  169. else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
  170. return SELFREQDCO_HS1;
  171. else
  172. return -1;
  173. }
  174. /*
  175. * select the sigma delta config
  176. * return: sigma delta val
  177. */
  178. static u32 pll_sigma_delta_val(u32 clkout_dco)
  179. {
  180. u32 sig_val = 0;
  181. sig_val = (clkout_dco + 225) / 250;
  182. sig_val = sig_val << 24;
  183. return sig_val;
  184. }
  185. /*
  186. * configure individual ADPLLJ
  187. */
  188. static void pll_config(u32 base, u32 n, u32 m, u32 m2,
  189. u32 clkctrl_val, int adpllj)
  190. {
  191. const struct ad_pll *adpll = (struct ad_pll *)base;
  192. u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
  193. u32 sig_val = 0, hs_mod = 0;
  194. m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
  195. mn2val = m;
  196. /* calculate clkout_dco */
  197. clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
  198. /* sigma delta & Hs mode selection skip for ADPLLS*/
  199. if (adpllj) {
  200. sig_val = pll_sigma_delta_val(clkout_dco);
  201. hs_mod = pll_dco_freq_sel(clkout_dco);
  202. }
  203. /* by-pass pll */
  204. read_clkctrl = readl(&adpll->clkctrl);
  205. writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
  206. while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
  207. != ADPLLJ_STATUS_BYPASSANDACK)
  208. ;
  209. /* clear TINITZ */
  210. read_clkctrl = readl(&adpll->clkctrl);
  211. writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
  212. /*
  213. * ref_clk = 20/(n + 1);
  214. * clkout_dco = ref_clk * m;
  215. * clk_out = clkout_dco/m2;
  216. */
  217. read_clkctrl = readl(&adpll->clkctrl) &
  218. ~(ADPLLJ_CLKCTRL_LPMODE |
  219. ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
  220. ADPLLJ_CLKCTRL_REGM4XEN);
  221. writel(m2nval, &adpll->m2ndiv);
  222. writel(mn2val, &adpll->mn2div);
  223. /* Skip for modena(ADPLLS) */
  224. if (adpllj) {
  225. writel(sig_val, &adpll->fracdiv);
  226. writel((read_clkctrl | hs_mod), &adpll->clkctrl);
  227. }
  228. /* Load M2, N2 dividers of ADPLL */
  229. writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
  230. writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
  231. /* Load M, N dividers of ADPLL */
  232. writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
  233. writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
  234. /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
  235. read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
  236. if (adpllj)
  237. writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
  238. &adpll->clkctrl);
  239. /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
  240. read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
  241. writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
  242. /* Wait for phase and freq lock */
  243. while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
  244. ADPLLJ_STATUS_PHSFRQLOCK)
  245. ;
  246. }
  247. static void unlock_pll_control_mmr(void)
  248. {
  249. /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
  250. writel(0x1EDA4C3D, 0x481C5040);
  251. writel(0x2FF1AC2B, 0x48140060);
  252. writel(0xF757FDC0, 0x48140064);
  253. writel(0xE2BC3A6D, 0x48140068);
  254. writel(0x1EBF131D, 0x4814006c);
  255. writel(0x6F361E05, 0x48140070);
  256. }
  257. static void mpu_pll_config(void)
  258. {
  259. pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
  260. }
  261. static void l3_pll_config(void)
  262. {
  263. u32 l3_osc_src, rd_osc_src = 0;
  264. l3_osc_src = L3_OSC_SRC;
  265. rd_osc_src = readl(OSC_SRC_CTRL);
  266. if (OSC_SRC0 == l3_osc_src)
  267. writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
  268. else
  269. writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
  270. pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
  271. }
  272. void ddr_pll_config(unsigned int ddrpll_m)
  273. {
  274. pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
  275. }
  276. void sata_pll_config(void)
  277. {
  278. /*
  279. * This sequence for configuring the SATA PLL
  280. * resident in the control module is documented
  281. * in TI8148 TRM section 21.3.1
  282. */
  283. writel(SATA_PLLCFG1, &spll->pllcfg1);
  284. udelay(50);
  285. writel(SATA_PLLCFG3, &spll->pllcfg3);
  286. udelay(50);
  287. writel(SATA_PLLCFG0_1, &spll->pllcfg0);
  288. udelay(50);
  289. writel(SATA_PLLCFG0_2, &spll->pllcfg0);
  290. udelay(50);
  291. writel(SATA_PLLCFG0_3, &spll->pllcfg0);
  292. udelay(50);
  293. writel(SATA_PLLCFG0_4, &spll->pllcfg0);
  294. udelay(50);
  295. while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
  296. ;
  297. }
  298. void enable_dmm_clocks(void)
  299. {
  300. writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
  301. writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
  302. writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
  303. while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
  304. ;
  305. writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
  306. while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
  307. ;
  308. while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
  309. ;
  310. writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
  311. while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
  312. ;
  313. writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
  314. while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
  315. ;
  316. }
  317. void setup_clocks_for_console(void)
  318. {
  319. unlock_pll_control_mmr();
  320. /* UART0 */
  321. writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
  322. while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
  323. ;
  324. }
  325. void setup_early_clocks(void)
  326. {
  327. setup_clocks_for_console();
  328. }
  329. /*
  330. * Configure the PLL/PRCM for necessary peripherals
  331. */
  332. void prcm_init(void)
  333. {
  334. /* Enable the control module */
  335. writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
  336. /* Configure PLLs */
  337. mpu_pll_config();
  338. l3_pll_config();
  339. sata_pll_config();
  340. /* Enable the required peripherals */
  341. enable_per_clocks();
  342. }