high_speed_env_spec.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/soc.h>
  10. #include <linux/delay.h>
  11. #include "high_speed_env_spec.h"
  12. #include "sys_env_lib.h"
  13. #include "ctrl_pex.h"
  14. #if defined(CONFIG_ARMADA_38X)
  15. #elif defined(CONFIG_ARMADA_39X)
  16. #else
  17. #error "No device is defined"
  18. #endif
  19. /*
  20. * serdes_seq_db - holds all serdes sequences, their size and the
  21. * relevant index in the data array initialized in serdes_seq_init
  22. */
  23. struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
  24. #define SERDES_VERSION "2.0"
  25. #define ENDED_OK "High speed PHY - Ended Successfully\n"
  26. #define LINK_WAIT_CNTR 100
  27. #define LINK_WAIT_SLEEP 100
  28. #define MAX_UNIT_NUMB 4
  29. #define TOPOLOGY_TEST_OK 0
  30. #define WRONG_NUMBER_OF_UNITS 1
  31. #define SERDES_ALREADY_IN_USE 2
  32. #define UNIT_NUMBER_VIOLATION 3
  33. /*
  34. * serdes_lane_in_use_count contains the exact amount of serdes lanes
  35. * needed per type
  36. */
  37. u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = {
  38. /* 0 1 2 3 */
  39. { 1, 1, 1, 1 }, /* PEX */
  40. { 1, 1, 1, 1 }, /* ETH_GIG */
  41. { 1, 1, 0, 0 }, /* USB3H */
  42. { 1, 1, 1, 0 }, /* USB3D */
  43. { 1, 1, 1, 1 }, /* SATA */
  44. { 1, 0, 0, 0 }, /* QSGMII */
  45. { 4, 0, 0, 0 }, /* XAUI */
  46. { 2, 0, 0, 0 } /* RXAUI */
  47. };
  48. /*
  49. * serdes_unit_count count unit number.
  50. * (i.e a single XAUI is counted as 1 unit)
  51. */
  52. u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
  53. /* Selector mapping for A380-A0 and A390-Z1 */
  54. u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
  55. /* 0 1 2 3 4 5 6 */
  56. { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
  57. { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */
  58. { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */
  59. { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */
  60. { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */
  61. { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */
  62. { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */
  63. { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */
  64. { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */
  65. { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */
  66. { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */
  67. { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */
  68. { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
  69. { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
  70. { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
  71. #ifdef CONFIG_ARMADA_39X
  72. { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */
  73. { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */
  74. { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */
  75. #endif
  76. { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
  77. };
  78. /* Selector mapping for PEX by 4 confiuration */
  79. u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 };
  80. static const char *const serdes_type_to_string[] = {
  81. "PCIe0",
  82. "PCIe1",
  83. "PCIe2",
  84. "PCIe3",
  85. "SATA0",
  86. "SATA1",
  87. "SATA2",
  88. "SATA3",
  89. "SGMII0",
  90. "SGMII1",
  91. "SGMII2",
  92. "QSGMII",
  93. "USB3 HOST0",
  94. "USB3 HOST1",
  95. "USB3 DEVICE",
  96. "SGMII3",
  97. "XAUI",
  98. "RXAUI",
  99. "DEFAULT SERDES",
  100. "LAST_SERDES_TYPE"
  101. };
  102. struct serdes_unit_data {
  103. u8 serdes_unit_id;
  104. u8 serdes_unit_num;
  105. };
  106. static struct serdes_unit_data serdes_type_to_unit_info[] = {
  107. {PEX_UNIT_ID, 0,},
  108. {PEX_UNIT_ID, 1,},
  109. {PEX_UNIT_ID, 2,},
  110. {PEX_UNIT_ID, 3,},
  111. {SATA_UNIT_ID, 0,},
  112. {SATA_UNIT_ID, 1,},
  113. {SATA_UNIT_ID, 2,},
  114. {SATA_UNIT_ID, 3,},
  115. {ETH_GIG_UNIT_ID, 0,},
  116. {ETH_GIG_UNIT_ID, 1,},
  117. {ETH_GIG_UNIT_ID, 2,},
  118. {QSGMII_UNIT_ID, 0,},
  119. {USB3H_UNIT_ID, 0,},
  120. {USB3H_UNIT_ID, 1,},
  121. {USB3D_UNIT_ID, 0,},
  122. {ETH_GIG_UNIT_ID, 3,},
  123. {XAUI_UNIT_ID, 0,},
  124. {RXAUI_UNIT_ID, 0,},
  125. };
  126. /* Sequences DB */
  127. /*
  128. * SATA and SGMII
  129. */
  130. struct op_params sata_port0_power_up_params[] = {
  131. /*
  132. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  133. * num_of_loops
  134. */
  135. /* Access to reg 0x48(OOB param 1) */
  136. {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
  137. /* OOB Com_wake and Com_reset spacing upper limit data */
  138. {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
  139. /* Access to reg 0xa(PHY Control) */
  140. {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
  141. /* Rx clk and Tx clk select non-inverted mode */
  142. {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
  143. /* Power Down Sata addr */
  144. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
  145. /* Power Down Sata Port 0 */
  146. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0},
  147. };
  148. struct op_params sata_port1_power_up_params[] = {
  149. /*
  150. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  151. * num_of_loops
  152. */
  153. /* Access to reg 0x48(OOB param 1) */
  154. {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
  155. /* OOB Com_wake and Com_reset spacing upper limit data */
  156. {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
  157. /* Access to reg 0xa(PHY Control) */
  158. {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
  159. /* Rx clk and Tx clk select non-inverted mode */
  160. {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
  161. /* Power Down Sata addr */
  162. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
  163. /* Power Down Sata Port 1 */
  164. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0},
  165. };
  166. /* SATA and SGMII - power up seq */
  167. struct op_params sata_and_sgmii_power_up_params[] = {
  168. /*
  169. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  170. * wait_time, num_of_loops
  171. */
  172. /* Power Up */
  173. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002},
  174. 0, 0},
  175. /* Unreset */
  176. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0},
  177. /* Phy Selector */
  178. {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0},
  179. /* Ref clock source select */
  180. {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0}
  181. };
  182. /* SATA and SGMII - speed config seq */
  183. struct op_params sata_and_sgmii_speed_config_params[] = {
  184. /*
  185. * unit_base_reg, unit_offset, mask, SATA data,
  186. * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops
  187. */
  188. /* Baud Rate */
  189. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000,
  190. {0x8800000, 0x19800000, 0x22000000}, 0, 0},
  191. /* Select Baud Rate for SATA only */
  192. {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0},
  193. /* Phy Gen RX and TX */
  194. {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0},
  195. /* Bus Width */
  196. {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0}
  197. };
  198. /* SATA and SGMII - TX config seq */
  199. struct op_params sata_and_sgmii_tx_config_params1[] = {
  200. /*
  201. * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data,
  202. * wait_time, num_of_loops
  203. */
  204. {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0},
  205. /* Sft Reset pulse */
  206. {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
  207. /* Sft Reset pulse */
  208. {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
  209. /* Power up PLL, RX and TX */
  210. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000},
  211. 0, 0}
  212. };
  213. struct op_params sata_port0_tx_config_params[] = {
  214. /*
  215. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  216. * num_of_loops
  217. */
  218. /* Power Down Sata addr */
  219. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
  220. /* Power Down Sata Port 0 */
  221. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0},
  222. /* Regret bit addr */
  223. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
  224. /* Regret bit data */
  225. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
  226. };
  227. struct op_params sata_port1_tx_config_params[] = {
  228. /*
  229. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  230. * num_of_loops
  231. */
  232. /* Power Down Sata addr */
  233. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
  234. /* Power Down Sata Port 1 */
  235. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0},
  236. /* Regret bit addr */
  237. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
  238. /* Regret bit data */
  239. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
  240. };
  241. struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = {
  242. /*
  243. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  244. * wait_time, num_of_loops
  245. */
  246. /* Wait for PHY power up sequence to finish */
  247. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
  248. /* Wait for PHY power up sequence to finish */
  249. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}
  250. };
  251. struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = {
  252. /*
  253. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  254. * wait_time, num_of_loops
  255. */
  256. /* Wait for PHY power up sequence to finish */
  257. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
  258. /* Assert Rx Init for SGMII */
  259. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000},
  260. 0, 0},
  261. /* Assert Rx Init for SATA */
  262. {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0},
  263. /* Wait for PHY power up sequence to finish */
  264. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000},
  265. /* De-assert Rx Init for SGMII */
  266. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0},
  267. /* De-assert Rx Init for SATA */
  268. {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0},
  269. /* os_ph_offset_force (align 90) */
  270. {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0},
  271. /* Set os_ph_valid */
  272. {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
  273. /* Unset os_ph_valid */
  274. {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
  275. };
  276. struct op_params sata_electrical_config_serdes_rev1_params[] = {
  277. /*
  278. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  279. * num_of_loops
  280. */
  281. /* enable SSC and DFE update enable */
  282. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0},
  283. /* tximpcal_th and rximpcal_th */
  284. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0},
  285. /* SQ_THRESH and FFE Setting */
  286. {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0},
  287. /* G1_TX SLEW, EMPH1 and AMP */
  288. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0},
  289. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  290. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0},
  291. /* G2_TX SLEW, EMPH1 and AMP */
  292. {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0},
  293. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  294. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
  295. /* G3_TX SLEW, EMPH1 and AMP */
  296. {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0},
  297. /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  298. {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
  299. /* Cal rxclkalign90 ext enable and Cal os ph ext */
  300. {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0},
  301. /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
  302. {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
  303. };
  304. struct op_params sata_electrical_config_serdes_rev2_params[] = {
  305. /*
  306. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  307. * num_of_loops
  308. */
  309. /* SQ_THRESH and FFE Setting */
  310. {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0},
  311. /* enable SSC and DFE update enable */
  312. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0},
  313. /* G1_TX SLEW, EMPH1 and AMP */
  314. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0},
  315. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  316. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  317. /* G2_TX SLEW, EMPH1 and AMP */
  318. {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0},
  319. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  320. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  321. /* G3_TX SLEW, EMPH1 and AMP */
  322. {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0},
  323. /*
  324. * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3,
  325. * DC wander calibration dis
  326. */
  327. {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0},
  328. /* Bit[12]=0x0 idle_sync_en */
  329. {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0},
  330. /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
  331. {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
  332. /* tximpcal_th and rximpcal_th */
  333. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  334. /* DFE_STEP_FINE_FX[3:0] =0xa */
  335. {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0},
  336. /* DFE_EN and Dis Update control from pin disable */
  337. {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0},
  338. /* FFE Force FFE_REs and cap settings for Gen1 */
  339. {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  340. /* FFE Force FFE_REs and cap settings for Gen2 */
  341. {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0},
  342. /* FE Force FFE_REs=4 and cap settings for Gen3n */
  343. {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  344. /* Set DFE Gen 3 Resolution to 3 */
  345. {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
  346. };
  347. struct op_params sgmii_electrical_config_serdes_rev1_params[] = {
  348. /*
  349. * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
  350. * wait_time, num_of_loops
  351. */
  352. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  353. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
  354. /* SQ_THRESH and FFE Setting */
  355. {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0},
  356. /* tximpcal_th and rximpcal_th */
  357. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0},
  358. };
  359. struct op_params sgmii_electrical_config_serdes_rev2_params[] = {
  360. /*
  361. * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
  362. * wait_time, num_of_loops
  363. */
  364. /* Set Slew_rate, Emph and Amp */
  365. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0},
  366. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  367. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
  368. /* DTL_FLOOP_EN */
  369. {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0},
  370. /* G1 FFE Setting Force, RES and CAP */
  371. {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0},
  372. /* tximpcal_th and rximpcal_th */
  373. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0},
  374. };
  375. /*
  376. * PEX and USB3
  377. */
  378. /* PEX and USB3 - power up seq for Serdes Rev 1.2 */
  379. struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = {
  380. /*
  381. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  382. * wait_time, num_of_loops
  383. */
  384. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
  385. {0x4471804, 0x4479804}, 0, 0},
  386. {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
  387. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
  388. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
  389. {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
  390. /* Ref clock source select */
  391. {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
  392. };
  393. /* PEX and USB3 - power up seq for Serdes Rev 2.1 */
  394. struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = {
  395. /*
  396. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  397. * wait_time, num_of_loops
  398. */
  399. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
  400. {0x4471804, 0x4479804}, 0, 0},
  401. {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
  402. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
  403. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
  404. {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
  405. {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0},
  406. /* Ref clock source select */
  407. {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
  408. };
  409. /* PEX and USB3 - speed config seq */
  410. struct op_params pex_and_usb3_speed_config_params[] = {
  411. /*
  412. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  413. * wait_time, num_of_loops
  414. */
  415. /* Maximal PHY Generation Setting */
  416. {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400},
  417. 0, 0},
  418. };
  419. struct op_params usb3_electrical_config_serdes_rev1_params[] = {
  420. /* Spread Spectrum Clock Enable */
  421. {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
  422. /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
  423. {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
  424. /* tximpcal_th and rximpcal_th */
  425. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0},
  426. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  427. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  428. /* FFE Setting Force, RES and CAP */
  429. {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0},
  430. /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
  431. {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
  432. /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
  433. {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0},
  434. /* vco_cal_vth_sel */
  435. {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
  436. };
  437. struct op_params usb3_electrical_config_serdes_rev2_params[] = {
  438. /* Spread Spectrum Clock Enable */
  439. {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
  440. /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
  441. {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
  442. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  443. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  444. /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
  445. {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
  446. /* vco_cal_vth_sel */
  447. {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
  448. /* Spread Spectrum Clock Enable */
  449. {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0},
  450. };
  451. /* PEX and USB3 - TX config seq */
  452. /*
  453. * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run
  454. * one by one on the lane.
  455. * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run
  456. * by setting each sequence for all 4 lanes.
  457. */
  458. struct op_params pex_and_usb3_tx_config_params1[] = {
  459. /*
  460. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  461. * wait_time, num_of_loops
  462. */
  463. {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0},
  464. /* 10ms delay */
  465. {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0},
  466. /* os_ph_offset_force (align 90) */
  467. {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0},
  468. /* Set os_ph_valid */
  469. {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
  470. /* Unset os_ph_valid */
  471. {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
  472. };
  473. struct op_params pex_and_usb3_tx_config_params2[] = {
  474. /*
  475. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  476. * wait_time, num_of_loops
  477. */
  478. /* Sft Reset pulse */
  479. {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
  480. };
  481. struct op_params pex_and_usb3_tx_config_params3[] = {
  482. /*
  483. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  484. * wait_time, num_of_loops
  485. */
  486. /* Sft Reset pulse */
  487. {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
  488. /* 10ms delay */
  489. {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}
  490. };
  491. /* PEX by 4 config seq */
  492. struct op_params pex_by4_config_params[] = {
  493. /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
  494. {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
  495. /* Lane Alignement enable */
  496. {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
  497. /* Max PLL phy config */
  498. {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
  499. 0, 0},
  500. /* Max PLL pipe config */
  501. {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0},
  502. };
  503. /* USB3 device donfig seq */
  504. struct op_params usb3_device_config_params[] = {
  505. /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
  506. {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0}
  507. };
  508. /* PEX - electrical configuration seq Rev 1.2 */
  509. struct op_params pex_electrical_config_serdes_rev1_params[] = {
  510. /*
  511. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  512. * num_of_loops
  513. */
  514. /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
  515. {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
  516. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  517. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  518. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  519. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  520. /* CFG_DFE_EN_SEL */
  521. {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
  522. /* FFE Setting Force, RES and CAP */
  523. {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0},
  524. /* tximpcal_th and rximpcal_th */
  525. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  526. /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
  527. {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0},
  528. };
  529. /* PEX - electrical configuration seq Rev 2.1 */
  530. struct op_params pex_electrical_config_serdes_rev2_params[] = {
  531. /*
  532. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  533. * num_of_loops
  534. */
  535. /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
  536. {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
  537. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  538. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  539. /* G1 FFE Setting Force, RES and CAP */
  540. {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  541. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  542. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  543. /* G2 FFE Setting Force, RES and CAP */
  544. {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0},
  545. /* G2 DFE resolution value */
  546. {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
  547. /* DFE resolution force */
  548. {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0},
  549. /* Tx amplitude for Tx Margin 0 */
  550. {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0},
  551. /* Tx_Emph value for -3.5d_b and -6d_b */
  552. {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0},
  553. /* CFG_DFE_EN_SEL */
  554. {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
  555. /* tximpcal_th and rximpcal_th */
  556. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  557. /* Force receiver detected */
  558. {LANE_CFG0_REG, 0x800, 0x8000, {0x8000}, 0, 0},
  559. };
  560. /* PEX - configuration seq for REF_CLOCK_25MHz */
  561. struct op_params pex_config_ref_clock25_m_hz[] = {
  562. /*
  563. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  564. * num_of_loops
  565. */
  566. /* Bits[4:0]=0x2 - REF_FREF_SEL */
  567. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0},
  568. /* Bit[10]=0x1 - REFCLK_SEL */
  569. {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
  570. /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */
  571. {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0},
  572. };
  573. /* PEX - configuration seq for REF_CLOCK_40MHz */
  574. struct op_params pex_config_ref_clock40_m_hz[] = {
  575. /*
  576. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  577. * num_of_loops
  578. */
  579. /* Bits[4:0]=0x3 - REF_FREF_SEL */
  580. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0},
  581. /* Bits[10]=0x1 - REFCLK_SEL */
  582. {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
  583. /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */
  584. {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0},
  585. };
  586. /* PEX - configuration seq for REF_CLOCK_100MHz */
  587. struct op_params pex_config_ref_clock100_m_hz[] = {
  588. /*
  589. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  590. * num_of_loops
  591. */
  592. /* Bits[4:0]=0x0 - REF_FREF_SEL */
  593. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0},
  594. /* Bit[10]=0x0 - REFCLK_SEL */
  595. {MISC_REG, 0x800, 0x400, {0x0}, 0, 0},
  596. /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */
  597. {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0},
  598. };
  599. /*
  600. * USB2
  601. */
  602. struct op_params usb2_power_up_params[] = {
  603. /*
  604. * unit_base_reg, unit_offset, mask, USB2 data, wait_time,
  605. * num_of_loops
  606. */
  607. /* Init phy 0 */
  608. {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  609. /* Init phy 1 */
  610. {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  611. /* Init phy 2 */
  612. {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  613. /* Phy offset 0x0 - PLL_CONTROL0 */
  614. {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0},
  615. {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  616. {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  617. {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  618. /* Phy offset 0x1 - PLL_CONTROL1 */
  619. {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0},
  620. /* Phy0 register 3 - TX Channel control 0 */
  621. {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  622. /* Phy0 register 3 - TX Channel control 0 */
  623. {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  624. /* Phy0 register 3 - TX Channel control 0 */
  625. {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  626. /* check PLLCAL_DONE is set and IMPCAL_DONE is set */
  627. {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
  628. /* check REG_SQCAL_DONE is set */
  629. {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
  630. /* check PLL_READY is set */
  631. {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}
  632. };
  633. /*
  634. * QSGMII
  635. */
  636. /* QSGMII - power up seq */
  637. struct op_params qsgmii_port_power_up_params[] = {
  638. /*
  639. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  640. * num_of_loops
  641. */
  642. /* Connect the QSGMII to Gigabit Ethernet units */
  643. {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0},
  644. /* Power Up */
  645. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0},
  646. /* Unreset */
  647. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0},
  648. /* Phy Selector */
  649. {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0},
  650. /* Ref clock source select */
  651. {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0}
  652. };
  653. /* QSGMII - speed config seq */
  654. struct op_params qsgmii_port_speed_config_params[] = {
  655. /*
  656. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  657. * num_of_loops
  658. */
  659. /* Baud Rate */
  660. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0},
  661. /* Phy Gen RX and TX */
  662. {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0},
  663. /* Bus Width */
  664. {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0}
  665. };
  666. /* QSGMII - Select electrical param seq */
  667. struct op_params qsgmii_port_electrical_config_params[] = {
  668. /*
  669. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  670. * num_of_loops
  671. */
  672. /* Slew rate and emphasis */
  673. {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0}
  674. };
  675. /* QSGMII - TX config seq */
  676. struct op_params qsgmii_port_tx_config_params1[] = {
  677. /*
  678. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  679. * num_of_loops
  680. */
  681. {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0},
  682. /* Sft Reset pulse */
  683. {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0},
  684. /* Sft Reset pulse */
  685. {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0},
  686. /* Lane align */
  687. {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0},
  688. /* Power up PLL, RX and TX */
  689. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0},
  690. /* Tx driver output idle */
  691. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0}
  692. };
  693. struct op_params qsgmii_port_tx_config_params2[] = {
  694. /*
  695. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  696. * num_of_loops
  697. */
  698. /* Wait for PHY power up sequence to finish */
  699. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000},
  700. /* Assert Rx Init and Tx driver output valid */
  701. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0},
  702. /* Wait for PHY power up sequence to finish */
  703. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000},
  704. /* De-assert Rx Init */
  705. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0}
  706. };
  707. /* SERDES_POWER_DOWN */
  708. struct op_params serdes_power_down_params[] = {
  709. {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)},
  710. 0, 0},
  711. {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0}
  712. };
  713. /*
  714. * hws_ctrl_serdes_rev_get
  715. *
  716. * DESCRIPTION: Get the Serdes revision number
  717. *
  718. * INPUT: config_field - Field description enum
  719. *
  720. * OUTPUT: None
  721. *
  722. * RETURN:
  723. * 8bit Serdes revision number
  724. */
  725. u8 hws_ctrl_serdes_rev_get(void)
  726. {
  727. #ifdef CONFIG_ARMADA_38X
  728. /* for A38x-Z1 */
  729. if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
  730. return MV_SERDES_REV_1_2;
  731. #endif
  732. /* for A39x-Z1, A38x-A0 */
  733. return MV_SERDES_REV_2_1;
  734. }
  735. u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id,
  736. enum serdes_mode serdes_mode)
  737. {
  738. u32 test_result = 0;
  739. u8 serd_max_num, unit_numb;
  740. enum unit_id unit_id;
  741. if (serdes_type > RXAUI) {
  742. printf("%s: Warning: Wrong serdes type %s serdes#%d\n",
  743. __func__, serdes_type_to_string[serdes_type], serdes_id);
  744. return MV_FAIL;
  745. }
  746. unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id;
  747. unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num;
  748. serd_max_num = sys_env_unit_max_num_get(unit_id);
  749. /* if didn't exceed amount of required Serdes lanes for current type */
  750. if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) {
  751. /* update amount of required Serdes lanes for current type */
  752. serdes_lane_in_use_count[unit_id][unit_numb]--;
  753. /*
  754. * If reached the exact amount of required Serdes lanes for
  755. * current type
  756. */
  757. if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) {
  758. if (((serdes_type <= PEX3)) &&
  759. ((serdes_mode == PEX_END_POINT_X4) ||
  760. (serdes_mode == PEX_ROOT_COMPLEX_X4))) {
  761. /* PCiex4 uses 2 SerDes */
  762. serdes_unit_count[PEX_UNIT_ID] += 2;
  763. } else {
  764. serdes_unit_count[unit_id]++;
  765. }
  766. /* test SoC unit count limitation */
  767. if (serdes_unit_count[unit_id] > serd_max_num) {
  768. test_result = WRONG_NUMBER_OF_UNITS;
  769. } else if (unit_numb >= serd_max_num) {
  770. /* test SoC unit number limitation */
  771. test_result = UNIT_NUMBER_VIOLATION;
  772. }
  773. }
  774. } else {
  775. test_result = SERDES_ALREADY_IN_USE;
  776. }
  777. if (test_result == SERDES_ALREADY_IN_USE) {
  778. printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
  779. __func__, serdes_id,
  780. serdes_type_to_string[serdes_type]);
  781. return MV_FAIL;
  782. } else if (test_result == WRONG_NUMBER_OF_UNITS) {
  783. printf("%s: Warning: serdes lane %d is set to type %s.\n",
  784. __func__, serdes_id,
  785. serdes_type_to_string[serdes_type]);
  786. printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
  787. __func__, serd_max_num);
  788. return MV_FAIL;
  789. } else if (test_result == UNIT_NUMBER_VIOLATION) {
  790. printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
  791. __func__, serdes_id,
  792. serdes_type_to_string[serdes_type],
  793. serd_max_num);
  794. return MV_FAIL;
  795. }
  796. return MV_OK;
  797. }
  798. void hws_serdes_xaui_topology_verify(void)
  799. {
  800. /*
  801. * If XAUI is in use - serdes_lane_in_use_count has to be = 0;
  802. * if it is not in use hast be = 4
  803. */
  804. if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) &&
  805. (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) {
  806. printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n",
  807. __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]);
  808. printf("%s: XAUI has to be defined on 4 lanes\n", __func__);
  809. }
  810. /*
  811. * If RXAUI is in use - serdes_lane_in_use_count has to be = 0;
  812. * if it is not in use hast be = 2
  813. */
  814. if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) &&
  815. (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) {
  816. printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n",
  817. __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]);
  818. printf("%s: RXAUI has to be defined on 2 lanes\n", __func__);
  819. }
  820. }
  821. int hws_serdes_seq_db_init(void)
  822. {
  823. u8 serdes_rev = hws_ctrl_serdes_rev_get();
  824. DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n");
  825. if (serdes_rev == MV_SERDES_REV_NA) {
  826. printf("hws_serdes_seq_db_init: serdes revision number is not supported\n");
  827. return MV_NOT_SUPPORTED;
  828. }
  829. /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */
  830. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr =
  831. sata_port0_power_up_params;
  832. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size =
  833. sizeof(sata_port0_power_up_params) / sizeof(struct op_params);
  834. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
  835. /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */
  836. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr =
  837. sata_port1_power_up_params;
  838. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size =
  839. sizeof(sata_port1_power_up_params) / sizeof(struct op_params);
  840. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
  841. /* SATA_POWER_UP_SEQ sequence init */
  842. serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr =
  843. sata_and_sgmii_power_up_params;
  844. serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size =
  845. sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
  846. serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA;
  847. /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */
  848. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr =
  849. sata_and_sgmii_speed_config_params;
  850. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  851. sizeof(sata_and_sgmii_speed_config_params) /
  852. sizeof(struct op_params);
  853. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  854. /* SATA_3_SPEED_CONFIG_SEQ sequence init */
  855. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr =
  856. sata_and_sgmii_speed_config_params;
  857. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size =
  858. sizeof(sata_and_sgmii_speed_config_params) /
  859. sizeof(struct op_params);
  860. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  861. /* SATA_6_SPEED_CONFIG_SEQ sequence init */
  862. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr =
  863. sata_and_sgmii_speed_config_params;
  864. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size =
  865. sizeof(sata_and_sgmii_speed_config_params) /
  866. sizeof(struct op_params);
  867. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  868. /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */
  869. if (serdes_rev == MV_SERDES_REV_1_2) {
  870. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  871. sata_electrical_config_serdes_rev1_params;
  872. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  873. sizeof(sata_electrical_config_serdes_rev1_params) /
  874. sizeof(struct op_params);
  875. } else {
  876. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  877. sata_electrical_config_serdes_rev2_params;
  878. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  879. sizeof(sata_electrical_config_serdes_rev2_params) /
  880. sizeof(struct op_params);
  881. }
  882. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA;
  883. /* SATA_TX_CONFIG_SEQ sequence init */
  884. serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr =
  885. sata_and_sgmii_tx_config_params1;
  886. serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size =
  887. sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
  888. serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA;
  889. /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */
  890. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr =
  891. sata_port0_tx_config_params;
  892. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
  893. sizeof(sata_port0_tx_config_params) / sizeof(struct op_params);
  894. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
  895. /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */
  896. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr =
  897. sata_port1_tx_config_params;
  898. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
  899. sizeof(sata_port1_tx_config_params) / sizeof(struct op_params);
  900. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
  901. /* SATA_TX_CONFIG_SEQ2 sequence init */
  902. if (serdes_rev == MV_SERDES_REV_1_2) {
  903. serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
  904. sata_and_sgmii_tx_config_serdes_rev1_params2;
  905. serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
  906. sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
  907. sizeof(struct op_params);
  908. } else {
  909. serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
  910. sata_and_sgmii_tx_config_serdes_rev2_params2;
  911. serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
  912. sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
  913. sizeof(struct op_params);
  914. }
  915. serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA;
  916. /* SGMII_POWER_UP_SEQ sequence init */
  917. serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr =
  918. sata_and_sgmii_power_up_params;
  919. serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size =
  920. sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
  921. serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII;
  922. /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */
  923. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr =
  924. sata_and_sgmii_speed_config_params;
  925. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size =
  926. sizeof(sata_and_sgmii_speed_config_params) /
  927. sizeof(struct op_params);
  928. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII;
  929. /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */
  930. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr =
  931. sata_and_sgmii_speed_config_params;
  932. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size =
  933. sizeof(sata_and_sgmii_speed_config_params) /
  934. sizeof(struct op_params);
  935. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125;
  936. /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
  937. if (serdes_rev == MV_SERDES_REV_1_2) {
  938. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  939. sgmii_electrical_config_serdes_rev1_params;
  940. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  941. sizeof(sgmii_electrical_config_serdes_rev1_params) /
  942. sizeof(struct op_params);
  943. } else {
  944. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  945. sgmii_electrical_config_serdes_rev2_params;
  946. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  947. sizeof(sgmii_electrical_config_serdes_rev2_params) /
  948. sizeof(struct op_params);
  949. }
  950. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII;
  951. /* SGMII_TX_CONFIG_SEQ sequence init */
  952. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr =
  953. sata_and_sgmii_tx_config_params1;
  954. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size =
  955. sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
  956. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII;
  957. /* SGMII_TX_CONFIG_SEQ sequence init */
  958. if (serdes_rev == MV_SERDES_REV_1_2) {
  959. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
  960. sata_and_sgmii_tx_config_serdes_rev1_params2;
  961. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  962. sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
  963. sizeof(struct op_params);
  964. } else {
  965. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
  966. sata_and_sgmii_tx_config_serdes_rev2_params2;
  967. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  968. sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
  969. sizeof(struct op_params);
  970. }
  971. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII;
  972. /* PEX_POWER_UP_SEQ sequence init */
  973. if (serdes_rev == MV_SERDES_REV_1_2) {
  974. serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
  975. pex_and_usb3_power_up_serdes_rev1_params;
  976. serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
  977. sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
  978. sizeof(struct op_params);
  979. } else {
  980. serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
  981. pex_and_usb3_power_up_serdes_rev2_params;
  982. serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
  983. sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
  984. sizeof(struct op_params);
  985. }
  986. serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX;
  987. /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */
  988. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr =
  989. pex_and_usb3_speed_config_params;
  990. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  991. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  992. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx =
  993. PEXSERDES_SPEED_2_5_GBPS;
  994. /* PEX_5_SPEED_CONFIG_SEQ sequence init */
  995. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr =
  996. pex_and_usb3_speed_config_params;
  997. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  998. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  999. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx =
  1000. PEXSERDES_SPEED_5_GBPS;
  1001. /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1002. if (serdes_rev == MV_SERDES_REV_1_2) {
  1003. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1004. pex_electrical_config_serdes_rev1_params;
  1005. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1006. sizeof(pex_electrical_config_serdes_rev1_params) /
  1007. sizeof(struct op_params);
  1008. } else {
  1009. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1010. pex_electrical_config_serdes_rev2_params;
  1011. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1012. sizeof(pex_electrical_config_serdes_rev2_params) /
  1013. sizeof(struct op_params);
  1014. }
  1015. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX;
  1016. /* PEX_TX_CONFIG_SEQ1 sequence init */
  1017. serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr =
  1018. pex_and_usb3_tx_config_params1;
  1019. serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size =
  1020. sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
  1021. serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX;
  1022. /* PEX_TX_CONFIG_SEQ2 sequence init */
  1023. serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr =
  1024. pex_and_usb3_tx_config_params2;
  1025. serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size =
  1026. sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
  1027. serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX;
  1028. /* PEX_TX_CONFIG_SEQ3 sequence init */
  1029. serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr =
  1030. pex_and_usb3_tx_config_params3;
  1031. serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size =
  1032. sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
  1033. serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX;
  1034. /* PEX_BY_4_CONFIG_SEQ sequence init */
  1035. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr =
  1036. pex_by4_config_params;
  1037. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size =
  1038. sizeof(pex_by4_config_params) / sizeof(struct op_params);
  1039. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX;
  1040. /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */
  1041. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr =
  1042. pex_config_ref_clock25_m_hz;
  1043. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size =
  1044. sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params);
  1045. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX;
  1046. /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */
  1047. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr =
  1048. pex_config_ref_clock40_m_hz;
  1049. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size =
  1050. sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params);
  1051. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX;
  1052. /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */
  1053. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr =
  1054. pex_config_ref_clock100_m_hz;
  1055. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size =
  1056. sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params);
  1057. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX;
  1058. /* USB3_POWER_UP_SEQ sequence init */
  1059. if (serdes_rev == MV_SERDES_REV_1_2) {
  1060. serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
  1061. pex_and_usb3_power_up_serdes_rev1_params;
  1062. serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
  1063. sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
  1064. sizeof(struct op_params);
  1065. } else {
  1066. serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
  1067. pex_and_usb3_power_up_serdes_rev2_params;
  1068. serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
  1069. sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
  1070. sizeof(struct op_params);
  1071. }
  1072. serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3;
  1073. /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */
  1074. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr =
  1075. pex_and_usb3_speed_config_params;
  1076. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size =
  1077. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  1078. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx =
  1079. USB3SERDES_SPEED_5_GBPS_HOST;
  1080. /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */
  1081. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr =
  1082. pex_and_usb3_speed_config_params;
  1083. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size =
  1084. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  1085. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx =
  1086. USB3SERDES_SPEED_5_GBPS_DEVICE;
  1087. /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1088. if (serdes_rev == MV_SERDES_REV_1_2) {
  1089. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1090. usb3_electrical_config_serdes_rev1_params;
  1091. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1092. sizeof(usb3_electrical_config_serdes_rev1_params) /
  1093. sizeof(struct op_params);
  1094. } else {
  1095. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1096. usb3_electrical_config_serdes_rev2_params;
  1097. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1098. sizeof(usb3_electrical_config_serdes_rev2_params) /
  1099. sizeof(struct op_params);
  1100. }
  1101. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3;
  1102. /* USB3_TX_CONFIG_SEQ sequence init */
  1103. serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr =
  1104. pex_and_usb3_tx_config_params1;
  1105. serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size =
  1106. sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
  1107. serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3;
  1108. /* USB3_TX_CONFIG_SEQ sequence init */
  1109. serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr =
  1110. pex_and_usb3_tx_config_params2;
  1111. serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size =
  1112. sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
  1113. serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3;
  1114. /* USB3_TX_CONFIG_SEQ sequence init */
  1115. serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr =
  1116. pex_and_usb3_tx_config_params3;
  1117. serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size =
  1118. sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
  1119. serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3;
  1120. /* USB2_POWER_UP_SEQ sequence init */
  1121. serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params;
  1122. serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size =
  1123. sizeof(usb2_power_up_params) / sizeof(struct op_params);
  1124. serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0;
  1125. /* USB3_DEVICE_CONFIG_SEQ sequence init */
  1126. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr =
  1127. usb3_device_config_params;
  1128. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size =
  1129. sizeof(usb3_device_config_params) / sizeof(struct op_params);
  1130. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */
  1131. /* SERDES_POWER_DOWN_SEQ sequence init */
  1132. serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr =
  1133. serdes_power_down_params;
  1134. serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size =
  1135. sizeof(serdes_power_down_params) /
  1136. sizeof(struct op_params);
  1137. serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL;
  1138. if (serdes_rev == MV_SERDES_REV_2_1) {
  1139. /* QSGMII_POWER_UP_SEQ sequence init */
  1140. serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr =
  1141. qsgmii_port_power_up_params;
  1142. serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size =
  1143. sizeof(qsgmii_port_power_up_params) /
  1144. sizeof(struct op_params);
  1145. serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx =
  1146. QSGMII_SEQ_IDX;
  1147. /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */
  1148. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr =
  1149. qsgmii_port_speed_config_params;
  1150. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  1151. sizeof(qsgmii_port_speed_config_params) /
  1152. sizeof(struct op_params);
  1153. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx =
  1154. QSGMII_SEQ_IDX;
  1155. /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1156. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1157. qsgmii_port_electrical_config_params;
  1158. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1159. sizeof(qsgmii_port_electrical_config_params) /
  1160. sizeof(struct op_params);
  1161. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx =
  1162. QSGMII_SEQ_IDX;
  1163. /* QSGMII_TX_CONFIG_SEQ sequence init */
  1164. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr =
  1165. qsgmii_port_tx_config_params1;
  1166. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size =
  1167. sizeof(qsgmii_port_tx_config_params1) /
  1168. sizeof(struct op_params);
  1169. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx =
  1170. QSGMII_SEQ_IDX;
  1171. /* QSGMII_TX_CONFIG_SEQ sequence init */
  1172. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr =
  1173. qsgmii_port_tx_config_params2;
  1174. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  1175. sizeof(qsgmii_port_tx_config_params2) /
  1176. sizeof(struct op_params);
  1177. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx =
  1178. QSGMII_SEQ_IDX;
  1179. }
  1180. return MV_OK;
  1181. }
  1182. enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
  1183. enum serdes_speed baud_rate)
  1184. {
  1185. enum serdes_seq seq_id = SERDES_LAST_SEQ;
  1186. DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n");
  1187. switch (serdes_type) {
  1188. case PEX0:
  1189. case PEX1:
  1190. case PEX2:
  1191. case PEX3:
  1192. if (baud_rate == SERDES_SPEED_2_5_GBPS)
  1193. seq_id = PEX_2_5_SPEED_CONFIG_SEQ;
  1194. else if (baud_rate == SERDES_SPEED_5_GBPS)
  1195. seq_id = PEX_5_SPEED_CONFIG_SEQ;
  1196. break;
  1197. case USB3_HOST0:
  1198. case USB3_HOST1:
  1199. if (baud_rate == SERDES_SPEED_5_GBPS)
  1200. seq_id = USB3_HOST_SPEED_CONFIG_SEQ;
  1201. break;
  1202. case USB3_DEVICE:
  1203. if (baud_rate == SERDES_SPEED_5_GBPS)
  1204. seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ;
  1205. break;
  1206. case SATA0:
  1207. case SATA1:
  1208. case SATA2:
  1209. case SATA3:
  1210. if (baud_rate == SERDES_SPEED_1_5_GBPS)
  1211. seq_id = SATA_1_5_SPEED_CONFIG_SEQ;
  1212. else if (baud_rate == SERDES_SPEED_3_GBPS)
  1213. seq_id = SATA_3_SPEED_CONFIG_SEQ;
  1214. else if (baud_rate == SERDES_SPEED_6_GBPS)
  1215. seq_id = SATA_6_SPEED_CONFIG_SEQ;
  1216. break;
  1217. case SGMII0:
  1218. case SGMII1:
  1219. case SGMII2:
  1220. #ifdef CONFIG_ARMADA_39X
  1221. case SGMII3:
  1222. #endif
  1223. if (baud_rate == SERDES_SPEED_1_25_GBPS)
  1224. seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
  1225. else if (baud_rate == SERDES_SPEED_3_125_GBPS)
  1226. seq_id = SGMII_3_125_SPEED_CONFIG_SEQ;
  1227. break;
  1228. case QSGMII:
  1229. seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
  1230. break;
  1231. #ifdef CONFIG_ARMADA_39X
  1232. case XAUI:
  1233. seq_id = XAUI_3_125_SPEED_CONFIG_SEQ;
  1234. break;
  1235. case RXAUI:
  1236. seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ;
  1237. break;
  1238. #endif
  1239. default:
  1240. return SERDES_LAST_SEQ;
  1241. }
  1242. return seq_id;
  1243. }
  1244. static void print_topology_details(const struct serdes_map *serdes_map,
  1245. u8 count)
  1246. {
  1247. u32 lane_num;
  1248. DEBUG_INIT_S("board SerDes lanes topology details:\n");
  1249. DEBUG_INIT_S(" | Lane # | Speed | Type |\n");
  1250. DEBUG_INIT_S(" --------------------------------\n");
  1251. for (lane_num = 0; lane_num < count; lane_num++) {
  1252. if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES)
  1253. continue;
  1254. DEBUG_INIT_S(" | ");
  1255. DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1);
  1256. DEBUG_INIT_S(" | ");
  1257. DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2);
  1258. DEBUG_INIT_S(" | ");
  1259. DEBUG_INIT_S((char *)
  1260. serdes_type_to_string[serdes_map[lane_num].
  1261. serdes_type]);
  1262. DEBUG_INIT_S("\t|\n");
  1263. }
  1264. DEBUG_INIT_S(" --------------------------------\n");
  1265. }
  1266. int hws_pre_serdes_init_config(void)
  1267. {
  1268. u32 data;
  1269. /*
  1270. * Configure Core PLL
  1271. */
  1272. /*
  1273. * set PLL parameters
  1274. * bits[2:0] =0x3 (Core-PLL Kdiv)
  1275. * bits[20:12]=0x9f (Core-PLL Ndiv)
  1276. * bits[24:21]=0x7(Core-PLL VCO Band)
  1277. * bits[28:25]=0x1(Core-PLL Rlf)
  1278. * bits[31:29]=0x2(Core-PLL charge-pump adjust)
  1279. */
  1280. reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003);
  1281. /* Enable PLL Configuration */
  1282. data = reg_read(CORE_PLL_CONFIG_REG);
  1283. data = SET_BIT(data, 9);
  1284. reg_write(CORE_PLL_CONFIG_REG, data);
  1285. return MV_OK;
  1286. }
  1287. int serdes_phy_config(void)
  1288. {
  1289. struct serdes_map *serdes_map;
  1290. u8 serdes_count;
  1291. DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
  1292. DEBUG_INIT_S("High speed PHY - Version: ");
  1293. DEBUG_INIT_S(SERDES_VERSION);
  1294. DEBUG_INIT_S("\n");
  1295. /* Init serdes sequences DB */
  1296. if (hws_serdes_seq_init() != MV_OK) {
  1297. printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n");
  1298. return MV_FAIL;
  1299. }
  1300. /* Board topology load */
  1301. DEBUG_INIT_FULL_S
  1302. ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");
  1303. CHECK_STATUS(hws_board_topology_load(&serdes_map, &serdes_count));
  1304. if (serdes_count > hws_serdes_get_max_lane()) {
  1305. printf("Error: too many serdes lanes specified by board\n");
  1306. return MV_FAIL;
  1307. }
  1308. /* print topology */
  1309. print_topology_details(serdes_map, serdes_count);
  1310. CHECK_STATUS(hws_pre_serdes_init_config());
  1311. /* Power-Up sequence */
  1312. DEBUG_INIT_FULL_S
  1313. ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n");
  1314. CHECK_STATUS(hws_power_up_serdes_lanes(serdes_map, serdes_count));
  1315. DEBUG_INIT_FULL_S
  1316. ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n");
  1317. DEBUG_INIT_S(ENDED_OK);
  1318. return MV_OK;
  1319. }
  1320. int serdes_polarity_config(u32 serdes_num, int is_rx)
  1321. {
  1322. u32 data;
  1323. u32 reg_addr;
  1324. u8 bit_off = (is_rx) ? 11 : 10;
  1325. reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG;
  1326. data = reg_read(reg_addr);
  1327. data = SET_BIT(data, bit_off);
  1328. reg_write(reg_addr, data);
  1329. return MV_OK;
  1330. }
  1331. int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count)
  1332. {
  1333. u32 serdes_id, serdes_lane_num;
  1334. enum ref_clock ref_clock;
  1335. enum serdes_type serdes_type;
  1336. enum serdes_speed serdes_speed;
  1337. enum serdes_mode serdes_mode;
  1338. int serdes_rx_polarity_swap;
  1339. int serdes_tx_polarity_swap;
  1340. int is_pex_enabled = 0;
  1341. /*
  1342. * is_pex_enabled:
  1343. * Flag which indicates that one of the Serdes is of PEX.
  1344. * In this case, PEX unit will be initialized after Serdes power-up
  1345. */
  1346. DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n");
  1347. /* COMMON PHYS SELECTORS register configuration */
  1348. DEBUG_INIT_FULL_S
  1349. ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n");
  1350. CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_map, count));
  1351. /* per Serdes Power Up */
  1352. for (serdes_id = 0; serdes_id < count; serdes_id++) {
  1353. DEBUG_INIT_FULL_S
  1354. ("calling serdes_power_up_ctrl: serdes lane number ");
  1355. DEBUG_INIT_FULL_D_10(serdes_lane_num, 1);
  1356. DEBUG_INIT_FULL_S("\n");
  1357. serdes_lane_num = hws_get_physical_serdes_num(serdes_id);
  1358. serdes_type = serdes_map[serdes_id].serdes_type;
  1359. serdes_speed = serdes_map[serdes_id].serdes_speed;
  1360. serdes_mode = serdes_map[serdes_id].serdes_mode;
  1361. serdes_rx_polarity_swap = serdes_map[serdes_id].swap_rx;
  1362. serdes_tx_polarity_swap = serdes_map[serdes_id].swap_tx;
  1363. /* serdes lane is not in use */
  1364. if (serdes_type == DEFAULT_SERDES)
  1365. continue;
  1366. else if (serdes_type <= PEX3) /* PEX type */
  1367. is_pex_enabled = 1;
  1368. ref_clock = hws_serdes_get_ref_clock_val(serdes_type);
  1369. if (ref_clock == REF_CLOCK_UNSUPPORTED) {
  1370. DEBUG_INIT_S
  1371. ("hws_power_up_serdes_lanes: unsupported ref clock\n");
  1372. return MV_NOT_SUPPORTED;
  1373. }
  1374. CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num,
  1375. 1,
  1376. serdes_type,
  1377. serdes_speed,
  1378. serdes_mode, ref_clock));
  1379. /* RX Polarity config */
  1380. if (serdes_rx_polarity_swap)
  1381. CHECK_STATUS(serdes_polarity_config
  1382. (serdes_lane_num, 1));
  1383. /* TX Polarity config */
  1384. if (serdes_tx_polarity_swap)
  1385. CHECK_STATUS(serdes_polarity_config
  1386. (serdes_lane_num, 0));
  1387. }
  1388. if (is_pex_enabled) {
  1389. /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode.
  1390. After finish the Power_up sequence for all lanes,
  1391. the lanes should be released from reset state. */
  1392. CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count));
  1393. /* PEX configuration */
  1394. CHECK_STATUS(hws_pex_config(serdes_map, count));
  1395. }
  1396. /* USB2 configuration */
  1397. DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n");
  1398. CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ));
  1399. DEBUG_INIT_FULL_S
  1400. ("### hws_power_up_serdes_lanes ended successfully ###\n");
  1401. return MV_OK;
  1402. }
  1403. int ctrl_high_speed_serdes_phy_config(void)
  1404. {
  1405. return hws_ctrl_high_speed_serdes_phy_config();
  1406. }
  1407. static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type)
  1408. {
  1409. u32 reg_data;
  1410. /* WA for A380 Z1 relevant for lanes 3,4,5 only */
  1411. if (serdes_num >= 3) {
  1412. reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
  1413. /* set delay on pipe -
  1414. * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1.
  1415. * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0.
  1416. * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1.
  1417. * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0.
  1418. * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1.
  1419. * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0.
  1420. */
  1421. if (serdes_type == PEX)
  1422. reg_data |= 1 << (7 + (serdes_num - 3));
  1423. if (serdes_type == USB3) {
  1424. /* USB3 */
  1425. reg_data &= ~(1 << (7 + (serdes_num - 3)));
  1426. }
  1427. reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data);
  1428. }
  1429. return MV_OK;
  1430. }
  1431. /*
  1432. * hws_serdes_pex_ref_clock_satr_get -
  1433. *
  1434. * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG
  1435. * and check:
  1436. * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31]
  1437. * for PEX#3.
  1438. * If bit=0 --> REF_CLOCK_100MHz
  1439. * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0
  1440. * --> REF_CLOCK_25MHz
  1441. * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1
  1442. * --> REF_CLOCK_40MHz
  1443. *
  1444. * INPUT: serdes_type - Type of Serdes
  1445. *
  1446. * OUTPUT: pex_satr - Return the REF_CLOCK value:
  1447. * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz
  1448. *
  1449. * RETURNS: MV_OK - for success
  1450. * MV_BAD_PARAM - for fail
  1451. */
  1452. int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr)
  1453. {
  1454. u32 data, reg_satr1;
  1455. reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
  1456. switch (serdes_type) {
  1457. case PEX0:
  1458. data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1);
  1459. break;
  1460. case PEX1:
  1461. data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1);
  1462. break;
  1463. case PEX2:
  1464. data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1);
  1465. break;
  1466. case PEX3:
  1467. data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1);
  1468. break;
  1469. default:
  1470. printf("%s: Error: SerDes type %d is not supported\n",
  1471. __func__, serdes_type);
  1472. return MV_BAD_PARAM;
  1473. }
  1474. *pex_satr = data;
  1475. return MV_OK;
  1476. }
  1477. u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type)
  1478. {
  1479. u32 pex_satr;
  1480. enum ref_clock ref_clock;
  1481. DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n");
  1482. if (serdes_type >= LAST_SERDES_TYPE)
  1483. return REF_CLOCK_UNSUPPORTED;
  1484. /* read ref clock from S@R */
  1485. ref_clock = hws_serdes_silicon_ref_clock_get();
  1486. if (serdes_type > PEX3) {
  1487. /* for all Serdes types but PCIe */
  1488. return ref_clock;
  1489. }
  1490. /* for PCIe, need also to check PCIe S@R */
  1491. CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get
  1492. (serdes_type, &pex_satr));
  1493. if (pex_satr == 0) {
  1494. return REF_CLOCK_100MHZ;
  1495. } else if (pex_satr == 1) {
  1496. /* value of 1 means we can use ref clock from SoC (as other Serdes types) */
  1497. return ref_clock;
  1498. } else {
  1499. printf
  1500. ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n",
  1501. __func__, serdes_type);
  1502. return REF_CLOCK_UNSUPPORTED;
  1503. }
  1504. }
  1505. int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
  1506. enum serdes_type serdes_type,
  1507. enum serdes_speed baud_rate,
  1508. enum serdes_mode serdes_mode, enum ref_clock ref_clock)
  1509. {
  1510. u32 sata_idx, pex_idx, sata_port;
  1511. enum serdes_seq speed_seq_id;
  1512. u32 reg_data;
  1513. int is_pex_by1;
  1514. DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n");
  1515. if (serdes_power_up == 1) { /* Serdes power up */
  1516. DEBUG_INIT_FULL_S
  1517. ("serdes_power_up_ctrl: executing power up.. ");
  1518. DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2);
  1519. DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2);
  1520. DEBUG_INIT_FULL_S("Going access 1");
  1521. /* Getting the Speed Select sequence id */
  1522. speed_seq_id =
  1523. serdes_type_and_speed_to_speed_seq(serdes_type,
  1524. baud_rate);
  1525. if (speed_seq_id == SERDES_LAST_SEQ) {
  1526. printf
  1527. ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n",
  1528. serdes_type, baud_rate);
  1529. return MV_BAD_PARAM;
  1530. }
  1531. /* Executing power up, ref clock set, speed config and TX config */
  1532. switch (serdes_type) {
  1533. case PEX0:
  1534. case PEX1:
  1535. case PEX2:
  1536. case PEX3:
  1537. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
  1538. CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
  1539. (serdes_num, PEX));
  1540. }
  1541. is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) ||
  1542. (serdes_mode == PEX_END_POINT_X1);
  1543. pex_idx = serdes_type - PEX0;
  1544. if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
  1545. /* For PEX by 4, init only the PEX 0 */
  1546. reg_data = reg_read(SOC_CONTROL_REG1);
  1547. if (is_pex_by1 == 1)
  1548. reg_data |= 0x4000;
  1549. else
  1550. reg_data &= ~0x4000;
  1551. reg_write(SOC_CONTROL_REG1, reg_data);
  1552. reg_data =
  1553. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1554. 0x6c));
  1555. reg_data &= ~0x3f0;
  1556. if (is_pex_by1 == 1)
  1557. reg_data |= 0x10;
  1558. else
  1559. reg_data |= 0x40;
  1560. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
  1561. reg_data);
  1562. reg_data =
  1563. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1564. 0x6c));
  1565. reg_data &= ~0xf;
  1566. reg_data |= 0x2;
  1567. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
  1568. reg_data);
  1569. reg_data =
  1570. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1571. 0x70));
  1572. reg_data &= ~0x40;
  1573. reg_data |= 0x40;
  1574. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
  1575. reg_data);
  1576. }
  1577. CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
  1578. if (is_pex_by1 == 0) {
  1579. /*
  1580. * for PEX by 4 - use the PEX index as the
  1581. * seq array index
  1582. */
  1583. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].
  1584. data_arr_idx = pex_idx;
  1585. CHECK_STATUS(mv_seq_exec
  1586. (serdes_num, PEX_BY_4_CONFIG_SEQ));
  1587. }
  1588. CHECK_STATUS(hws_ref_clock_set
  1589. (serdes_num, serdes_type, ref_clock));
  1590. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1591. CHECK_STATUS(mv_seq_exec
  1592. (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ));
  1593. if (is_pex_by1 == 1) {
  1594. CHECK_STATUS(mv_seq_exec
  1595. (serdes_num, PEX_TX_CONFIG_SEQ2));
  1596. CHECK_STATUS(mv_seq_exec
  1597. (serdes_num, PEX_TX_CONFIG_SEQ3));
  1598. CHECK_STATUS(mv_seq_exec
  1599. (serdes_num, PEX_TX_CONFIG_SEQ1));
  1600. }
  1601. udelay(20);
  1602. break;
  1603. case USB3_HOST0:
  1604. case USB3_HOST1:
  1605. case USB3_DEVICE:
  1606. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
  1607. CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
  1608. (serdes_num, USB3));
  1609. }
  1610. CHECK_STATUS(mv_seq_exec
  1611. (serdes_num, USB3_POWER_UP_SEQ));
  1612. CHECK_STATUS(hws_ref_clock_set
  1613. (serdes_num, serdes_type, ref_clock));
  1614. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1615. if (serdes_type == USB3_DEVICE) {
  1616. CHECK_STATUS(mv_seq_exec
  1617. (serdes_num,
  1618. USB3_DEVICE_CONFIG_SEQ));
  1619. }
  1620. CHECK_STATUS(mv_seq_exec
  1621. (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ));
  1622. CHECK_STATUS(mv_seq_exec
  1623. (serdes_num, USB3_TX_CONFIG_SEQ1));
  1624. CHECK_STATUS(mv_seq_exec
  1625. (serdes_num, USB3_TX_CONFIG_SEQ2));
  1626. CHECK_STATUS(mv_seq_exec
  1627. (serdes_num, USB3_TX_CONFIG_SEQ3));
  1628. udelay(10000);
  1629. break;
  1630. case SATA0:
  1631. case SATA1:
  1632. case SATA2:
  1633. case SATA3:
  1634. sata_idx = ((serdes_type == SATA0) ||
  1635. (serdes_type == SATA1)) ? 0 : 1;
  1636. sata_port = ((serdes_type == SATA0) ||
  1637. (serdes_type == SATA2)) ? 0 : 1;
  1638. CHECK_STATUS(mv_seq_exec
  1639. (sata_idx, (sata_port == 0) ?
  1640. SATA_PORT_0_ONLY_POWER_UP_SEQ :
  1641. SATA_PORT_1_ONLY_POWER_UP_SEQ));
  1642. CHECK_STATUS(mv_seq_exec
  1643. (serdes_num, SATA_POWER_UP_SEQ));
  1644. CHECK_STATUS(hws_ref_clock_set
  1645. (serdes_num, serdes_type, ref_clock));
  1646. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1647. CHECK_STATUS(mv_seq_exec
  1648. (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ));
  1649. CHECK_STATUS(mv_seq_exec
  1650. (serdes_num, SATA_TX_CONFIG_SEQ1));
  1651. CHECK_STATUS(mv_seq_exec
  1652. (sata_idx, (sata_port == 0) ?
  1653. SATA_PORT_0_ONLY_TX_CONFIG_SEQ :
  1654. SATA_PORT_1_ONLY_TX_CONFIG_SEQ));
  1655. CHECK_STATUS(mv_seq_exec
  1656. (serdes_num, SATA_TX_CONFIG_SEQ2));
  1657. udelay(10000);
  1658. break;
  1659. case SGMII0:
  1660. case SGMII1:
  1661. case SGMII2:
  1662. CHECK_STATUS(mv_seq_exec
  1663. (serdes_num, SGMII_POWER_UP_SEQ));
  1664. CHECK_STATUS(hws_ref_clock_set
  1665. (serdes_num, serdes_type, ref_clock));
  1666. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1667. CHECK_STATUS(mv_seq_exec
  1668. (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ));
  1669. CHECK_STATUS(mv_seq_exec
  1670. (serdes_num, SGMII_TX_CONFIG_SEQ1));
  1671. CHECK_STATUS(mv_seq_exec
  1672. (serdes_num, SGMII_TX_CONFIG_SEQ2));
  1673. /* GBE configuration */
  1674. reg_data = reg_read(GBE_CONFIGURATION_REG);
  1675. /* write the SGMII index */
  1676. reg_data |= 0x1 << (serdes_type - SGMII0);
  1677. reg_write(GBE_CONFIGURATION_REG, reg_data);
  1678. break;
  1679. case QSGMII:
  1680. if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1)
  1681. return MV_NOT_SUPPORTED;
  1682. CHECK_STATUS(mv_seq_exec
  1683. (serdes_num, QSGMII_POWER_UP_SEQ));
  1684. CHECK_STATUS(hws_ref_clock_set
  1685. (serdes_num, serdes_type, ref_clock));
  1686. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1687. CHECK_STATUS(mv_seq_exec
  1688. (serdes_num,
  1689. QSGMII_ELECTRICAL_CONFIG_SEQ));
  1690. CHECK_STATUS(mv_seq_exec
  1691. (serdes_num, QSGMII_TX_CONFIG_SEQ1));
  1692. CHECK_STATUS(mv_seq_exec
  1693. (serdes_num, QSGMII_TX_CONFIG_SEQ2));
  1694. break;
  1695. case SGMII3:
  1696. case XAUI:
  1697. case RXAUI:
  1698. CHECK_STATUS(serdes_power_up_ctrl_ext
  1699. (serdes_num, serdes_power_up, serdes_type,
  1700. baud_rate, serdes_mode, ref_clock));
  1701. break;
  1702. default:
  1703. DEBUG_INIT_S
  1704. ("serdes_power_up_ctrl: bad serdes_type parameter\n");
  1705. return MV_BAD_PARAM;
  1706. }
  1707. } else { /* Serdes power down */
  1708. DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. ");
  1709. DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1);
  1710. CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ));
  1711. }
  1712. DEBUG_INIT_FULL_C(
  1713. "serdes_power_up_ctrl ended successfully for serdes ",
  1714. serdes_num, 2);
  1715. return MV_OK;
  1716. }
  1717. int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count)
  1718. {
  1719. u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0;
  1720. enum serdes_type serdes_type;
  1721. enum serdes_mode serdes_mode;
  1722. u8 select_bit_off;
  1723. int is_pex_x4 = 0;
  1724. int updated_topology_print = 0;
  1725. DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n");
  1726. DEBUG_INIT_FULL_S
  1727. ("Updating the COMMON PHYS SELECTORS register with the serdes types\n");
  1728. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2)
  1729. select_bit_off = 3;
  1730. else
  1731. select_bit_off = 4;
  1732. /*
  1733. * Updating bits 0-17 in the COMMON PHYS SELECTORS register
  1734. * according to the serdes types
  1735. */
  1736. for (idx = 0; idx < count; idx++) {
  1737. serdes_type = serdes_map[idx].serdes_type;
  1738. serdes_mode = serdes_map[idx].serdes_mode;
  1739. serdes_lane_hw_num = hws_get_physical_serdes_num(idx);
  1740. lane_data =
  1741. hws_serdes_get_phy_selector_val(serdes_lane_hw_num,
  1742. serdes_type);
  1743. if (serdes_type == DEFAULT_SERDES)
  1744. continue;
  1745. if (hws_serdes_topology_verify
  1746. (serdes_type, idx, serdes_mode) != MV_OK) {
  1747. serdes_map[idx].serdes_type =
  1748. DEFAULT_SERDES;
  1749. printf("%s: SerDes lane #%d is disabled\n", __func__,
  1750. serdes_lane_hw_num);
  1751. updated_topology_print = 1;
  1752. continue;
  1753. }
  1754. /*
  1755. * Checking if the board topology configuration includes
  1756. * PEXx4 - for the next step
  1757. */
  1758. if ((serdes_mode == PEX_END_POINT_X4) ||
  1759. (serdes_mode == PEX_ROOT_COMPLEX_X4)) {
  1760. /* update lane data to the 3 next SERDES lanes */
  1761. lane_data =
  1762. common_phys_selectors_pex_by4_lanes
  1763. [serdes_lane_hw_num];
  1764. if (serdes_type == PEX0)
  1765. is_pex_x4 = 1;
  1766. }
  1767. if (lane_data == NA) {
  1768. printf
  1769. ("%s: Warning: SerDes lane #%d and type %d are not supported together\n",
  1770. __func__, serdes_lane_hw_num, serdes_mode);
  1771. serdes_map[idx].serdes_type = DEFAULT_SERDES;
  1772. printf("%s: SerDes lane #%d is disabled\n", __func__,
  1773. serdes_lane_hw_num);
  1774. continue;
  1775. }
  1776. /*
  1777. * Updating the data that will be written to
  1778. * COMMON_PHYS_SELECTORS_REG
  1779. */
  1780. reg_data |= (lane_data <<
  1781. (select_bit_off * serdes_lane_hw_num));
  1782. }
  1783. /*
  1784. * Check that number of used lanes for XAUI and RXAUI
  1785. * (if used) is right
  1786. */
  1787. hws_serdes_xaui_topology_verify();
  1788. /* Print topology */
  1789. if (updated_topology_print)
  1790. print_topology_details(serdes_map, count);
  1791. /*
  1792. * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS
  1793. * register for PEXx4 mode
  1794. */
  1795. reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0;
  1796. /* Updating the COMMON PHYS SELECTORS register */
  1797. reg_write(COMMON_PHYS_SELECTORS_REG, reg_data);
  1798. return MV_OK;
  1799. }
  1800. int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
  1801. enum ref_clock ref_clock)
  1802. {
  1803. u32 data1 = 0, data2 = 0, data3 = 0, reg_data;
  1804. DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n");
  1805. if (hws_is_serdes_active(serdes_num) != 1) {
  1806. printf("%s: SerDes lane #%d is not Active\n", __func__,
  1807. serdes_num);
  1808. return MV_BAD_PARAM;
  1809. }
  1810. switch (serdes_type) {
  1811. case PEX0:
  1812. case PEX1:
  1813. case PEX2:
  1814. case PEX3:
  1815. switch (ref_clock) {
  1816. case REF_CLOCK_25MHZ:
  1817. CHECK_STATUS(mv_seq_exec
  1818. (serdes_num,
  1819. PEX_CONFIG_REF_CLOCK_25MHZ_SEQ));
  1820. return MV_OK;
  1821. case REF_CLOCK_100MHZ:
  1822. CHECK_STATUS(mv_seq_exec
  1823. (serdes_num,
  1824. PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
  1825. return MV_OK;
  1826. #ifdef CONFIG_ARMADA_39X
  1827. case REF_CLOCK_40MHZ:
  1828. CHECK_STATUS(mv_seq_exec
  1829. (serdes_num,
  1830. PEX_CONFIG_REF_CLOCK_40MHZ_SEQ));
  1831. return MV_OK;
  1832. #endif
  1833. default:
  1834. printf
  1835. ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
  1836. __func__, ref_clock, serdes_num, serdes_type);
  1837. return MV_BAD_PARAM;
  1838. }
  1839. case USB3_HOST0:
  1840. case USB3_HOST1:
  1841. case USB3_DEVICE:
  1842. if (ref_clock == REF_CLOCK_25MHZ) {
  1843. data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2;
  1844. data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL;
  1845. data3 = LANE_CFG4_REG_25MHZ_VAL;
  1846. } else if (ref_clock == REF_CLOCK_40MHZ) {
  1847. data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
  1848. data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL;
  1849. data3 = LANE_CFG4_REG_40MHZ_VAL;
  1850. } else {
  1851. printf
  1852. ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
  1853. serdes_type);
  1854. return MV_BAD_PARAM;
  1855. }
  1856. break;
  1857. case SATA0:
  1858. case SATA1:
  1859. case SATA2:
  1860. case SATA3:
  1861. case SGMII0:
  1862. case SGMII1:
  1863. case SGMII2:
  1864. case QSGMII:
  1865. if (ref_clock == REF_CLOCK_25MHZ) {
  1866. data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
  1867. } else if (ref_clock == REF_CLOCK_40MHZ) {
  1868. data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
  1869. } else {
  1870. printf
  1871. ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
  1872. serdes_type);
  1873. return MV_BAD_PARAM;
  1874. }
  1875. break;
  1876. #ifdef CONFIG_ARMADA_39X
  1877. case SGMII3:
  1878. case XAUI:
  1879. case RXAUI:
  1880. if (ref_clock == REF_CLOCK_25MHZ) {
  1881. data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
  1882. } else if (ref_clock == REF_CLOCK_40MHZ) {
  1883. data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
  1884. } else {
  1885. printf
  1886. ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
  1887. serdes_type);
  1888. return MV_BAD_PARAM;
  1889. }
  1890. break;
  1891. #endif
  1892. default:
  1893. DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
  1894. return MV_BAD_PARAM;
  1895. }
  1896. /*
  1897. * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and
  1898. * offset
  1899. */
  1900. reg_data = reg_read(POWER_AND_PLL_CTRL_REG +
  1901. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1902. reg_data &= POWER_AND_PLL_CTRL_REG_MASK;
  1903. reg_data |= data1;
  1904. reg_write(POWER_AND_PLL_CTRL_REG +
  1905. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1906. if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) ||
  1907. (serdes_type == USB3_DEVICE)) {
  1908. reg_data = reg_read(GLOBAL_PM_CTRL +
  1909. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1910. reg_data &= GLOBAL_PM_CTRL_REG_MASK;
  1911. reg_data |= data2;
  1912. reg_write(GLOBAL_PM_CTRL +
  1913. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1914. reg_data = reg_read(LANE_CFG4_REG +
  1915. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1916. reg_data &= LANE_CFG4_REG_MASK;
  1917. reg_data |= data3;
  1918. reg_write(LANE_CFG4_REG +
  1919. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1920. }
  1921. return MV_OK;
  1922. }
  1923. /*
  1924. * hws_pex_tx_config_seq -
  1925. *
  1926. * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode
  1927. * INPUT: serdes_map - The board topology map
  1928. * OUTPUT: None
  1929. * RETURNS: MV_OK - for success
  1930. * MV_BAD_PARAM - for fail
  1931. */
  1932. int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count)
  1933. {
  1934. enum serdes_mode serdes_mode;
  1935. u32 serdes_lane_id, serdes_lane_hw_num;
  1936. DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n");
  1937. /*
  1938. * For PEXx4: the pex_and_usb3_tx_config_params1/2/3
  1939. * configurations should run by setting each sequence for
  1940. * all 4 lanes.
  1941. */
  1942. /* relese pipe soft reset for all lanes */
  1943. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1944. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1945. serdes_lane_hw_num =
  1946. hws_get_physical_serdes_num(serdes_lane_id);
  1947. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1948. (serdes_mode == PEX_END_POINT_X4)) {
  1949. CHECK_STATUS(mv_seq_exec
  1950. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1));
  1951. }
  1952. }
  1953. /* set phy soft reset for all lanes */
  1954. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1955. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1956. serdes_lane_hw_num =
  1957. hws_get_physical_serdes_num(serdes_lane_id);
  1958. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1959. (serdes_mode == PEX_END_POINT_X4)) {
  1960. CHECK_STATUS(mv_seq_exec
  1961. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2));
  1962. }
  1963. }
  1964. /* set phy soft reset for all lanes */
  1965. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1966. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1967. serdes_lane_hw_num =
  1968. hws_get_physical_serdes_num(serdes_lane_id);
  1969. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1970. (serdes_mode == PEX_END_POINT_X4)) {
  1971. CHECK_STATUS(mv_seq_exec
  1972. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3));
  1973. }
  1974. }
  1975. return MV_OK;
  1976. }