soc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/bootm.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/dma.h>
  19. #include <asm/mach-imx/hab.h>
  20. #include <stdbool.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <dm.h>
  24. #include <imx_thermal.h>
  25. #include <mmc.h>
  26. struct scu_regs {
  27. u32 ctrl;
  28. u32 config;
  29. u32 status;
  30. u32 invalidate;
  31. u32 fpga_rev;
  32. };
  33. #if defined(CONFIG_IMX_THERMAL)
  34. static const struct imx_thermal_plat imx6_thermal_plat = {
  35. .regs = (void *)ANATOP_BASE_ADDR,
  36. .fuse_bank = 1,
  37. .fuse_word = 6,
  38. };
  39. U_BOOT_DEVICE(imx6_thermal) = {
  40. .name = "imx_thermal",
  41. .platdata = &imx6_thermal_plat,
  42. };
  43. #endif
  44. #if defined(CONFIG_IMX_HAB)
  45. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  46. .bank = 0,
  47. .word = 6,
  48. };
  49. #endif
  50. u32 get_nr_cpus(void)
  51. {
  52. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  53. return readl(&scu->config) & 3;
  54. }
  55. u32 get_cpu_rev(void)
  56. {
  57. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  58. u32 reg = readl(&anatop->digprog_sololite);
  59. u32 type = ((reg >> 16) & 0xff);
  60. u32 major, cfg = 0;
  61. if (type != MXC_CPU_MX6SL) {
  62. reg = readl(&anatop->digprog);
  63. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  64. cfg = readl(&scu->config) & 3;
  65. type = ((reg >> 16) & 0xff);
  66. if (type == MXC_CPU_MX6DL) {
  67. if (!cfg)
  68. type = MXC_CPU_MX6SOLO;
  69. }
  70. if (type == MXC_CPU_MX6Q) {
  71. if (cfg == 1)
  72. type = MXC_CPU_MX6D;
  73. }
  74. if (type == MXC_CPU_MX6ULL) {
  75. if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
  76. type = MXC_CPU_MX6ULZ;
  77. }
  78. }
  79. major = ((reg >> 8) & 0xff);
  80. if ((major >= 1) &&
  81. ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  82. major--;
  83. type = MXC_CPU_MX6QP;
  84. if (cfg == 1)
  85. type = MXC_CPU_MX6DP;
  86. }
  87. reg &= 0xff; /* mx6 silicon revision */
  88. /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
  89. if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
  90. reg = 0x3;
  91. return (type << 12) | (reg + (0x10 * (major + 1)));
  92. }
  93. /*
  94. * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
  95. * defines a 2-bit SPEED_GRADING
  96. */
  97. #define OCOTP_CFG3_SPEED_SHIFT 16
  98. #define OCOTP_CFG3_SPEED_800MHZ 0
  99. #define OCOTP_CFG3_SPEED_850MHZ 1
  100. #define OCOTP_CFG3_SPEED_1GHZ 2
  101. #define OCOTP_CFG3_SPEED_1P2GHZ 3
  102. /*
  103. * For i.MX6UL
  104. */
  105. #define OCOTP_CFG3_SPEED_528MHZ 1
  106. #define OCOTP_CFG3_SPEED_696MHZ 2
  107. /*
  108. * For i.MX6ULL
  109. */
  110. #define OCOTP_CFG3_SPEED_792MHZ 2
  111. #define OCOTP_CFG3_SPEED_900MHZ 3
  112. u32 get_cpu_speed_grade_hz(void)
  113. {
  114. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  115. struct fuse_bank *bank = &ocotp->bank[0];
  116. struct fuse_bank0_regs *fuse =
  117. (struct fuse_bank0_regs *)bank->fuse_regs;
  118. uint32_t val;
  119. val = readl(&fuse->cfg3);
  120. val >>= OCOTP_CFG3_SPEED_SHIFT;
  121. val &= 0x3;
  122. if (is_mx6ul()) {
  123. if (val == OCOTP_CFG3_SPEED_528MHZ)
  124. return 528000000;
  125. else if (val == OCOTP_CFG3_SPEED_696MHZ)
  126. return 696000000;
  127. else
  128. return 0;
  129. }
  130. if (is_mx6ull()) {
  131. if (val == OCOTP_CFG3_SPEED_528MHZ)
  132. return 528000000;
  133. else if (val == OCOTP_CFG3_SPEED_792MHZ)
  134. return 792000000;
  135. else if (val == OCOTP_CFG3_SPEED_900MHZ)
  136. return 900000000;
  137. else
  138. return 0;
  139. }
  140. switch (val) {
  141. /* Valid for IMX6DQ */
  142. case OCOTP_CFG3_SPEED_1P2GHZ:
  143. if (is_mx6dq() || is_mx6dqp())
  144. return 1200000000;
  145. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  146. case OCOTP_CFG3_SPEED_1GHZ:
  147. return 996000000;
  148. /* Valid for IMX6DQ */
  149. case OCOTP_CFG3_SPEED_850MHZ:
  150. if (is_mx6dq() || is_mx6dqp())
  151. return 852000000;
  152. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  153. case OCOTP_CFG3_SPEED_800MHZ:
  154. return 792000000;
  155. }
  156. return 0;
  157. }
  158. /*
  159. * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
  160. * defines a 2-bit Temperature Grade
  161. *
  162. * return temperature grade and min/max temperature in Celsius
  163. */
  164. #define OCOTP_MEM0_TEMP_SHIFT 6
  165. u32 get_cpu_temp_grade(int *minc, int *maxc)
  166. {
  167. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  168. struct fuse_bank *bank = &ocotp->bank[1];
  169. struct fuse_bank1_regs *fuse =
  170. (struct fuse_bank1_regs *)bank->fuse_regs;
  171. uint32_t val;
  172. val = readl(&fuse->mem0);
  173. val >>= OCOTP_MEM0_TEMP_SHIFT;
  174. val &= 0x3;
  175. if (minc && maxc) {
  176. if (val == TEMP_AUTOMOTIVE) {
  177. *minc = -40;
  178. *maxc = 125;
  179. } else if (val == TEMP_INDUSTRIAL) {
  180. *minc = -40;
  181. *maxc = 105;
  182. } else if (val == TEMP_EXTCOMMERCIAL) {
  183. *minc = -20;
  184. *maxc = 105;
  185. } else {
  186. *minc = 0;
  187. *maxc = 95;
  188. }
  189. }
  190. return val;
  191. }
  192. #ifdef CONFIG_REVISION_TAG
  193. u32 __weak get_board_rev(void)
  194. {
  195. u32 cpurev = get_cpu_rev();
  196. u32 type = ((cpurev >> 12) & 0xff);
  197. if (type == MXC_CPU_MX6SOLO)
  198. cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  199. if (type == MXC_CPU_MX6D)
  200. cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  201. return cpurev;
  202. }
  203. #endif
  204. static void clear_ldo_ramp(void)
  205. {
  206. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  207. int reg;
  208. /* ROM may modify LDO ramp up time according to fuse setting, so in
  209. * order to be in the safe side we neeed to reset these settings to
  210. * match the reset value: 0'b00
  211. */
  212. reg = readl(&anatop->ana_misc2);
  213. reg &= ~(0x3f << 24);
  214. writel(reg, &anatop->ana_misc2);
  215. }
  216. /*
  217. * Set the PMU_REG_CORE register
  218. *
  219. * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
  220. * Possible values are from 0.725V to 1.450V in steps of
  221. * 0.025V (25mV).
  222. */
  223. int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
  224. {
  225. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  226. u32 val, step, old, reg = readl(&anatop->reg_core);
  227. u8 shift;
  228. /* No LDO_SOC/PU/ARM */
  229. if (is_mx6sll())
  230. return 0;
  231. if (mv < 725)
  232. val = 0x00; /* Power gated off */
  233. else if (mv > 1450)
  234. val = 0x1F; /* Power FET switched full on. No regulation */
  235. else
  236. val = (mv - 700) / 25;
  237. clear_ldo_ramp();
  238. switch (ldo) {
  239. case LDO_SOC:
  240. shift = 18;
  241. break;
  242. case LDO_PU:
  243. shift = 9;
  244. break;
  245. case LDO_ARM:
  246. shift = 0;
  247. break;
  248. default:
  249. return -EINVAL;
  250. }
  251. old = (reg & (0x1F << shift)) >> shift;
  252. step = abs(val - old);
  253. if (step == 0)
  254. return 0;
  255. reg = (reg & ~(0x1F << shift)) | (val << shift);
  256. writel(reg, &anatop->reg_core);
  257. /*
  258. * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
  259. * step
  260. */
  261. udelay(3 * step);
  262. return 0;
  263. }
  264. static void set_ahb_rate(u32 val)
  265. {
  266. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  267. u32 reg, div;
  268. div = get_periph_clk() / val - 1;
  269. reg = readl(&mxc_ccm->cbcdr);
  270. writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
  271. (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
  272. }
  273. static void clear_mmdc_ch_mask(void)
  274. {
  275. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  276. u32 reg;
  277. reg = readl(&mxc_ccm->ccdr);
  278. /* Clear MMDC channel mask */
  279. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
  280. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
  281. else
  282. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
  283. writel(reg, &mxc_ccm->ccdr);
  284. }
  285. #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
  286. static void init_bandgap(void)
  287. {
  288. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  289. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  290. struct fuse_bank *bank = &ocotp->bank[1];
  291. struct fuse_bank1_regs *fuse =
  292. (struct fuse_bank1_regs *)bank->fuse_regs;
  293. uint32_t val;
  294. /*
  295. * Ensure the bandgap has stabilized.
  296. */
  297. while (!(readl(&anatop->ana_misc0) & 0x80))
  298. ;
  299. /*
  300. * For best noise performance of the analog blocks using the
  301. * outputs of the bandgap, the reftop_selfbiasoff bit should
  302. * be set.
  303. */
  304. writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
  305. /*
  306. * On i.MX6ULL,we need to set VBGADJ bits according to the
  307. * REFTOP_TRIM[3:0] in fuse table
  308. * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  309. * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  310. * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  311. * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  312. * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  313. * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  314. * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  315. * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
  316. */
  317. if (is_mx6ull()) {
  318. val = readl(&fuse->mem0);
  319. val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  320. val &= 0x7;
  321. writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  322. &anatop->ana_misc0_set);
  323. }
  324. }
  325. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  326. static void noc_setup(void)
  327. {
  328. enable_ipu_clock();
  329. writel(0x80000201, 0xbb0608);
  330. /* Bypass IPU1 QoS generator */
  331. writel(0x00000002, 0x00bb048c);
  332. /* Bypass IPU2 QoS generator */
  333. writel(0x00000002, 0x00bb050c);
  334. /* Bandwidth THR for of PRE0 */
  335. writel(0x00000200, 0x00bb0690);
  336. /* Bandwidth THR for of PRE1 */
  337. writel(0x00000200, 0x00bb0710);
  338. /* Bandwidth THR for of PRE2 */
  339. writel(0x00000200, 0x00bb0790);
  340. /* Bandwidth THR for of PRE3 */
  341. writel(0x00000200, 0x00bb0810);
  342. /* Saturation THR for of PRE0 */
  343. writel(0x00000010, 0x00bb0694);
  344. /* Saturation THR for of PRE1 */
  345. writel(0x00000010, 0x00bb0714);
  346. /* Saturation THR for of PRE2 */
  347. writel(0x00000010, 0x00bb0794);
  348. /* Saturation THR for of PRE */
  349. writel(0x00000010, 0x00bb0814);
  350. disable_ipu_clock();
  351. }
  352. #endif
  353. int arch_cpu_init(void)
  354. {
  355. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  356. init_aips();
  357. /* Need to clear MMDC_CHx_MASK to make warm reset work. */
  358. clear_mmdc_ch_mask();
  359. /*
  360. * Disable self-bias circuit in the analog bandap.
  361. * The self-bias circuit is used by the bandgap during startup.
  362. * This bit should be set after the bandgap has initialized.
  363. */
  364. init_bandgap();
  365. if (!is_mx6ul() && !is_mx6ull()) {
  366. /*
  367. * When low freq boot is enabled, ROM will not set AHB
  368. * freq, so we need to ensure AHB freq is 132MHz in such
  369. * scenario.
  370. *
  371. * To i.MX6UL, when power up, default ARM core and
  372. * AHB rate is 396M and 132M.
  373. */
  374. if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
  375. set_ahb_rate(132000000);
  376. }
  377. if (is_mx6ul()) {
  378. if (is_soc_rev(CHIP_REV_1_0) == 0) {
  379. /*
  380. * According to the design team's requirement on
  381. * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
  382. * as open drain 100K (0x0000b8a0).
  383. * Only exists on TO1.0
  384. */
  385. writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  386. } else {
  387. /*
  388. * From TO1.1, SNVS adds internal pull up control
  389. * for POR_B, the register filed is GPBIT[1:0],
  390. * after system boot up, it can be set to 2b'01
  391. * to disable internal pull up.It can save about
  392. * 30uA power in SNVS mode.
  393. */
  394. writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
  395. (~0x1400)) | 0x400,
  396. MX6UL_SNVS_LP_BASE_ADDR + 0x10);
  397. }
  398. }
  399. if (is_mx6ull()) {
  400. /*
  401. * GPBIT[1:0] is suggested to set to 2'b11:
  402. * 2'b00 : always PUP100K
  403. * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
  404. * 2'b10 : always disable PUP100K
  405. * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
  406. * register offset is different from i.MX6UL, since
  407. * i.MX6UL is fixed by ECO.
  408. */
  409. writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
  410. 0x3, MX6UL_SNVS_LP_BASE_ADDR);
  411. }
  412. /* Set perclk to source from OSC 24MHz */
  413. if (is_mx6sl())
  414. setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
  415. imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
  416. if (is_mx6sx())
  417. setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
  418. init_src();
  419. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  420. if (is_mx6dqp())
  421. noc_setup();
  422. #endif
  423. return 0;
  424. }
  425. #ifdef CONFIG_ENV_IS_IN_MMC
  426. __weak int board_mmc_get_env_dev(int devno)
  427. {
  428. return CONFIG_SYS_MMC_ENV_DEV;
  429. }
  430. static int mmc_get_boot_dev(void)
  431. {
  432. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  433. u32 soc_sbmr = readl(&src_regs->sbmr1);
  434. u32 bootsel;
  435. int devno;
  436. /*
  437. * Refer to
  438. * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
  439. * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
  440. * i.MX6SL/SX/UL has same layout.
  441. */
  442. bootsel = (soc_sbmr & 0x000000FF) >> 6;
  443. /* No boot from sd/mmc */
  444. if (bootsel != 1)
  445. return -1;
  446. /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  447. devno = (soc_sbmr & 0x00001800) >> 11;
  448. return devno;
  449. }
  450. int mmc_get_env_dev(void)
  451. {
  452. int devno = mmc_get_boot_dev();
  453. /* If not boot from sd/mmc, use default value */
  454. if (devno < 0)
  455. return CONFIG_SYS_MMC_ENV_DEV;
  456. return board_mmc_get_env_dev(devno);
  457. }
  458. #ifdef CONFIG_SYS_MMC_ENV_PART
  459. __weak int board_mmc_get_env_part(int devno)
  460. {
  461. return CONFIG_SYS_MMC_ENV_PART;
  462. }
  463. uint mmc_get_env_part(struct mmc *mmc)
  464. {
  465. int devno = mmc_get_boot_dev();
  466. /* If not boot from sd/mmc, use default value */
  467. if (devno < 0)
  468. return CONFIG_SYS_MMC_ENV_PART;
  469. return board_mmc_get_env_part(devno);
  470. }
  471. #endif
  472. #endif
  473. int board_postclk_init(void)
  474. {
  475. /* NO LDO SOC on i.MX6SLL */
  476. if (is_mx6sll())
  477. return 0;
  478. set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
  479. return 0;
  480. }
  481. #ifndef CONFIG_SPL_BUILD
  482. /*
  483. * cfg_val will be used for
  484. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  485. * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
  486. * instead of SBMR1 to determine the boot device.
  487. */
  488. const struct boot_mode soc_boot_modes[] = {
  489. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  490. /* reserved value should start rom usb */
  491. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  492. {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  493. #else
  494. {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  495. #endif
  496. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  497. {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  498. {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  499. {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  500. {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  501. /* 4 bit bus width */
  502. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  503. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  504. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  505. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  506. {NULL, 0},
  507. };
  508. #endif
  509. void reset_misc(void)
  510. {
  511. #ifndef CONFIG_SPL_BUILD
  512. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  513. lcdif_power_down();
  514. #endif
  515. #endif
  516. }
  517. void s_init(void)
  518. {
  519. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  520. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  521. u32 mask480;
  522. u32 mask528;
  523. u32 reg, periph1, periph2;
  524. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
  525. return;
  526. /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
  527. * to make sure PFD is working right, otherwise, PFDs may
  528. * not output clock after reset, MX6DL and MX6SL have added 396M pfd
  529. * workaround in ROM code, as bus clock need it
  530. */
  531. mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
  532. ANATOP_PFD_CLKGATE_MASK(1) |
  533. ANATOP_PFD_CLKGATE_MASK(2) |
  534. ANATOP_PFD_CLKGATE_MASK(3);
  535. mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
  536. ANATOP_PFD_CLKGATE_MASK(3);
  537. reg = readl(&ccm->cbcmr);
  538. periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
  539. >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
  540. periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
  541. >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
  542. /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
  543. if ((periph2 != 0x2) && (periph1 != 0x2))
  544. mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
  545. if ((periph2 != 0x1) && (periph1 != 0x1) &&
  546. (periph2 != 0x3) && (periph1 != 0x3))
  547. mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
  548. writel(mask480, &anatop->pfd_480_set);
  549. writel(mask528, &anatop->pfd_528_set);
  550. writel(mask480, &anatop->pfd_480_clr);
  551. writel(mask528, &anatop->pfd_528_clr);
  552. }
  553. #ifdef CONFIG_IMX_HDMI
  554. void imx_enable_hdmi_phy(void)
  555. {
  556. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  557. u8 reg;
  558. reg = readb(&hdmi->phy_conf0);
  559. reg |= HDMI_PHY_CONF0_PDZ_MASK;
  560. writeb(reg, &hdmi->phy_conf0);
  561. udelay(3000);
  562. reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
  563. writeb(reg, &hdmi->phy_conf0);
  564. udelay(3000);
  565. reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
  566. writeb(reg, &hdmi->phy_conf0);
  567. writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
  568. }
  569. void imx_setup_hdmi(void)
  570. {
  571. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  572. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  573. int reg, count;
  574. u8 val;
  575. /* Turn on HDMI PHY clock */
  576. reg = readl(&mxc_ccm->CCGR2);
  577. reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
  578. MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
  579. writel(reg, &mxc_ccm->CCGR2);
  580. writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
  581. reg = readl(&mxc_ccm->chsccdr);
  582. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
  583. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
  584. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  585. reg |= (CHSCCDR_PODF_DIVIDE_BY_3
  586. << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  587. |(CHSCCDR_IPU_PRE_CLK_540M_PFD
  588. << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  589. writel(reg, &mxc_ccm->chsccdr);
  590. /* Clear the overflow condition */
  591. if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
  592. /* TMDS software reset */
  593. writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
  594. val = readb(&hdmi->fc_invidconf);
  595. /* Need minimum 3 times to write to clear the register */
  596. for (count = 0 ; count < 5 ; count++)
  597. writeb(val, &hdmi->fc_invidconf);
  598. }
  599. }
  600. #endif
  601. /*
  602. * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
  603. * MX6Q and MX6QP processors
  604. */
  605. void gpr_init(void)
  606. {
  607. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  608. /*
  609. * If this function is used in a common MX6 spl implementation
  610. * we have to ensure that it is only called for suitable cpu types,
  611. * otherwise it breaks hardware parts like enet1, can1, can2, etc.
  612. */
  613. if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
  614. return;
  615. /* enable AXI cache for VDOA/VPU/IPU */
  616. writel(0xF00000CF, &iomux->gpr[4]);
  617. if (is_mx6dqp()) {
  618. /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
  619. writel(0x77177717, &iomux->gpr[6]);
  620. writel(0x77177717, &iomux->gpr[7]);
  621. } else {
  622. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  623. writel(0x007F007F, &iomux->gpr[6]);
  624. writel(0x007F007F, &iomux->gpr[7]);
  625. }
  626. }