ddr.c 50 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <log.h>
  9. #include <linux/delay.h>
  10. #include <linux/types.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/io.h>
  15. #include <asm/types.h>
  16. #include <wait_bit.h>
  17. #if defined(CONFIG_MX6_DDRCAL)
  18. static void reset_read_data_fifos(void)
  19. {
  20. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  21. /* Reset data FIFOs twice. */
  22. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  23. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  24. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  25. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  26. }
  27. static void precharge_all(const bool cs0_enable, const bool cs1_enable)
  28. {
  29. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  30. /*
  31. * Issue the Precharge-All command to the DDR device for both
  32. * chip selects. Note, CON_REQ bit should also remain set. If
  33. * only using one chip select, then precharge only the desired
  34. * chip select.
  35. */
  36. if (cs0_enable) { /* CS0 */
  37. writel(0x04008050, &mmdc0->mdscr);
  38. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  39. }
  40. if (cs1_enable) { /* CS1 */
  41. writel(0x04008058, &mmdc0->mdscr);
  42. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  43. }
  44. }
  45. static void force_delay_measurement(int bus_size)
  46. {
  47. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  48. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  49. writel(0x800, &mmdc0->mpmur0);
  50. if (bus_size == 0x2)
  51. writel(0x800, &mmdc1->mpmur0);
  52. }
  53. static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
  54. {
  55. u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
  56. /*
  57. * DQS gating absolute offset should be modified from reflecting
  58. * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
  59. */
  60. val_ctrl = readl(reg_ctrl);
  61. val_ctrl &= 0xf0000000;
  62. dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
  63. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  64. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  65. val_ctrl |= dg_dl_abs_offset + dg_hc_del;
  66. dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
  67. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  68. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  69. val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
  70. writel(val_ctrl, reg_ctrl);
  71. }
  72. static void correct_mpwldectr_result(void *reg)
  73. {
  74. /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
  75. const unsigned int limit = 0x148;
  76. u32 val = readl(reg);
  77. u32 old = val;
  78. if ((val & 0x17f) > limit)
  79. val &= 0xffff << 16;
  80. if (((val >> 16) & 0x17f) > limit)
  81. val &= 0xffff;
  82. if (old != val)
  83. writel(val, reg);
  84. }
  85. int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  86. {
  87. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  88. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  89. u32 esdmisc_val, zq_val;
  90. u32 errors = 0;
  91. u32 ldectrl[4] = {0};
  92. u32 ddr_mr1 = 0x4;
  93. u32 rwalat_max;
  94. /*
  95. * Stash old values in case calibration fails,
  96. * we need to restore them
  97. */
  98. ldectrl[0] = readl(&mmdc0->mpwldectrl0);
  99. ldectrl[1] = readl(&mmdc0->mpwldectrl1);
  100. if (sysinfo->dsize == 2) {
  101. ldectrl[2] = readl(&mmdc1->mpwldectrl0);
  102. ldectrl[3] = readl(&mmdc1->mpwldectrl1);
  103. }
  104. /* disable DDR logic power down timer */
  105. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  106. /* disable Adopt power down timer */
  107. setbits_le32(&mmdc0->mapsr, 0x1);
  108. debug("Starting write leveling calibration.\n");
  109. /*
  110. * 2. disable auto refresh and ZQ calibration
  111. * before proceeding with Write Leveling calibration
  112. */
  113. esdmisc_val = readl(&mmdc0->mdref);
  114. writel(0x0000C000, &mmdc0->mdref);
  115. zq_val = readl(&mmdc0->mpzqhwctrl);
  116. writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
  117. /* 3. increase walat and ralat to maximum */
  118. rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
  119. setbits_le32(&mmdc0->mdmisc, rwalat_max);
  120. if (sysinfo->dsize == 2)
  121. setbits_le32(&mmdc1->mdmisc, rwalat_max);
  122. /*
  123. * 4 & 5. Configure the external DDR device to enter write-leveling
  124. * mode through Load Mode Register command.
  125. * Register setting:
  126. * Bits[31:16] MR1 value (0x0080 write leveling enable)
  127. * Bit[9] set WL_EN to enable MMDC DQS output
  128. * Bits[6:4] set CMD bits for Load Mode Register programming
  129. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  130. */
  131. writel(0x00808231, &mmdc0->mdscr);
  132. /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
  133. writel(0x00000001, &mmdc0->mpwlgcr);
  134. /*
  135. * 7. Upon completion of this process the MMDC de-asserts
  136. * the MPWLGCR[HW_WL_EN]
  137. */
  138. wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
  139. /*
  140. * 8. check for any errors: check both PHYs for x64 configuration,
  141. * if x32, check only PHY0
  142. */
  143. if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
  144. errors |= 1;
  145. if (sysinfo->dsize == 2)
  146. if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
  147. errors |= 2;
  148. debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
  149. /* check to see if cal failed */
  150. if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
  151. (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
  152. ((sysinfo->dsize < 2) ||
  153. ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
  154. (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
  155. debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
  156. writel(ldectrl[0], &mmdc0->mpwldectrl0);
  157. writel(ldectrl[1], &mmdc0->mpwldectrl1);
  158. if (sysinfo->dsize == 2) {
  159. writel(ldectrl[2], &mmdc1->mpwldectrl0);
  160. writel(ldectrl[3], &mmdc1->mpwldectrl1);
  161. }
  162. errors |= 4;
  163. }
  164. correct_mpwldectr_result(&mmdc0->mpwldectrl0);
  165. correct_mpwldectr_result(&mmdc0->mpwldectrl1);
  166. if (sysinfo->dsize == 2) {
  167. correct_mpwldectr_result(&mmdc1->mpwldectrl0);
  168. correct_mpwldectr_result(&mmdc1->mpwldectrl1);
  169. }
  170. /*
  171. * User should issue MRS command to exit write leveling mode
  172. * through Load Mode Register command
  173. * Register setting:
  174. * Bits[31:16] MR1 value "ddr_mr1" value from initialization
  175. * Bit[9] clear WL_EN to disable MMDC DQS output
  176. * Bits[6:4] set CMD bits for Load Mode Register programming
  177. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  178. */
  179. writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
  180. /* re-enable auto refresh and zq cal */
  181. writel(esdmisc_val, &mmdc0->mdref);
  182. writel(zq_val, &mmdc0->mpzqhwctrl);
  183. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  184. readl(&mmdc0->mpwldectrl0));
  185. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  186. readl(&mmdc0->mpwldectrl1));
  187. if (sysinfo->dsize == 2) {
  188. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  189. readl(&mmdc1->mpwldectrl0));
  190. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  191. readl(&mmdc1->mpwldectrl1));
  192. }
  193. /* We must force a readback of these values, to get them to stick */
  194. readl(&mmdc0->mpwldectrl0);
  195. readl(&mmdc0->mpwldectrl1);
  196. if (sysinfo->dsize == 2) {
  197. readl(&mmdc1->mpwldectrl0);
  198. readl(&mmdc1->mpwldectrl1);
  199. }
  200. /* enable DDR logic power down timer: */
  201. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  202. /* Enable Adopt power down timer: */
  203. clrbits_le32(&mmdc0->mapsr, 0x1);
  204. /* Clear CON_REQ */
  205. writel(0, &mmdc0->mdscr);
  206. return errors;
  207. }
  208. static void mmdc_set_sdqs(bool set)
  209. {
  210. struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
  211. (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  212. struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
  213. (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  214. int i, sdqs_cnt;
  215. u32 sdqs;
  216. if (is_mx6sx()) {
  217. sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
  218. sdqs_cnt = 2;
  219. } else { /* MX6DQ */
  220. sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
  221. sdqs_cnt = 8;
  222. }
  223. for (i = 0; i < sdqs_cnt; i++) {
  224. if (set)
  225. setbits_le32(sdqs + (4 * i), 0x7000);
  226. else
  227. clrbits_le32(sdqs + (4 * i), 0x7000);
  228. }
  229. }
  230. int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  231. {
  232. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  233. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  234. bool cs0_enable;
  235. bool cs1_enable;
  236. bool cs0_enable_initial;
  237. bool cs1_enable_initial;
  238. u32 esdmisc_val;
  239. u32 temp_ref;
  240. u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
  241. u32 errors = 0;
  242. u32 initdelay = 0x40404040;
  243. /* check to see which chip selects are enabled */
  244. cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
  245. cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
  246. /* disable DDR logic power down timer: */
  247. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  248. /* disable Adopt power down timer: */
  249. setbits_le32(&mmdc0->mapsr, 0x1);
  250. /* set DQS pull ups */
  251. mmdc_set_sdqs(true);
  252. /* Save old RALAT and WALAT values */
  253. esdmisc_val = readl(&mmdc0->mdmisc);
  254. setbits_le32(&mmdc0->mdmisc,
  255. (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
  256. /* Disable auto refresh before proceeding with calibration */
  257. temp_ref = readl(&mmdc0->mdref);
  258. writel(0x0000c000, &mmdc0->mdref);
  259. /*
  260. * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
  261. * this also sets the CON_REQ bit.
  262. */
  263. if (cs0_enable_initial)
  264. writel(0x00008020, &mmdc0->mdscr);
  265. if (cs1_enable_initial)
  266. writel(0x00008028, &mmdc0->mdscr);
  267. /* poll to make sure the con_ack bit was asserted */
  268. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  269. /*
  270. * Check MDMISC register CALIB_PER_CS to see which CS calibration
  271. * is targeted to (under normal cases, it should be cleared
  272. * as this is the default value, indicating calibration is directed
  273. * to CS0).
  274. * Disable the other chip select not being target for calibration
  275. * to avoid any potential issues. This will get re-enabled at end
  276. * of calibration.
  277. */
  278. if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
  279. clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
  280. else
  281. clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
  282. /*
  283. * Check to see which chip selects are now enabled for
  284. * the remainder of the calibration.
  285. */
  286. cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
  287. cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
  288. precharge_all(cs0_enable, cs1_enable);
  289. /* Write the pre-defined value into MPPDCMPR1 */
  290. writel(pddword, &mmdc0->mppdcmpr1);
  291. /*
  292. * Issue a write access to the external DDR device by setting
  293. * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
  294. * this bit until it clears to indicate completion of the write access.
  295. */
  296. setbits_le32(&mmdc0->mpswdar0, 1);
  297. wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
  298. /* Set the RD_DL_ABS# bits to their default values
  299. * (will be calibrated later in the read delay-line calibration).
  300. * Both PHYs for x64 configuration, if x32, do only PHY0.
  301. */
  302. writel(initdelay, &mmdc0->mprddlctl);
  303. if (sysinfo->dsize == 0x2)
  304. writel(initdelay, &mmdc1->mprddlctl);
  305. /* Force a measurment, for previous delay setup to take effect. */
  306. force_delay_measurement(sysinfo->dsize);
  307. /*
  308. * ***************************
  309. * Read DQS Gating calibration
  310. * ***************************
  311. */
  312. debug("Starting Read DQS Gating calibration.\n");
  313. /*
  314. * Reset the read data FIFOs (two resets); only need to issue reset
  315. * to PHY0 since in x64 mode, the reset will also go to PHY1.
  316. */
  317. reset_read_data_fifos();
  318. /*
  319. * Start the automatic read DQS gating calibration process by
  320. * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
  321. * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
  322. * to indicate completion.
  323. * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
  324. * no errors were seen during calibration.
  325. */
  326. /*
  327. * Set bit 30: chooses option to wait 32 cycles instead of
  328. * 16 before comparing read data.
  329. */
  330. setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  331. if (sysinfo->dsize == 2)
  332. setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  333. /* Set bit 28 to start automatic read DQS gating calibration */
  334. setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
  335. /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
  336. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
  337. /*
  338. * Check to see if any errors were encountered during calibration
  339. * (check MPDGCTRL0[HW_DG_ERR]).
  340. * Check both PHYs for x64 configuration, if x32, check only PHY0.
  341. */
  342. if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
  343. errors |= 1;
  344. if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
  345. errors |= 2;
  346. /* now disable mpdgctrl0[DG_CMP_CYC] */
  347. clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  348. if (sysinfo->dsize == 2)
  349. clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  350. /*
  351. * DQS gating absolute offset should be modified from
  352. * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
  353. * reflecting (HW_DG_UPx - 0x80)
  354. */
  355. modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
  356. &mmdc0->mpdgctrl0);
  357. modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
  358. &mmdc0->mpdgctrl1);
  359. if (sysinfo->dsize == 0x2) {
  360. modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
  361. &mmdc1->mpdgctrl0);
  362. modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
  363. &mmdc1->mpdgctrl1);
  364. }
  365. debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
  366. /*
  367. * **********************
  368. * Read Delay calibration
  369. * **********************
  370. */
  371. debug("Starting Read Delay calibration.\n");
  372. reset_read_data_fifos();
  373. /*
  374. * 4. Issue the Precharge-All command to the DDR device for both
  375. * chip selects. If only using one chip select, then precharge
  376. * only the desired chip select.
  377. */
  378. precharge_all(cs0_enable, cs1_enable);
  379. /*
  380. * 9. Read delay-line calibration
  381. * Start the automatic read calibration process by asserting
  382. * MPRDDLHWCTL[HW_RD_DL_EN].
  383. */
  384. writel(0x00000030, &mmdc0->mprddlhwctl);
  385. /*
  386. * 10. poll for completion
  387. * MMDC indicates that the write data calibration had finished by
  388. * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
  389. * no error bits were set.
  390. */
  391. wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
  392. /* check both PHYs for x64 configuration, if x32, check only PHY0 */
  393. if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
  394. errors |= 4;
  395. if ((sysinfo->dsize == 0x2) &&
  396. (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
  397. errors |= 8;
  398. debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
  399. /*
  400. * ***********************
  401. * Write Delay Calibration
  402. * ***********************
  403. */
  404. debug("Starting Write Delay calibration.\n");
  405. reset_read_data_fifos();
  406. /*
  407. * 4. Issue the Precharge-All command to the DDR device for both
  408. * chip selects. If only using one chip select, then precharge
  409. * only the desired chip select.
  410. */
  411. precharge_all(cs0_enable, cs1_enable);
  412. /*
  413. * 8. Set the WR_DL_ABS# bits to their default values.
  414. * Both PHYs for x64 configuration, if x32, do only PHY0.
  415. */
  416. writel(initdelay, &mmdc0->mpwrdlctl);
  417. if (sysinfo->dsize == 0x2)
  418. writel(initdelay, &mmdc1->mpwrdlctl);
  419. /*
  420. * XXX This isn't in the manual. Force a measurement,
  421. * for previous delay setup to effect.
  422. */
  423. force_delay_measurement(sysinfo->dsize);
  424. /*
  425. * 9. 10. Start the automatic write calibration process
  426. * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
  427. */
  428. writel(0x00000030, &mmdc0->mpwrdlhwctl);
  429. /*
  430. * Poll for completion.
  431. * MMDC indicates that the write data calibration had finished
  432. * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
  433. * Also, ensure that no error bits were set.
  434. */
  435. wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
  436. /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
  437. if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
  438. errors |= 16;
  439. if ((sysinfo->dsize == 0x2) &&
  440. (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
  441. errors |= 32;
  442. debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
  443. reset_read_data_fifos();
  444. /* Enable DDR logic power down timer */
  445. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  446. /* Enable Adopt power down timer */
  447. clrbits_le32(&mmdc0->mapsr, 0x1);
  448. /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
  449. writel(esdmisc_val, &mmdc0->mdmisc);
  450. /* Clear DQS pull ups */
  451. mmdc_set_sdqs(false);
  452. /* Re-enable SDE (chip selects) if they were set initially */
  453. if (cs1_enable_initial)
  454. /* Set SDE_1 */
  455. setbits_le32(&mmdc0->mdctl, 1 << 30);
  456. if (cs0_enable_initial)
  457. /* Set SDE_0 */
  458. setbits_le32(&mmdc0->mdctl, 1 << 31);
  459. /* Re-enable to auto refresh */
  460. writel(temp_ref, &mmdc0->mdref);
  461. /* Clear the MDSCR (including the con_req bit) */
  462. writel(0x0, &mmdc0->mdscr); /* CS0 */
  463. /* Poll to make sure the con_ack bit is clear */
  464. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
  465. /*
  466. * Print out the registers that were updated as a result
  467. * of the calibration process.
  468. */
  469. debug("MMDC registers updated from calibration\n");
  470. debug("Read DQS gating calibration:\n");
  471. debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
  472. debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
  473. if (sysinfo->dsize == 2) {
  474. debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
  475. debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
  476. }
  477. debug("Read calibration:\n");
  478. debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
  479. if (sysinfo->dsize == 2)
  480. debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
  481. debug("Write calibration:\n");
  482. debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
  483. if (sysinfo->dsize == 2)
  484. debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
  485. /*
  486. * Registers below are for debugging purposes. These print out
  487. * the upper and lower boundaries captured during
  488. * read DQS gating calibration.
  489. */
  490. debug("Status registers bounds for read DQS gating:\n");
  491. debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
  492. debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
  493. debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
  494. debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
  495. if (sysinfo->dsize == 2) {
  496. debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
  497. debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
  498. debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
  499. debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
  500. }
  501. debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
  502. return errors;
  503. }
  504. #endif
  505. #if defined(CONFIG_MX6SX)
  506. /* Configure MX6SX mmdc iomux */
  507. void mx6sx_dram_iocfg(unsigned width,
  508. const struct mx6sx_iomux_ddr_regs *ddr,
  509. const struct mx6sx_iomux_grp_regs *grp)
  510. {
  511. struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  512. struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  513. mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  514. mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  515. /* DDR IO TYPE */
  516. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  517. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  518. /* CLOCK */
  519. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  520. /* ADDRESS */
  521. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  522. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  523. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  524. /* Control */
  525. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  526. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  527. writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  528. writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  529. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  530. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  531. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  532. /* Data Strobes */
  533. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  534. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  535. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  536. if (width >= 32) {
  537. writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  538. writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  539. }
  540. /* Data */
  541. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  542. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  543. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  544. if (width >= 32) {
  545. writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  546. writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  547. }
  548. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  549. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  550. if (width >= 32) {
  551. writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  552. writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  553. }
  554. }
  555. #endif
  556. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  557. void mx6ul_dram_iocfg(unsigned width,
  558. const struct mx6ul_iomux_ddr_regs *ddr,
  559. const struct mx6ul_iomux_grp_regs *grp)
  560. {
  561. struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
  562. struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
  563. mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  564. mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
  565. /* DDR IO TYPE */
  566. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  567. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  568. /* CLOCK */
  569. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  570. /* ADDRESS */
  571. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  572. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  573. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  574. /* Control */
  575. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  576. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  577. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  578. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  579. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  580. /* Data Strobes */
  581. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  582. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  583. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  584. /* Data */
  585. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  586. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  587. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  588. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  589. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  590. }
  591. #endif
  592. #if defined(CONFIG_MX6SL)
  593. void mx6sl_dram_iocfg(unsigned width,
  594. const struct mx6sl_iomux_ddr_regs *ddr,
  595. const struct mx6sl_iomux_grp_regs *grp)
  596. {
  597. struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
  598. struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
  599. mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
  600. mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
  601. /* DDR IO TYPE */
  602. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  603. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  604. /* CLOCK */
  605. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  606. /* ADDRESS */
  607. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  608. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  609. mx6_grp_iomux->grp_addds = grp->grp_addds;
  610. /* Control */
  611. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  612. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  613. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  614. /* Data Strobes */
  615. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  616. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  617. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  618. if (width >= 32) {
  619. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  620. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  621. }
  622. /* Data */
  623. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  624. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  625. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  626. if (width >= 32) {
  627. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  628. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  629. }
  630. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  631. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  632. if (width >= 32) {
  633. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  634. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  635. }
  636. }
  637. #endif
  638. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
  639. /* Configure MX6DQ mmdc iomux */
  640. void mx6dq_dram_iocfg(unsigned width,
  641. const struct mx6dq_iomux_ddr_regs *ddr,
  642. const struct mx6dq_iomux_grp_regs *grp)
  643. {
  644. volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
  645. volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
  646. mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  647. mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
  648. /* DDR IO Type */
  649. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  650. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  651. /* Clock */
  652. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  653. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  654. /* Address */
  655. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  656. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  657. mx6_grp_iomux->grp_addds = grp->grp_addds;
  658. /* Control */
  659. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  660. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  661. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  662. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  663. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  664. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  665. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  666. /* Data Strobes */
  667. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  668. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  669. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  670. if (width >= 32) {
  671. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  672. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  673. }
  674. if (width >= 64) {
  675. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  676. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  677. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  678. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  679. }
  680. /* Data */
  681. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  682. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  683. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  684. if (width >= 32) {
  685. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  686. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  687. }
  688. if (width >= 64) {
  689. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  690. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  691. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  692. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  693. }
  694. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  695. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  696. if (width >= 32) {
  697. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  698. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  699. }
  700. if (width >= 64) {
  701. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  702. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  703. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  704. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  705. }
  706. }
  707. #endif
  708. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  709. /* Configure MX6SDL mmdc iomux */
  710. void mx6sdl_dram_iocfg(unsigned width,
  711. const struct mx6sdl_iomux_ddr_regs *ddr,
  712. const struct mx6sdl_iomux_grp_regs *grp)
  713. {
  714. volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
  715. volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
  716. mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  717. mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
  718. /* DDR IO Type */
  719. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  720. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  721. /* Clock */
  722. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  723. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  724. /* Address */
  725. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  726. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  727. mx6_grp_iomux->grp_addds = grp->grp_addds;
  728. /* Control */
  729. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  730. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  731. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  732. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  733. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  734. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  735. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  736. /* Data Strobes */
  737. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  738. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  739. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  740. if (width >= 32) {
  741. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  742. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  743. }
  744. if (width >= 64) {
  745. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  746. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  747. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  748. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  749. }
  750. /* Data */
  751. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  752. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  753. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  754. if (width >= 32) {
  755. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  756. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  757. }
  758. if (width >= 64) {
  759. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  760. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  761. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  762. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  763. }
  764. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  765. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  766. if (width >= 32) {
  767. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  768. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  769. }
  770. if (width >= 64) {
  771. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  772. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  773. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  774. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  775. }
  776. }
  777. #endif
  778. /*
  779. * Configure mx6 mmdc registers based on:
  780. * - board-specific memory configuration
  781. * - board-specific calibration data
  782. * - ddr3/lpddr2 chip details
  783. *
  784. * The various calculations here are derived from the Freescale
  785. * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
  786. * MMDC configuration registers based on memory system and memory chip
  787. * parameters.
  788. *
  789. * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
  790. * configuration registers based on memory system and memory chip
  791. * parameters.
  792. *
  793. * The defaults here are those which were specified in the spreadsheet.
  794. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
  795. * and/or IMX6SLRM section titled MMDC initialization.
  796. */
  797. #define MR(val, ba, cmd, cs1) \
  798. ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
  799. #define MMDC1(entry, value) do { \
  800. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
  801. mmdc1->entry = value; \
  802. } while (0)
  803. /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
  804. #define BOOT_CFG3_DDR_MASK 0x30
  805. #define BOOT_CFG3_EXT_DDR_MASK 0x33
  806. #define DDR_MMAP_NOC_SINGLE 0
  807. #define DDR_MMAP_NOC_DUAL 0x31
  808. /* NoC ACTIVATE shifts */
  809. #define NOC_RD_SHIFT 0
  810. #define NOC_FAW_PERIOD_SHIFT 4
  811. #define NOC_FAW_BANKS_SHIFT 10
  812. /* NoC DdrTiming shifts */
  813. #define NOC_ACT_TO_ACT_SHIFT 0
  814. #define NOC_RD_TO_MISS_SHIFT 6
  815. #define NOC_WR_TO_MISS_SHIFT 12
  816. #define NOC_BURST_LEN_SHIFT 18
  817. #define NOC_RD_TO_WR_SHIFT 21
  818. #define NOC_WR_TO_RD_SHIFT 26
  819. #define NOC_BW_RATIO_SHIFT 31
  820. /*
  821. * According JESD209-2B-LPDDR2: Table 103
  822. * WL: write latency
  823. */
  824. static int lpddr2_wl(uint32_t mem_speed)
  825. {
  826. switch (mem_speed) {
  827. case 1066:
  828. case 933:
  829. return 4;
  830. case 800:
  831. return 3;
  832. case 677:
  833. case 533:
  834. return 2;
  835. case 400:
  836. case 333:
  837. return 1;
  838. default:
  839. puts("invalid memory speed\n");
  840. hang();
  841. }
  842. return 0;
  843. }
  844. /*
  845. * According JESD209-2B-LPDDR2: Table 103
  846. * RL: read latency
  847. */
  848. static int lpddr2_rl(uint32_t mem_speed)
  849. {
  850. switch (mem_speed) {
  851. case 1066:
  852. return 8;
  853. case 933:
  854. return 7;
  855. case 800:
  856. return 6;
  857. case 677:
  858. return 5;
  859. case 533:
  860. return 4;
  861. case 400:
  862. case 333:
  863. return 3;
  864. default:
  865. puts("invalid memory speed\n");
  866. hang();
  867. }
  868. return 0;
  869. }
  870. void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  871. const struct mx6_mmdc_calibration *calib,
  872. const struct mx6_lpddr2_cfg *lpddr2_cfg)
  873. {
  874. volatile struct mmdc_p_regs *mmdc0;
  875. u32 val;
  876. u8 tcke, tcksrx, tcksre, trrd;
  877. u8 twl, txp, tfaw, tcl;
  878. u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
  879. u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
  880. u16 cs0_end;
  881. u8 coladdr;
  882. int clkper; /* clock period in picoseconds */
  883. int clock; /* clock freq in mHz */
  884. int cs;
  885. /* only support 16/32 bits */
  886. if (sysinfo->dsize > 1)
  887. hang();
  888. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  889. clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
  890. clkper = (1000 * 1000) / clock; /* pico seconds */
  891. twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
  892. /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
  893. switch (lpddr2_cfg->density) {
  894. case 1:
  895. case 2:
  896. case 4:
  897. trfc = DIV_ROUND_UP(130000, clkper) - 1;
  898. txsr = DIV_ROUND_UP(140000, clkper) - 1;
  899. break;
  900. case 8:
  901. trfc = DIV_ROUND_UP(210000, clkper) - 1;
  902. txsr = DIV_ROUND_UP(220000, clkper) - 1;
  903. break;
  904. default:
  905. /*
  906. * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
  907. */
  908. hang();
  909. break;
  910. }
  911. /*
  912. * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
  913. * set them to 0. */
  914. txp = DIV_ROUND_UP(7500, clkper) - 1;
  915. tcke = 3;
  916. if (lpddr2_cfg->mem_speed == 333)
  917. tfaw = DIV_ROUND_UP(60000, clkper) - 1;
  918. else
  919. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  920. trrd = DIV_ROUND_UP(10000, clkper) - 1;
  921. /* tckesr for LPDDR2 */
  922. tcksre = DIV_ROUND_UP(15000, clkper);
  923. tcksrx = tcksre;
  924. twr = DIV_ROUND_UP(15000, clkper) - 1;
  925. /*
  926. * tMRR: 2, tMRW: 5
  927. * tMRD should be set to max(tMRR, tMRW)
  928. */
  929. tmrd = 5;
  930. tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
  931. /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
  932. trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
  933. trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
  934. clkper / 10) - 1;
  935. trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
  936. trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
  937. /* To LPDDR2, CL in MDCFG0 refers to RL */
  938. tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
  939. twtr = DIV_ROUND_UP(7500, clkper) - 1;
  940. trtp = DIV_ROUND_UP(7500, clkper) - 1;
  941. cs0_end = 4 * sysinfo->cs_density - 1;
  942. debug("density:%d Gb (%d Gb per chip)\n",
  943. sysinfo->cs_density, lpddr2_cfg->density);
  944. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  945. debug("memspd:%d\n", lpddr2_cfg->mem_speed);
  946. debug("trcd_lp=%d\n", trcd_lp);
  947. debug("trppb_lp=%d\n", trppb_lp);
  948. debug("trpab_lp=%d\n", trpab_lp);
  949. debug("trc_lp=%d\n", trc_lp);
  950. debug("tcke=%d\n", tcke);
  951. debug("tcksrx=%d\n", tcksrx);
  952. debug("tcksre=%d\n", tcksre);
  953. debug("trfc=%d\n", trfc);
  954. debug("txsr=%d\n", txsr);
  955. debug("txp=%d\n", txp);
  956. debug("tfaw=%d\n", tfaw);
  957. debug("tcl=%d\n", tcl);
  958. debug("tras=%d\n", tras);
  959. debug("twr=%d\n", twr);
  960. debug("tmrd=%d\n", tmrd);
  961. debug("twl=%d\n", twl);
  962. debug("trtp=%d\n", trtp);
  963. debug("twtr=%d\n", twtr);
  964. debug("trrd=%d\n", trrd);
  965. debug("cs0_end=%d\n", cs0_end);
  966. debug("ncs=%d\n", sysinfo->ncs);
  967. /*
  968. * board-specific configuration:
  969. * These values are determined empirically and vary per board layout
  970. */
  971. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  972. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  973. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  974. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  975. mmdc0->mprddlctl = calib->p0_mprddlctl;
  976. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  977. mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
  978. /* Read data DQ Byte0-3 delay */
  979. mmdc0->mprddqby0dl = 0x33333333;
  980. mmdc0->mprddqby1dl = 0x33333333;
  981. if (sysinfo->dsize > 0) {
  982. mmdc0->mprddqby2dl = 0x33333333;
  983. mmdc0->mprddqby3dl = 0x33333333;
  984. }
  985. /* Write data DQ Byte0-3 delay */
  986. mmdc0->mpwrdqby0dl = 0xf3333333;
  987. mmdc0->mpwrdqby1dl = 0xf3333333;
  988. if (sysinfo->dsize > 0) {
  989. mmdc0->mpwrdqby2dl = 0xf3333333;
  990. mmdc0->mpwrdqby3dl = 0xf3333333;
  991. }
  992. /*
  993. * In LPDDR2 mode this register should be cleared,
  994. * so no termination will be activated.
  995. */
  996. mmdc0->mpodtctrl = 0;
  997. /* complete calibration */
  998. val = (1 << 11); /* Force measurement on delay-lines */
  999. mmdc0->mpmur0 = val;
  1000. /* Step 1: configuration request */
  1001. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1002. /* Step 2: Timing configuration */
  1003. mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
  1004. (tfaw << 4) | tcl;
  1005. mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
  1006. mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
  1007. mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
  1008. (trppb_lp << 4) | trpab_lp;
  1009. mmdc0->mdotc = 0;
  1010. mmdc0->mdasp = cs0_end; /* CS addressing */
  1011. /* Step 3: Configure DDR type */
  1012. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1013. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1014. (sysinfo->ralat << 6) | (1 << 3);
  1015. /* Step 4: Configure delay while leaving reset */
  1016. mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
  1017. (sysinfo->rst_to_cke << 0);
  1018. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1019. coladdr = lpddr2_cfg->coladdr;
  1020. if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1021. coladdr += 4;
  1022. else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1023. coladdr += 1;
  1024. mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
  1025. (coladdr - 9) << 20 | /* COL */
  1026. (0 << 19) | /* Burst Length = 4 for LPDDR2 */
  1027. (sysinfo->dsize << 16); /* DDR data bus size */
  1028. /* Step 6: Perform ZQ calibration */
  1029. val = 0xa1390003; /* one-time HW ZQ calib */
  1030. mmdc0->mpzqhwctrl = val;
  1031. /* Step 7: Enable MMDC with desired chip select */
  1032. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1033. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1034. /* Step 8: Write Mode Registers to Init LPDDR2 devices */
  1035. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1036. /* MR63: reset */
  1037. mmdc0->mdscr = MR(63, 0, 3, cs);
  1038. /* MR10: calibration,
  1039. * 0xff is calibration command after intilization.
  1040. */
  1041. val = 0xA | (0xff << 8);
  1042. mmdc0->mdscr = MR(val, 0, 3, cs);
  1043. /* MR1 */
  1044. val = 0x1 | (0x82 << 8);
  1045. mmdc0->mdscr = MR(val, 0, 3, cs);
  1046. /* MR2 */
  1047. val = 0x2 | (0x04 << 8);
  1048. mmdc0->mdscr = MR(val, 0, 3, cs);
  1049. /* MR3 */
  1050. val = 0x3 | (0x02 << 8);
  1051. mmdc0->mdscr = MR(val, 0, 3, cs);
  1052. }
  1053. /* Step 10: Power down control and self-refresh */
  1054. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1055. 5 << 12 | /* PWDT_1: 256 cycles */
  1056. 5 << 8 | /* PWDT_0: 256 cycles */
  1057. 1 << 6 | /* BOTH_CS_PD */
  1058. (tcksrx & 0x7) << 3 |
  1059. (tcksre & 0x7);
  1060. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1061. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1062. val = 0xa1310003;
  1063. mmdc0->mpzqhwctrl = val;
  1064. /* Step 12: Configure and activate periodic refresh */
  1065. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1066. /* Step 13: Deassert config request - init complete */
  1067. mmdc0->mdscr = 0x00000000;
  1068. /* wait for auto-ZQ calibration to complete */
  1069. mdelay(1);
  1070. }
  1071. void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1072. const struct mx6_mmdc_calibration *calib,
  1073. const struct mx6_ddr3_cfg *ddr3_cfg)
  1074. {
  1075. volatile struct mmdc_p_regs *mmdc0;
  1076. volatile struct mmdc_p_regs *mmdc1;
  1077. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  1078. u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
  1079. u32 val;
  1080. u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
  1081. u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
  1082. u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
  1083. u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
  1084. u16 cs0_end;
  1085. u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  1086. u8 coladdr;
  1087. int clkper; /* clock period in picoseconds */
  1088. int clock; /* clock freq in MHz */
  1089. int cs;
  1090. u16 mem_speed = ddr3_cfg->mem_speed;
  1091. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1092. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
  1093. mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1094. /* Limit mem_speed for MX6D/MX6Q */
  1095. if (is_mx6dq() || is_mx6dqp()) {
  1096. if (mem_speed > 1066)
  1097. mem_speed = 1066; /* 1066 MT/s */
  1098. tcwl = 4;
  1099. }
  1100. /* Limit mem_speed for MX6S/MX6DL */
  1101. else {
  1102. if (mem_speed > 800)
  1103. mem_speed = 800; /* 800 MT/s */
  1104. tcwl = 3;
  1105. }
  1106. clock = mem_speed / 2;
  1107. /*
  1108. * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
  1109. * up to 528 MHz, so reduce the clock to fit chip specs
  1110. */
  1111. if (is_mx6dq() || is_mx6dqp()) {
  1112. if (clock > 528)
  1113. clock = 528; /* 528 MHz */
  1114. }
  1115. clkper = (1000 * 1000) / clock; /* pico seconds */
  1116. todtlon = tcwl;
  1117. taxpd = tcwl;
  1118. tanpd = tcwl;
  1119. switch (ddr3_cfg->density) {
  1120. case 1: /* 1Gb per chip */
  1121. trfc = DIV_ROUND_UP(110000, clkper) - 1;
  1122. txs = DIV_ROUND_UP(120000, clkper) - 1;
  1123. break;
  1124. case 2: /* 2Gb per chip */
  1125. trfc = DIV_ROUND_UP(160000, clkper) - 1;
  1126. txs = DIV_ROUND_UP(170000, clkper) - 1;
  1127. break;
  1128. case 4: /* 4Gb per chip */
  1129. trfc = DIV_ROUND_UP(260000, clkper) - 1;
  1130. txs = DIV_ROUND_UP(270000, clkper) - 1;
  1131. break;
  1132. case 8: /* 8Gb per chip */
  1133. trfc = DIV_ROUND_UP(350000, clkper) - 1;
  1134. txs = DIV_ROUND_UP(360000, clkper) - 1;
  1135. break;
  1136. default:
  1137. /* invalid density */
  1138. puts("invalid chip density\n");
  1139. hang();
  1140. break;
  1141. }
  1142. txpr = txs;
  1143. switch (mem_speed) {
  1144. case 800:
  1145. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1146. tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1147. if (ddr3_cfg->pagesz == 1) {
  1148. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  1149. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1150. } else {
  1151. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1152. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1153. }
  1154. break;
  1155. case 1066:
  1156. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1157. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  1158. if (ddr3_cfg->pagesz == 1) {
  1159. tfaw = DIV_ROUND_UP(37500, clkper) - 1;
  1160. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  1161. } else {
  1162. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1163. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1164. }
  1165. break;
  1166. default:
  1167. puts("invalid memory speed\n");
  1168. hang();
  1169. break;
  1170. }
  1171. txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
  1172. tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
  1173. taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  1174. tcksrx = tcksre;
  1175. taofpd = taonpd;
  1176. twr = DIV_ROUND_UP(15000, clkper) - 1;
  1177. tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
  1178. trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  1179. tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  1180. tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  1181. trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  1182. twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
  1183. trcd = trp;
  1184. trtp = twtr;
  1185. cs0_end = 4 * sysinfo->cs_density - 1;
  1186. debug("density:%d Gb (%d Gb per chip)\n",
  1187. sysinfo->cs_density, ddr3_cfg->density);
  1188. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  1189. debug("memspd:%d\n", mem_speed);
  1190. debug("tcke=%d\n", tcke);
  1191. debug("tcksrx=%d\n", tcksrx);
  1192. debug("tcksre=%d\n", tcksre);
  1193. debug("taofpd=%d\n", taofpd);
  1194. debug("taonpd=%d\n", taonpd);
  1195. debug("todtlon=%d\n", todtlon);
  1196. debug("tanpd=%d\n", tanpd);
  1197. debug("taxpd=%d\n", taxpd);
  1198. debug("trfc=%d\n", trfc);
  1199. debug("txs=%d\n", txs);
  1200. debug("txp=%d\n", txp);
  1201. debug("txpdll=%d\n", txpdll);
  1202. debug("tfaw=%d\n", tfaw);
  1203. debug("tcl=%d\n", tcl);
  1204. debug("trcd=%d\n", trcd);
  1205. debug("trp=%d\n", trp);
  1206. debug("trc=%d\n", trc);
  1207. debug("tras=%d\n", tras);
  1208. debug("twr=%d\n", twr);
  1209. debug("tmrd=%d\n", tmrd);
  1210. debug("tcwl=%d\n", tcwl);
  1211. debug("tdllk=%d\n", tdllk);
  1212. debug("trtp=%d\n", trtp);
  1213. debug("twtr=%d\n", twtr);
  1214. debug("trrd=%d\n", trrd);
  1215. debug("txpr=%d\n", txpr);
  1216. debug("cs0_end=%d\n", cs0_end);
  1217. debug("ncs=%d\n", sysinfo->ncs);
  1218. debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  1219. debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  1220. debug("SRT=%d\n", ddr3_cfg->SRT);
  1221. debug("twr=%d\n", twr);
  1222. /*
  1223. * board-specific configuration:
  1224. * These values are determined empirically and vary per board layout
  1225. * see:
  1226. * appnote, ddr3 spreadsheet
  1227. */
  1228. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  1229. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  1230. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  1231. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  1232. mmdc0->mprddlctl = calib->p0_mprddlctl;
  1233. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  1234. if (sysinfo->dsize > 1) {
  1235. MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
  1236. MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
  1237. MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
  1238. MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
  1239. MMDC1(mprddlctl, calib->p1_mprddlctl);
  1240. MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
  1241. }
  1242. /* Read data DQ Byte0-3 delay */
  1243. mmdc0->mprddqby0dl = 0x33333333;
  1244. mmdc0->mprddqby1dl = 0x33333333;
  1245. if (sysinfo->dsize > 0) {
  1246. mmdc0->mprddqby2dl = 0x33333333;
  1247. mmdc0->mprddqby3dl = 0x33333333;
  1248. }
  1249. if (sysinfo->dsize > 1) {
  1250. MMDC1(mprddqby0dl, 0x33333333);
  1251. MMDC1(mprddqby1dl, 0x33333333);
  1252. MMDC1(mprddqby2dl, 0x33333333);
  1253. MMDC1(mprddqby3dl, 0x33333333);
  1254. }
  1255. /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
  1256. val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  1257. mmdc0->mpodtctrl = val;
  1258. if (sysinfo->dsize > 1)
  1259. MMDC1(mpodtctrl, val);
  1260. /* complete calibration */
  1261. val = (1 << 11); /* Force measurement on delay-lines */
  1262. mmdc0->mpmur0 = val;
  1263. if (sysinfo->dsize > 1)
  1264. MMDC1(mpmur0, val);
  1265. /* Step 1: configuration request */
  1266. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1267. /* Step 2: Timing configuration */
  1268. mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  1269. (txpdll << 9) | (tfaw << 4) | tcl;
  1270. mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  1271. (tras << 16) | (1 << 15) /* trpa */ |
  1272. (twr << 9) | (tmrd << 5) | tcwl;
  1273. mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  1274. mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  1275. (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  1276. mmdc0->mdasp = cs0_end; /* CS addressing */
  1277. /* Step 3: Configure DDR type */
  1278. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1279. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1280. (sysinfo->ralat << 6);
  1281. /* Step 4: Configure delay while leaving reset */
  1282. mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  1283. (sysinfo->rst_to_cke << 0);
  1284. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1285. coladdr = ddr3_cfg->coladdr;
  1286. if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1287. coladdr += 4;
  1288. else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1289. coladdr += 1;
  1290. mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  1291. (coladdr - 9) << 20 | /* COL */
  1292. (1 << 19) | /* Burst Length = 8 for DDR3 */
  1293. (sysinfo->dsize << 16); /* DDR data bus size */
  1294. /* Step 6: Perform ZQ calibration */
  1295. val = 0xa1390001; /* one-time HW ZQ calib */
  1296. mmdc0->mpzqhwctrl = val;
  1297. if (sysinfo->dsize > 1)
  1298. MMDC1(mpzqhwctrl, val);
  1299. /* Step 7: Enable MMDC with desired chip select */
  1300. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1301. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1302. /* Step 8: Write Mode Registers to Init DDR3 devices */
  1303. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1304. /* MR2 */
  1305. val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
  1306. ((tcwl - 3) & 3) << 3;
  1307. debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
  1308. mmdc0->mdscr = MR(val, 2, 3, cs);
  1309. /* MR3 */
  1310. debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
  1311. mmdc0->mdscr = MR(0, 3, 3, cs);
  1312. /* MR1 */
  1313. val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  1314. ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  1315. debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
  1316. mmdc0->mdscr = MR(val, 1, 3, cs);
  1317. /* MR0 */
  1318. val = ((tcl - 1) << 4) | /* CAS */
  1319. (1 << 8) | /* DLL Reset */
  1320. ((twr - 3) << 9) | /* Write Recovery */
  1321. (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
  1322. debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
  1323. mmdc0->mdscr = MR(val, 0, 3, cs);
  1324. /* ZQ calibration */
  1325. val = (1 << 10);
  1326. mmdc0->mdscr = MR(val, 0, 4, cs);
  1327. }
  1328. /* Step 10: Power down control and self-refresh */
  1329. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1330. 5 << 12 | /* PWDT_1: 256 cycles */
  1331. 5 << 8 | /* PWDT_0: 256 cycles */
  1332. 1 << 6 | /* BOTH_CS_PD */
  1333. (tcksrx & 0x7) << 3 |
  1334. (tcksre & 0x7);
  1335. if (!sysinfo->pd_fast_exit)
  1336. mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
  1337. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1338. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1339. val = 0xa1390003;
  1340. mmdc0->mpzqhwctrl = val;
  1341. if (sysinfo->dsize > 1)
  1342. MMDC1(mpzqhwctrl, val);
  1343. /* Step 12: Configure and activate periodic refresh */
  1344. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1345. /*
  1346. * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
  1347. * configure it and disable MMDC arbitration/reordering (see EB828)
  1348. */
  1349. if (is_mx6dqp() &&
  1350. ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
  1351. (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
  1352. struct mx6dqp_noc_sched_regs *noc_sched =
  1353. (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
  1354. /*
  1355. * These values are fixed based on integration parameters and
  1356. * should not be modified
  1357. */
  1358. noc_sched->rlat = 0x00000040;
  1359. noc_sched->ipu1 = 0x00000020;
  1360. noc_sched->ipu2 = 0x00000020;
  1361. noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
  1362. (tfaw << NOC_FAW_PERIOD_SHIFT) |
  1363. (trrd << NOC_RD_SHIFT);
  1364. noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
  1365. << NOC_BW_RATIO_SHIFT) |
  1366. ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
  1367. ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
  1368. (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
  1369. ((tcwl + twr + trp + trcd)
  1370. << NOC_WR_TO_MISS_SHIFT) |
  1371. ((trtp + trp + trcd - 4)
  1372. << NOC_RD_TO_MISS_SHIFT) |
  1373. (trc << NOC_ACT_TO_ACT_SHIFT);
  1374. if (sysinfo->dsize == 2) {
  1375. if (ddr3_cfg->coladdr == 10) {
  1376. if (ddr3_cfg->rowaddr == 15 &&
  1377. sysinfo->ncs == 2)
  1378. noc_sched->ddrconf = 4;
  1379. else
  1380. noc_sched->ddrconf = 0;
  1381. } else if (ddr3_cfg->coladdr == 11) {
  1382. noc_sched->ddrconf = 1;
  1383. }
  1384. } else {
  1385. if (ddr3_cfg->coladdr == 9) {
  1386. if (ddr3_cfg->rowaddr == 13)
  1387. noc_sched->ddrconf = 2;
  1388. else if (ddr3_cfg->rowaddr == 14)
  1389. noc_sched->ddrconf = 15;
  1390. } else if (ddr3_cfg->coladdr == 10) {
  1391. if (ddr3_cfg->rowaddr == 14 &&
  1392. sysinfo->ncs == 2)
  1393. noc_sched->ddrconf = 14;
  1394. else if (ddr3_cfg->rowaddr == 15 &&
  1395. sysinfo->ncs == 2)
  1396. noc_sched->ddrconf = 9;
  1397. else
  1398. noc_sched->ddrconf = 3;
  1399. } else if (ddr3_cfg->coladdr == 11) {
  1400. if (ddr3_cfg->rowaddr == 15 &&
  1401. sysinfo->ncs == 2)
  1402. noc_sched->ddrconf = 4;
  1403. else
  1404. noc_sched->ddrconf = 0;
  1405. } else if (ddr3_cfg->coladdr == 12) {
  1406. if (ddr3_cfg->rowaddr == 14)
  1407. noc_sched->ddrconf = 1;
  1408. }
  1409. }
  1410. /* Disable MMDC arbitration/reordering */
  1411. mmdc0->maarcr = 0x14420000;
  1412. }
  1413. /* Step 13: Deassert config request - init complete */
  1414. mmdc0->mdscr = 0x00000000;
  1415. /* wait for auto-ZQ calibration to complete */
  1416. mdelay(1);
  1417. }
  1418. void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
  1419. struct mx6_mmdc_calibration *calib)
  1420. {
  1421. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1422. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1423. calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
  1424. calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
  1425. calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
  1426. calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
  1427. calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
  1428. calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
  1429. if (sysinfo->dsize == 2) {
  1430. calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
  1431. calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
  1432. calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
  1433. calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
  1434. calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
  1435. calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
  1436. }
  1437. }
  1438. void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1439. const struct mx6_mmdc_calibration *calib,
  1440. const void *ddr_cfg)
  1441. {
  1442. if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
  1443. mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
  1444. } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
  1445. mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
  1446. } else {
  1447. puts("Unsupported ddr type\n");
  1448. hang();
  1449. }
  1450. }