dp_info.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. *
  5. * Author: Donghwa Lee <dh09.lee@samsung.com>
  6. */
  7. #ifndef _DP_INFO_H
  8. #define _DP_INFO_H
  9. #define msleep(a) udelay(a * 1000)
  10. #define DP_TIMEOUT_LOOP_COUNT 100
  11. #define MAX_CR_LOOP 5
  12. #define MAX_EQ_LOOP 4
  13. #define EXYNOS_DP_SUCCESS 0
  14. enum {
  15. DP_DISABLE,
  16. DP_ENABLE,
  17. };
  18. struct edp_disp_info {
  19. char *name;
  20. unsigned int h_total;
  21. unsigned int h_res;
  22. unsigned int h_sync_width;
  23. unsigned int h_back_porch;
  24. unsigned int h_front_porch;
  25. unsigned int v_total;
  26. unsigned int v_res;
  27. unsigned int v_sync_width;
  28. unsigned int v_back_porch;
  29. unsigned int v_front_porch;
  30. unsigned int v_sync_rate;
  31. };
  32. struct edp_link_train_info {
  33. unsigned int lt_status;
  34. unsigned int ep_loop;
  35. unsigned int cr_loop[4];
  36. };
  37. struct edp_video_info {
  38. unsigned int master_mode;
  39. unsigned int bist_mode;
  40. unsigned int bist_pattern;
  41. unsigned int h_sync_polarity;
  42. unsigned int v_sync_polarity;
  43. unsigned int interlaced;
  44. unsigned int color_space;
  45. unsigned int dynamic_range;
  46. unsigned int ycbcr_coeff;
  47. unsigned int color_depth;
  48. };
  49. struct exynos_dp_priv {
  50. struct edp_disp_info disp_info;
  51. struct edp_link_train_info lt_info;
  52. struct edp_video_info video_info;
  53. /*below info get from panel during training*/
  54. unsigned char lane_bw;
  55. unsigned char lane_cnt;
  56. unsigned char dpcd_rev;
  57. /*support enhanced frame cap */
  58. unsigned char dpcd_efc;
  59. struct exynos_dp *regs;
  60. };
  61. enum analog_power_block {
  62. AUX_BLOCK,
  63. CH0_BLOCK,
  64. CH1_BLOCK,
  65. CH2_BLOCK,
  66. CH3_BLOCK,
  67. ANALOG_TOTAL,
  68. POWER_ALL
  69. };
  70. enum pll_status {
  71. PLL_UNLOCKED = 0,
  72. PLL_LOCKED
  73. };
  74. enum {
  75. COLOR_RGB,
  76. COLOR_YCBCR422,
  77. COLOR_YCBCR444
  78. };
  79. enum {
  80. VESA,
  81. CEA
  82. };
  83. enum {
  84. COLOR_YCBCR601,
  85. COLOR_YCBCR709
  86. };
  87. enum {
  88. COLOR_6,
  89. COLOR_8,
  90. COLOR_10,
  91. COLOR_12
  92. };
  93. enum {
  94. DP_LANE_BW_1_62 = 0x06,
  95. DP_LANE_BW_2_70 = 0x0a,
  96. };
  97. enum {
  98. DP_LANE_CNT_1 = 1,
  99. DP_LANE_CNT_2 = 2,
  100. DP_LANE_CNT_4 = 4,
  101. };
  102. enum {
  103. DP_DPCD_REV_10 = 0x10,
  104. DP_DPCD_REV_11 = 0x11,
  105. };
  106. enum {
  107. DP_LT_NONE,
  108. DP_LT_START,
  109. DP_LT_CR,
  110. DP_LT_ET,
  111. DP_LT_FINISHED,
  112. DP_LT_FAIL,
  113. };
  114. enum {
  115. PRE_EMPHASIS_LEVEL_0,
  116. PRE_EMPHASIS_LEVEL_1,
  117. PRE_EMPHASIS_LEVEL_2,
  118. PRE_EMPHASIS_LEVEL_3,
  119. };
  120. enum {
  121. PRBS7,
  122. D10_2,
  123. TRAINING_PTN1,
  124. TRAINING_PTN2,
  125. DP_NONE
  126. };
  127. enum {
  128. VOLTAGE_LEVEL_0,
  129. VOLTAGE_LEVEL_1,
  130. VOLTAGE_LEVEL_2,
  131. VOLTAGE_LEVEL_3,
  132. };
  133. enum pattern_type {
  134. NO_PATTERN,
  135. COLOR_RAMP,
  136. BALCK_WHITE_V_LINES,
  137. COLOR_SQUARE,
  138. INVALID_PATTERN,
  139. COLORBAR_32,
  140. COLORBAR_64,
  141. WHITE_GRAY_BALCKBAR_32,
  142. WHITE_GRAY_BALCKBAR_64,
  143. MOBILE_WHITEBAR_32,
  144. MOBILE_WHITEBAR_64
  145. };
  146. enum {
  147. CALCULATED_M,
  148. REGISTER_M
  149. };
  150. enum {
  151. VIDEO_TIMING_FROM_CAPTURE,
  152. VIDEO_TIMING_FROM_REGISTER
  153. };
  154. struct exynos_dp_platform_data {
  155. struct exynos_dp_priv *edp_dev_info;
  156. };
  157. #ifdef CONFIG_EXYNOS_DP
  158. unsigned int exynos_init_dp(void);
  159. #else
  160. unsigned int exynos_init_dp(void)
  161. {
  162. return 0;
  163. }
  164. #endif
  165. #include <linux/delay.h>
  166. #endif /* _DP_INFO_H */