mpddrc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. *
  6. * Copyright (C) 2015 Atmel Corporation
  7. * Wenyou Yang <wenyou.yang@atmel.com>
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/atmel_mpddrc.h>
  12. #include <asm/arch/at91_common.h>
  13. #include <linux/delay.h>
  14. #define SAMA5D3_MPDDRC_VERSION 0x140
  15. static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
  16. int mode,
  17. u32 ram_address)
  18. {
  19. writel(mode, &mpddr->mr);
  20. dmb();
  21. writel(0, ram_address);
  22. }
  23. static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
  24. {
  25. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  26. u16 version = readl(&mpddr->version) & 0xffff;
  27. if ((version >= SAMA5D3_MPDDRC_VERSION) &&
  28. (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
  29. return 0;
  30. return 1;
  31. }
  32. int ddr2_init(const unsigned int base,
  33. const unsigned int ram_address,
  34. const struct atmel_mpddrc_config *mpddr_value)
  35. {
  36. const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  37. u32 ba_off, cr;
  38. /* Compute bank offset according to NC in configuration register */
  39. ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
  40. if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
  41. ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
  42. ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
  43. /* Program the memory device type into the memory device register */
  44. writel(mpddr_value->md, &mpddr->md);
  45. /* Program the configuration register */
  46. writel(mpddr_value->cr, &mpddr->cr);
  47. /* Program the timing register */
  48. writel(mpddr_value->tpr0, &mpddr->tpr0);
  49. writel(mpddr_value->tpr1, &mpddr->tpr1);
  50. writel(mpddr_value->tpr2, &mpddr->tpr2);
  51. /* Issue a NOP command */
  52. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  53. /* A 200 us is provided to precede any signal toggle */
  54. udelay(200);
  55. /* Issue a NOP command */
  56. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  57. /* Issue an all banks precharge command */
  58. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  59. /* Issue an extended mode register set(EMRS2) to choose operation */
  60. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  61. ram_address + (0x2 << ba_off));
  62. /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
  63. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  64. ram_address + (0x3 << ba_off));
  65. /*
  66. * Issue an extended mode register set(EMRS1) to enable DLL and
  67. * program D.I.C (output driver impedance control)
  68. */
  69. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  70. ram_address + (0x1 << ba_off));
  71. /* Enable DLL reset */
  72. cr = readl(&mpddr->cr);
  73. writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
  74. /* A mode register set(MRS) cycle is issued to reset DLL */
  75. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  76. /* Issue an all banks precharge command */
  77. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  78. /* Two auto-refresh (CBR) cycles are provided */
  79. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  80. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  81. /* Disable DLL reset */
  82. cr = readl(&mpddr->cr);
  83. writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
  84. /* A mode register set (MRS) cycle is issued to disable DLL reset */
  85. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  86. /* Set OCD calibration in default state */
  87. cr = readl(&mpddr->cr);
  88. writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
  89. /*
  90. * An extended mode register set (EMRS1) cycle is issued
  91. * to OCD default value
  92. */
  93. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  94. ram_address + (0x1 << ba_off));
  95. /* OCD calibration mode exit */
  96. cr = readl(&mpddr->cr);
  97. writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
  98. /*
  99. * An extended mode register set (EMRS1) cycle is issued
  100. * to enable OCD exit
  101. */
  102. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  103. ram_address + (0x1 << ba_off));
  104. /* A nornal mode command is provided */
  105. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  106. /* Perform a write access to any DDR2-SDRAM address */
  107. writel(0, ram_address);
  108. /* Write the refresh rate */
  109. writel(mpddr_value->rtr, &mpddr->rtr);
  110. return 0;
  111. }
  112. int ddr3_init(const unsigned int base,
  113. const unsigned int ram_address,
  114. const struct atmel_mpddrc_config *mpddr_value)
  115. {
  116. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  117. u32 ba_off;
  118. /* Compute bank offset according to NC in configuration register */
  119. ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
  120. if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
  121. ba_off += ((mpddr_value->cr &
  122. ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
  123. ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
  124. /* Program the memory device type */
  125. writel(mpddr_value->md, &mpddr->md);
  126. /*
  127. * Program features of the DDR3-SDRAM device and timing parameters
  128. */
  129. writel(mpddr_value->cr, &mpddr->cr);
  130. writel(mpddr_value->tpr0, &mpddr->tpr0);
  131. writel(mpddr_value->tpr1, &mpddr->tpr1);
  132. writel(mpddr_value->tpr2, &mpddr->tpr2);
  133. /* A NOP command is issued to the DDR3-SRAM */
  134. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  135. /* A pause of at least 500us must be observed before a single toggle. */
  136. udelay(500);
  137. /* A NOP command is issued to the DDR3-SDRAM */
  138. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  139. /*
  140. * An Extended Mode Register Set (EMRS2) cycle is issued to choose
  141. * between commercial or high temperature operations.
  142. */
  143. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  144. ram_address + (0x2 << ba_off));
  145. /*
  146. * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
  147. * the Extended Mode Register to 0.
  148. */
  149. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  150. ram_address + (0x3 << ba_off));
  151. /*
  152. * An Extended Mode Register Set (EMRS1) cycle is issued to disable and
  153. * to program O.D.S. (Output Driver Strength).
  154. */
  155. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  156. ram_address + (0x1 << ba_off));
  157. /*
  158. * Write a one to the DLL bit (enable DLL reset) in the MPDDRC
  159. * Configuration Register.
  160. */
  161. /* A Mode Register Set (MRS) cycle is issued to reset DLL. */
  162. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  163. udelay(50);
  164. /*
  165. * A Calibration command (MRS) is issued to calibrate RTT and RON
  166. * values for the Process Voltage Temperature (PVT).
  167. */
  168. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
  169. /* A Normal Mode command is provided. */
  170. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  171. /* Perform a write access to any DDR3-SDRAM address. */
  172. writel(0, ram_address);
  173. /*
  174. * Write the refresh rate into the COUNT field in the MPDDRC
  175. * Refresh Timer Register (MPDDRC_RTR):
  176. */
  177. writel(mpddr_value->rtr, &mpddr->rtr);
  178. return 0;
  179. }
  180. int lpddr2_init(const unsigned int base,
  181. const unsigned int ram_address,
  182. const struct atmel_mpddrc_config *mpddr_value)
  183. {
  184. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  185. u32 reg;
  186. writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr);
  187. writel(mpddr_value->tim_cal, &mpddr->tim_cal);
  188. /* 1. Program the memory device type */
  189. writel(mpddr_value->md, &mpddr->md);
  190. /*
  191. * 2. Program features of the LPDDR2-SDRAM device and timing parameters
  192. */
  193. writel(mpddr_value->cr, &mpddr->cr);
  194. writel(mpddr_value->tpr0, &mpddr->tpr0);
  195. writel(mpddr_value->tpr1, &mpddr->tpr1);
  196. writel(mpddr_value->tpr2, &mpddr->tpr2);
  197. /* 3. A NOP command is issued to the LPDDR2-SDRAM */
  198. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  199. /*
  200. * 3bis. Add memory barrier then Perform a write access to
  201. * any low-power DDR2-SDRAM address to acknowledge the command.
  202. */
  203. dmb();
  204. writel(0, ram_address);
  205. /* 4. A pause of at least 100 ns must be observed before a single toggle */
  206. udelay(1);
  207. /* 5. A NOP command is issued to the LPDDR2-SDRAM */
  208. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  209. /* 6. A pause of at least 200 us must be observed before a Reset Command */
  210. udelay(200);
  211. /* 7. A Reset command is issued to the low-power DDR2-SDRAM. */
  212. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  213. ATMEL_MPDDRC_MR_MRS(63), ram_address);
  214. /*
  215. * 8. A pause of at least tINIT5 must be observed before issuing
  216. * any commands
  217. */
  218. udelay(1);
  219. /* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */
  220. reg = readl(&mpddr->cr);
  221. reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
  222. reg |= ATMEL_MPDDRC_CR_ZQ_RESET;
  223. writel(reg, &mpddr->cr);
  224. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  225. ATMEL_MPDDRC_MR_MRS(10), ram_address);
  226. /*
  227. * 9bis: The ZQ Calibration command is now issued.
  228. * Program the type of calibration in the MPDDRC_CR: set the
  229. * ZQ field to the SHORT value.
  230. */
  231. reg = readl(&mpddr->cr);
  232. reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
  233. reg |= ATMEL_MPDDRC_CR_ZQ_SHORT;
  234. writel(reg, &mpddr->cr);
  235. /*
  236. * 10: A Mode Register Write command with 1 to the MRS field
  237. * is issued to the low-power DDR2-SDRAM.
  238. */
  239. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  240. ATMEL_MPDDRC_MR_MRS(1), ram_address);
  241. /*
  242. * 11: A Mode Register Write command with 2 to the MRS field
  243. * is issued to the low-power DDR2-SDRAM.
  244. */
  245. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  246. ATMEL_MPDDRC_MR_MRS(2), ram_address);
  247. /*
  248. * 12: A Mode Register Write command with 3 to the MRS field
  249. * is issued to the low-power DDR2-SDRAM.
  250. */
  251. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  252. ATMEL_MPDDRC_MR_MRS(3), ram_address);
  253. /*
  254. * 13: A Mode Register Write command with 16 to the MRS field
  255. * is issued to the low-power DDR2-SDRAM.
  256. */
  257. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  258. ATMEL_MPDDRC_MR_MRS(16), ram_address);
  259. /*
  260. * 14: In the DDR Configuration Register, open the input buffers.
  261. */
  262. #ifdef CONFIG_ATMEL_SFR
  263. configure_ddrcfg_input_buffers(true);
  264. #endif
  265. /* 15. A NOP command is issued to the LPDDR2-SDRAM */
  266. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  267. /*
  268. * 16: A Mode Register Write command with 5 to the MRS field
  269. * is issued to the low-power DDR2-SDRAM.
  270. */
  271. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  272. ATMEL_MPDDRC_MR_MRS(5), ram_address);
  273. /*
  274. * 17: A Mode Register Write command with 6 to the MRS field
  275. * is issued to the low-power DDR2-SDRAM.
  276. */
  277. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  278. ATMEL_MPDDRC_MR_MRS(6), ram_address);
  279. /*
  280. * 18: A Mode Register Write command with 8 to the MRS field
  281. * is issued to the low-power DDR2-SDRAM.
  282. */
  283. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  284. ATMEL_MPDDRC_MR_MRS(8), ram_address);
  285. /*
  286. * 19: A Mode Register Write command with 0 to the MRS field
  287. * is issued to the low-power DDR2-SDRAM.
  288. */
  289. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  290. ATMEL_MPDDRC_MR_MRS(0), ram_address);
  291. /*
  292. * 20: A Normal Mode command is provided.
  293. */
  294. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  295. /* 21: In the DDR Configuration Register, close the input buffers. */
  296. #ifdef CONFIG_ATMEL_SFR
  297. configure_ddrcfg_input_buffers(false);
  298. #endif
  299. /*
  300. * 22: Write the refresh rate into the COUNT field in the MPDDRC
  301. * Refresh Timer Register.
  302. */
  303. writel(mpddr_value->rtr, &mpddr->rtr);
  304. /* 23. Configre CAL MR4 register */
  305. writel(mpddr_value->cal_mr4, &mpddr->cal_mr4);
  306. return 0;
  307. }