clock.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  4. *
  5. * Copyright (C) 2005 David Brownell
  6. * Copyright (C) 2005 Ivan Kokshaysky
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
  9. * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
  10. */
  11. #include <common.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/at91_pmc.h>
  17. #include <asm/arch/clk.h>
  18. #if !defined(CONFIG_AT91FAMILY)
  19. # error You need to define CONFIG_AT91FAMILY in your board config!
  20. #endif
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static unsigned long at91_css_to_rate(unsigned long css)
  23. {
  24. switch (css) {
  25. case AT91_PMC_MCKR_CSS_SLOW:
  26. return CONFIG_SYS_AT91_SLOW_CLOCK;
  27. case AT91_PMC_MCKR_CSS_MAIN:
  28. return gd->arch.main_clk_rate_hz;
  29. case AT91_PMC_MCKR_CSS_PLLA:
  30. return gd->arch.plla_rate_hz;
  31. }
  32. return 0;
  33. }
  34. static u32 at91_pll_rate(u32 freq, u32 reg)
  35. {
  36. unsigned mul, div;
  37. div = reg & 0xff;
  38. mul = (reg >> 18) & 0x7f;
  39. if (div && mul) {
  40. freq /= div;
  41. freq *= mul + 1;
  42. } else {
  43. freq = 0;
  44. }
  45. return freq;
  46. }
  47. int at91_clock_init(unsigned long main_clock)
  48. {
  49. unsigned freq, mckr;
  50. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  51. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  52. unsigned tmp;
  53. /*
  54. * When the bootloader initialized the main oscillator correctly,
  55. * there's no problem using the cycle counter. But if it didn't,
  56. * or when using oscillator bypass mode, we must be told the speed
  57. * of the main clock.
  58. */
  59. if (!main_clock) {
  60. do {
  61. tmp = readl(&pmc->mcfr);
  62. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  63. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  64. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  65. }
  66. #endif
  67. gd->arch.main_clk_rate_hz = main_clock;
  68. /* report if PLLA is more than mildly overclocked */
  69. gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  70. /*
  71. * MCK and CPU derive from one of those primary clocks.
  72. * For now, assume this parentage won't change.
  73. */
  74. mckr = readl(&pmc->mckr);
  75. /* plla divisor by 2 */
  76. if (mckr & (1 << 12))
  77. gd->arch.plla_rate_hz >>= 1;
  78. gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  79. freq = gd->arch.mck_rate_hz;
  80. /* prescale */
  81. freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
  82. switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
  83. case AT91_PMC_MCKR_MDIV_2:
  84. gd->arch.mck_rate_hz = freq / 2;
  85. break;
  86. case AT91_PMC_MCKR_MDIV_3:
  87. gd->arch.mck_rate_hz = freq / 3;
  88. break;
  89. case AT91_PMC_MCKR_MDIV_4:
  90. gd->arch.mck_rate_hz = freq / 4;
  91. break;
  92. default:
  93. break;
  94. }
  95. gd->arch.cpu_clk_rate_hz = freq;
  96. return 0;
  97. }
  98. void at91_plla_init(u32 pllar)
  99. {
  100. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  101. writel(pllar, &pmc->pllar);
  102. while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
  103. ;
  104. }
  105. void at91_mck_init(u32 mckr)
  106. {
  107. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  108. u32 tmp;
  109. tmp = readl(&pmc->mckr);
  110. tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
  111. AT91_PMC_MCKR_PRES_MASK |
  112. AT91_PMC_MCKR_MDIV_MASK |
  113. AT91_PMC_MCKR_PLLADIV_2);
  114. #ifdef CPU_HAS_H32MXDIV
  115. tmp &= ~AT91_PMC_MCKR_H32MXDIV;
  116. #endif
  117. tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
  118. AT91_PMC_MCKR_PRES_MASK |
  119. AT91_PMC_MCKR_MDIV_MASK |
  120. AT91_PMC_MCKR_PLLADIV_2);
  121. #ifdef CPU_HAS_H32MXDIV
  122. tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
  123. #endif
  124. writel(tmp, &pmc->mckr);
  125. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  126. ;
  127. }
  128. /*
  129. * For the Master Clock Controller Register(MCKR), while switching
  130. * to a lower clock source, we must switch the clock source first
  131. * instead of last. Otherwise, we could end up with too high frequency
  132. * on the internal bus and peripherals.
  133. */
  134. void at91_mck_init_down(u32 mckr)
  135. {
  136. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  137. u32 tmp;
  138. tmp = readl(&pmc->mckr);
  139. tmp &= (~AT91_PMC_MCKR_CSS_MASK);
  140. tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
  141. writel(tmp, &pmc->mckr);
  142. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  143. ;
  144. #ifdef CPU_HAS_H32MXDIV
  145. tmp = readl(&pmc->mckr);
  146. tmp &= (~AT91_PMC_MCKR_H32MXDIV);
  147. tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
  148. writel(tmp, &pmc->mckr);
  149. #endif
  150. tmp = readl(&pmc->mckr);
  151. tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
  152. tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
  153. writel(tmp, &pmc->mckr);
  154. tmp = readl(&pmc->mckr);
  155. tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
  156. tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
  157. writel(tmp, &pmc->mckr);
  158. tmp = readl(&pmc->mckr);
  159. tmp &= (~AT91_PMC_MCKR_PRES_MASK);
  160. tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
  161. writel(tmp, &pmc->mckr);
  162. }
  163. int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
  164. {
  165. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  166. u32 regval, status;
  167. u32 timeout = 1000;
  168. if (id > AT91_PMC_PCR_PID_MASK)
  169. return -EINVAL;
  170. if (div > 0xff)
  171. return -EINVAL;
  172. if (clk_source == GCK_CSS_UPLL_CLK) {
  173. if (at91_upll_clk_enable())
  174. return -ENODEV;
  175. }
  176. writel(id, &pmc->pcr);
  177. regval = readl(&pmc->pcr);
  178. regval &= ~AT91_PMC_PCR_GCKCSS;
  179. regval &= ~AT91_PMC_PCR_GCKDIV;
  180. switch (clk_source) {
  181. case GCK_CSS_SLOW_CLK:
  182. regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
  183. break;
  184. case GCK_CSS_MAIN_CLK:
  185. regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
  186. break;
  187. case GCK_CSS_PLLA_CLK:
  188. regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
  189. break;
  190. case GCK_CSS_UPLL_CLK:
  191. regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
  192. break;
  193. case GCK_CSS_MCK_CLK:
  194. regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
  195. break;
  196. case GCK_CSS_AUDIO_CLK:
  197. regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
  198. break;
  199. default:
  200. printf("Error GCK clock source selection!\n");
  201. return -EINVAL;
  202. }
  203. regval |= AT91_PMC_PCR_CMD_WRITE |
  204. AT91_PMC_PCR_GCKDIV_(div) |
  205. AT91_PMC_PCR_GCKEN;
  206. writel(regval, &pmc->pcr);
  207. do {
  208. udelay(1);
  209. status = readl(&pmc->sr);
  210. } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
  211. if (!timeout)
  212. printf("Timeout waiting for GCK ready!\n");
  213. return 0;
  214. }
  215. u32 at91_get_periph_generated_clk(u32 id)
  216. {
  217. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  218. u32 regval, clk_source, div;
  219. u32 freq;
  220. if (id > AT91_PMC_PCR_PID_MASK)
  221. return 0;
  222. writel(id, &pmc->pcr);
  223. regval = readl(&pmc->pcr);
  224. clk_source = regval & AT91_PMC_PCR_GCKCSS;
  225. switch (clk_source) {
  226. case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
  227. freq = CONFIG_SYS_AT91_SLOW_CLOCK;
  228. break;
  229. case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
  230. freq = gd->arch.main_clk_rate_hz;
  231. break;
  232. case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
  233. freq = gd->arch.plla_rate_hz;
  234. break;
  235. case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
  236. freq = AT91_UTMI_PLL_CLK_FREQ;
  237. break;
  238. case AT91_PMC_PCR_GCKCSS_MCK_CLK:
  239. freq = gd->arch.mck_rate_hz;
  240. break;
  241. default:
  242. printf("Improper GCK clock source selection!\n");
  243. freq = 0;
  244. break;
  245. }
  246. div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
  247. div += 1;
  248. return freq / div;
  249. }