fsl_lsch3_serdes.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016-2018 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/arch/soc.h>
  14. #include <fsl-mc/ldpaa_wriop.h>
  15. #ifdef CONFIG_SYS_FSL_SRDS_1
  16. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  17. #endif
  18. #ifdef CONFIG_SYS_FSL_SRDS_2
  19. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  20. #endif
  21. #ifdef CONFIG_SYS_NXP_SRDS_3
  22. static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  23. #endif
  24. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  25. #ifdef CONFIG_ARCH_LX2160A
  26. int xfi_dpmac[XFI14 + 1];
  27. int sgmii_dpmac[SGMII18 + 1];
  28. int a25gaui_dpmac[_25GE10 + 1];
  29. int xlaui_dpmac[_40GE2 + 1];
  30. int caui2_dpmac[_50GE2 + 1];
  31. int caui4_dpmac[_100GE2 + 1];
  32. #else
  33. int xfi_dpmac[XFI8 + 1];
  34. int sgmii_dpmac[SGMII16 + 1];
  35. #endif
  36. #endif
  37. __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  38. {
  39. return;
  40. }
  41. /*
  42. *The return value of this func is the serdes protocol used.
  43. *Typically this function is called number of times depending
  44. *upon the number of serdes blocks in the Silicon.
  45. *Zero is used to denote that no serdes was enabled,
  46. *this is the case when golden RCW was used where DPAA2 bring was
  47. *intentionally removed to achieve boot to prompt
  48. */
  49. __weak int serdes_get_number(int serdes, int cfg)
  50. {
  51. return cfg;
  52. }
  53. int is_serdes_configured(enum srds_prtcl device)
  54. {
  55. int ret = 0;
  56. #ifdef CONFIG_SYS_FSL_SRDS_1
  57. if (!serdes1_prtcl_map[NONE])
  58. fsl_serdes_init();
  59. ret |= serdes1_prtcl_map[device];
  60. #endif
  61. #ifdef CONFIG_SYS_FSL_SRDS_2
  62. if (!serdes2_prtcl_map[NONE])
  63. fsl_serdes_init();
  64. ret |= serdes2_prtcl_map[device];
  65. #endif
  66. #ifdef CONFIG_SYS_NXP_SRDS_3
  67. if (!serdes3_prtcl_map[NONE])
  68. fsl_serdes_init();
  69. ret |= serdes3_prtcl_map[device];
  70. #endif
  71. return !!ret;
  72. }
  73. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  74. {
  75. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  76. u32 cfg = 0;
  77. int i;
  78. switch (sd) {
  79. #ifdef CONFIG_SYS_FSL_SRDS_1
  80. case FSL_SRDS_1:
  81. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  82. cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  83. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  84. break;
  85. #endif
  86. #ifdef CONFIG_SYS_FSL_SRDS_2
  87. case FSL_SRDS_2:
  88. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  89. cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
  90. cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
  91. break;
  92. #endif
  93. #ifdef CONFIG_SYS_NXP_SRDS_3
  94. case NXP_SRDS_3:
  95. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  96. cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
  97. cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
  98. break;
  99. #endif
  100. default:
  101. printf("invalid SerDes%d\n", sd);
  102. break;
  103. }
  104. cfg = serdes_get_number(sd, cfg);
  105. /* Is serdes enabled at all? */
  106. if (cfg == 0)
  107. return -ENODEV;
  108. for (i = 0; i < SRDS_MAX_LANES; i++) {
  109. if (serdes_get_prtcl(sd, cfg, i) == device)
  110. return i;
  111. }
  112. return -ENODEV;
  113. }
  114. void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
  115. u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  116. {
  117. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  118. u32 cfg;
  119. int lane;
  120. if (serdes_prtcl_map[NONE])
  121. return;
  122. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  123. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  124. cfg >>= sd_prctl_shift;
  125. cfg = serdes_get_number(sd, cfg);
  126. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  127. if (!is_serdes_prtcl_valid(sd, cfg))
  128. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  129. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  130. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  131. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  132. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  133. else {
  134. serdes_prtcl_map[lane_prtcl] = 1;
  135. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  136. #ifdef CONFIG_ARCH_LX2160A
  137. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
  138. wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
  139. (int)lane_prtcl);
  140. if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
  141. wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
  142. (int)lane_prtcl);
  143. if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
  144. wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
  145. (int)lane_prtcl);
  146. if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
  147. wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
  148. (int)lane_prtcl);
  149. if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
  150. wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
  151. (int)lane_prtcl);
  152. if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
  153. wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
  154. (int)lane_prtcl);
  155. #else
  156. switch (lane_prtcl) {
  157. case QSGMII_A:
  158. case QSGMII_B:
  159. case QSGMII_C:
  160. case QSGMII_D:
  161. wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
  162. break;
  163. default:
  164. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
  165. wriop_init_dpmac(sd,
  166. xfi_dpmac[lane_prtcl],
  167. (int)lane_prtcl);
  168. if (lane_prtcl >= SGMII1 &&
  169. lane_prtcl <= SGMII16)
  170. wriop_init_dpmac(sd, sgmii_dpmac[
  171. lane_prtcl],
  172. (int)lane_prtcl);
  173. break;
  174. }
  175. #endif
  176. #endif
  177. }
  178. }
  179. /* Set the first element to indicate serdes has been initialized */
  180. serdes_prtcl_map[NONE] = 1;
  181. }
  182. __weak int get_serdes_volt(void)
  183. {
  184. return -1;
  185. }
  186. __weak int set_serdes_volt(int svdd)
  187. {
  188. return -1;
  189. }
  190. #define LNAGCR0_RT_RSTB 0x00600000
  191. #define RSTCTL_RESET_MASK 0x000000E0
  192. #define RSTCTL_RSTREQ 0x80000000
  193. #define RSTCTL_RST_DONE 0x40000000
  194. #define RSTCTL_RSTERR 0x20000000
  195. #define RSTCTL_SDEN 0x00000020
  196. #define RSTCTL_SDRST_B 0x00000040
  197. #define RSTCTL_PLLRST_B 0x00000080
  198. #define TCALCR_CALRST_B 0x08000000
  199. struct serdes_prctl_info {
  200. u32 id;
  201. u32 mask;
  202. u32 shift;
  203. };
  204. struct serdes_prctl_info srds_prctl_info[] = {
  205. #ifdef CONFIG_SYS_FSL_SRDS_1
  206. {.id = 1,
  207. .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  208. .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
  209. },
  210. #endif
  211. #ifdef CONFIG_SYS_FSL_SRDS_2
  212. {.id = 2,
  213. .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  214. .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
  215. },
  216. #endif
  217. #ifdef CONFIG_SYS_NXP_SRDS_3
  218. {.id = 3,
  219. .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  220. .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
  221. },
  222. #endif
  223. {} /* NULL ENTRY */
  224. };
  225. static int get_serdes_prctl_info_idx(u32 serdes_id)
  226. {
  227. int pos = 0;
  228. struct serdes_prctl_info *srds_info;
  229. /* loop until NULL ENTRY defined by .id=0 */
  230. for (srds_info = srds_prctl_info; srds_info->id != 0;
  231. srds_info++, pos++) {
  232. if (srds_info->id == serdes_id)
  233. return pos;
  234. }
  235. return -1;
  236. }
  237. static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
  238. struct ccsr_serdes __iomem *serdes_base,
  239. bool cmplt)
  240. {
  241. int i, pos;
  242. u32 cfg_tmp;
  243. pos = get_serdes_prctl_info_idx(serdes_id);
  244. if (pos == -1) {
  245. printf("invalid serdes_id %d\n", serdes_id);
  246. return;
  247. }
  248. cfg_tmp = cfg & srds_prctl_info[pos].mask;
  249. cfg_tmp >>= srds_prctl_info[pos].shift;
  250. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  251. if (cmplt)
  252. setbits_le32(&serdes_base->lane[i].gcr0,
  253. LNAGCR0_RT_RSTB);
  254. else
  255. clrbits_le32(&serdes_base->lane[i].gcr0,
  256. LNAGCR0_RT_RSTB);
  257. }
  258. }
  259. static void do_pll_reset(u32 cfg,
  260. struct ccsr_serdes __iomem *serdes_base)
  261. {
  262. int i;
  263. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  264. clrbits_le32(&serdes_base->bank[i].rstctl,
  265. RSTCTL_RESET_MASK);
  266. udelay(1);
  267. setbits_le32(&serdes_base->bank[i].rstctl,
  268. RSTCTL_RSTREQ);
  269. }
  270. udelay(1);
  271. }
  272. static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
  273. {
  274. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  275. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  276. }
  277. static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
  278. struct ccsr_serdes __iomem *serdes_base)
  279. {
  280. if (!(cfg == 0x3 && i == 1)) {
  281. udelay(1);
  282. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  283. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  284. }
  285. udelay(1);
  286. }
  287. static void do_pll_reset_done(u32 cfg,
  288. struct ccsr_serdes __iomem *serdes_base)
  289. {
  290. int i;
  291. u32 reg = 0;
  292. for (i = 0; i < 2; i++) {
  293. reg = in_le32(&serdes_base->bank[i].pllcr0);
  294. if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  295. setbits_le32(&serdes_base->bank[i].rstctl,
  296. RSTCTL_RST_DONE);
  297. }
  298. }
  299. }
  300. static void do_serdes_enable(u32 cfg,
  301. struct ccsr_serdes __iomem *serdes_base)
  302. {
  303. int i;
  304. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  305. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
  306. udelay(1);
  307. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
  308. udelay(1);
  309. /* Take the Rx/Tx calibration out of reset */
  310. do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
  311. }
  312. }
  313. static void do_pll_lock(u32 cfg,
  314. struct ccsr_serdes __iomem *serdes_base)
  315. {
  316. int i;
  317. u32 reg = 0;
  318. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  319. /* if the PLL is not locked, set RST_ERR */
  320. reg = in_le32(&serdes_base->bank[i].pllcr0);
  321. if (!((reg >> 23) & 0x1)) {
  322. setbits_le32(&serdes_base->bank[i].rstctl,
  323. RSTCTL_RSTERR);
  324. } else {
  325. udelay(1);
  326. setbits_le32(&serdes_base->bank[i].rstctl,
  327. RSTCTL_SDRST_B);
  328. udelay(1);
  329. }
  330. }
  331. }
  332. int setup_serdes_volt(u32 svdd)
  333. {
  334. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  335. struct ccsr_serdes __iomem *serdes1_base =
  336. (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
  337. u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  338. #ifdef CONFIG_SYS_FSL_SRDS_2
  339. struct ccsr_serdes __iomem *serdes2_base =
  340. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
  341. u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  342. #endif
  343. #ifdef CONFIG_SYS_NXP_SRDS_3
  344. struct ccsr_serdes __iomem *serdes3_base =
  345. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
  346. u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  347. #endif
  348. u32 cfg_tmp;
  349. int svdd_cur, svdd_tar;
  350. int ret = 1;
  351. /* Only support switch SVDD to 900mV */
  352. if (svdd != 900)
  353. return -EINVAL;
  354. /* Scale up to the LTC resolution is 1/4096V */
  355. svdd = (svdd * 4096) / 1000;
  356. svdd_tar = svdd;
  357. svdd_cur = get_serdes_volt();
  358. if (svdd_cur < 0)
  359. return -EINVAL;
  360. debug("%s: current SVDD: %x; target SVDD: %x\n",
  361. __func__, svdd_cur, svdd_tar);
  362. if (svdd_cur == svdd_tar)
  363. return 0;
  364. /* Put the all enabled lanes in reset */
  365. #ifdef CONFIG_SYS_FSL_SRDS_1
  366. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
  367. #endif
  368. #ifdef CONFIG_SYS_FSL_SRDS_2
  369. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
  370. #endif
  371. #ifdef CONFIG_SYS_NXP_SRDS_3
  372. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
  373. #endif
  374. /* Put the all enabled PLL in reset */
  375. #ifdef CONFIG_SYS_FSL_SRDS_1
  376. cfg_tmp = cfg_rcwsrds1 & 0x3;
  377. do_pll_reset(cfg_tmp, serdes1_base);
  378. #endif
  379. #ifdef CONFIG_SYS_FSL_SRDS_2
  380. cfg_tmp = cfg_rcwsrds1 & 0xC;
  381. cfg_tmp >>= 2;
  382. do_pll_reset(cfg_tmp, serdes2_base);
  383. #endif
  384. #ifdef CONFIG_SYS_NXP_SRDS_3
  385. cfg_tmp = cfg_rcwsrds3 & 0x30;
  386. cfg_tmp >>= 4;
  387. do_pll_reset(cfg_tmp, serdes3_base);
  388. #endif
  389. /* Put the Rx/Tx calibration into reset */
  390. #ifdef CONFIG_SYS_FSL_SRDS_1
  391. do_rx_tx_cal_reset(serdes1_base);
  392. #endif
  393. #ifdef CONFIG_SYS_FSL_SRDS_2
  394. do_rx_tx_cal_reset(serdes2_base);
  395. #endif
  396. #ifdef CONFIG_SYS_NXP_SRDS_3
  397. do_rx_tx_cal_reset(serdes3_base);
  398. #endif
  399. ret = set_serdes_volt(svdd);
  400. if (ret < 0) {
  401. printf("could not change SVDD\n");
  402. ret = -1;
  403. }
  404. /* For each PLL that’s not disabled via RCW enable the SERDES */
  405. #ifdef CONFIG_SYS_FSL_SRDS_1
  406. cfg_tmp = cfg_rcwsrds1 & 0x3;
  407. do_serdes_enable(cfg_tmp, serdes1_base);
  408. #endif
  409. #ifdef CONFIG_SYS_FSL_SRDS_2
  410. cfg_tmp = cfg_rcwsrds1 & 0xC;
  411. cfg_tmp >>= 2;
  412. do_serdes_enable(cfg_tmp, serdes2_base);
  413. #endif
  414. #ifdef CONFIG_SYS_NXP_SRDS_3
  415. cfg_tmp = cfg_rcwsrds3 & 0x30;
  416. cfg_tmp >>= 4;
  417. do_serdes_enable(cfg_tmp, serdes3_base);
  418. #endif
  419. /* Wait for at at least 625us, ensure the PLLs being reset are locked */
  420. udelay(800);
  421. #ifdef CONFIG_SYS_FSL_SRDS_1
  422. cfg_tmp = cfg_rcwsrds1 & 0x3;
  423. do_pll_lock(cfg_tmp, serdes1_base);
  424. #endif
  425. #ifdef CONFIG_SYS_FSL_SRDS_2
  426. cfg_tmp = cfg_rcwsrds1 & 0xC;
  427. cfg_tmp >>= 2;
  428. do_pll_lock(cfg_tmp, serdes2_base);
  429. #endif
  430. #ifdef CONFIG_SYS_NXP_SRDS_3
  431. cfg_tmp = cfg_rcwsrds3 & 0x30;
  432. cfg_tmp >>= 4;
  433. do_pll_lock(cfg_tmp, serdes3_base);
  434. #endif
  435. /* Take the all enabled lanes out of reset */
  436. #ifdef CONFIG_SYS_FSL_SRDS_1
  437. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
  438. #endif
  439. #ifdef CONFIG_SYS_FSL_SRDS_2
  440. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
  441. #endif
  442. #ifdef CONFIG_SYS_NXP_SRDS_3
  443. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
  444. #endif
  445. /* For each PLL being reset, and achieved PLL lock set RST_DONE */
  446. #ifdef CONFIG_SYS_FSL_SRDS_1
  447. cfg_tmp = cfg_rcwsrds1 & 0x3;
  448. do_pll_reset_done(cfg_tmp, serdes1_base);
  449. #endif
  450. #ifdef CONFIG_SYS_FSL_SRDS_2
  451. cfg_tmp = cfg_rcwsrds1 & 0xC;
  452. cfg_tmp >>= 2;
  453. do_pll_reset_done(cfg_tmp, serdes2_base);
  454. #endif
  455. #ifdef CONFIG_SYS_NXP_SRDS_3
  456. cfg_tmp = cfg_rcwsrds3 & 0x30;
  457. cfg_tmp >>= 4;
  458. do_pll_reset_done(cfg_tmp, serdes3_base);
  459. #endif
  460. return ret;
  461. }
  462. void fsl_serdes_init(void)
  463. {
  464. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  465. int i , j;
  466. #ifdef CONFIG_ARCH_LX2160A
  467. for (i = XFI1, j = 1; i <= XFI14; i++, j++)
  468. xfi_dpmac[i] = j;
  469. for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
  470. sgmii_dpmac[i] = j;
  471. for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
  472. a25gaui_dpmac[i] = j;
  473. for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
  474. xlaui_dpmac[i] = j;
  475. for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
  476. caui2_dpmac[i] = j;
  477. for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
  478. caui4_dpmac[i] = j;
  479. #else
  480. for (i = XFI1, j = 1; i <= XFI8; i++, j++)
  481. xfi_dpmac[i] = j;
  482. for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
  483. sgmii_dpmac[i] = j;
  484. #endif
  485. #endif
  486. #ifdef CONFIG_SYS_FSL_SRDS_1
  487. serdes_init(FSL_SRDS_1,
  488. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
  489. FSL_CHASSIS3_SRDS1_REGSR,
  490. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  491. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
  492. serdes1_prtcl_map);
  493. #endif
  494. #ifdef CONFIG_SYS_FSL_SRDS_2
  495. serdes_init(FSL_SRDS_2,
  496. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
  497. FSL_CHASSIS3_SRDS2_REGSR,
  498. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  499. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
  500. serdes2_prtcl_map);
  501. #endif
  502. #ifdef CONFIG_SYS_NXP_SRDS_3
  503. serdes_init(NXP_SRDS_3,
  504. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
  505. FSL_CHASSIS3_SRDS3_REGSR,
  506. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  507. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
  508. serdes3_prtcl_map);
  509. #endif
  510. }
  511. int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
  512. {
  513. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  514. char scfg[16], snum[16];
  515. int cfgr = 0;
  516. u32 cfg;
  517. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  518. cfg >>= sd_prctl_shift;
  519. cfg = serdes_get_number(sd, cfg);
  520. #if defined(SRDS_BITS_PER_LANE)
  521. /*
  522. * reverse lanes, lane 0 should be printed first so it must be moved to
  523. * high order bits.
  524. * For example bb58 should read 85bb, lane 0 being protocol 8.
  525. * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
  526. * independent per-lane protocol configuration, at this time LS1028A and
  527. * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
  528. * lanes as a single value.
  529. */
  530. for (int i = 0; i < SRDS_MAX_LANES; i++) {
  531. int tmp;
  532. tmp = cfg >> (i * SRDS_BITS_PER_LANE);
  533. tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
  534. tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
  535. cfgr |= tmp;
  536. }
  537. #endif /* SRDS_BITS_PER_LANE */
  538. snprintf(snum, 16, "serdes%d", sd);
  539. snprintf(scfg, 16, "%x", cfgr);
  540. env_set(snum, scfg);
  541. return 0;
  542. }
  543. int serdes_misc_init(void)
  544. {
  545. #ifdef CONFIG_SYS_FSL_SRDS_1
  546. serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
  547. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  548. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
  549. #endif
  550. #ifdef CONFIG_SYS_FSL_SRDS_2
  551. serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
  552. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  553. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
  554. #endif
  555. #ifdef CONFIG_SYS_NXP_SRDS_3
  556. serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
  557. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  558. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
  559. #endif
  560. return 0;
  561. }