timer.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2011
  4. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  5. * Tom Cubie <tangliang@allwinnertech.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/timer.h>
  12. #include <linux/delay.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #define TIMER_MODE (0x0 << 7) /* continuous mode */
  15. #define TIMER_DIV (0x0 << 4) /* pre scale 1 */
  16. #define TIMER_SRC (0x1 << 2) /* osc24m */
  17. #define TIMER_RELOAD (0x1 << 1) /* reload internal value */
  18. #define TIMER_EN (0x1 << 0) /* enable timer */
  19. #define TIMER_CLOCK (24 * 1000 * 1000)
  20. #define COUNT_TO_USEC(x) ((x) / 24)
  21. #define USEC_TO_COUNT(x) ((x) * 24)
  22. #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
  23. #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
  24. #define TIMER_LOAD_VAL 0xffffffff
  25. #define TIMER_NUM 0 /* we use timer 0 */
  26. /* read the 32-bit timer */
  27. static ulong read_timer(void)
  28. {
  29. struct sunxi_timer_reg *timers =
  30. (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
  31. struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
  32. /*
  33. * The hardware timer counts down, therefore we invert to
  34. * produce an incrementing timer.
  35. */
  36. return ~readl(&timer->val);
  37. }
  38. /* init timer register */
  39. int timer_init(void)
  40. {
  41. struct sunxi_timer_reg *timers =
  42. (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
  43. struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
  44. writel(TIMER_LOAD_VAL, &timer->inter);
  45. writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
  46. &timer->ctl);
  47. return 0;
  48. }
  49. /* timer without interrupts */
  50. static ulong get_timer_masked(void)
  51. {
  52. /* current tick value */
  53. ulong now = TICKS_TO_HZ(read_timer());
  54. if (now >= gd->arch.lastinc) /* normal (non rollover) */
  55. gd->arch.tbl += (now - gd->arch.lastinc);
  56. else {
  57. /* rollover */
  58. gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
  59. - gd->arch.lastinc) + now;
  60. }
  61. gd->arch.lastinc = now;
  62. return gd->arch.tbl;
  63. }
  64. ulong get_timer(ulong base)
  65. {
  66. return get_timer_masked() - base;
  67. }
  68. /* delay x useconds */
  69. void __udelay(unsigned long usec)
  70. {
  71. long tmo = USEC_TO_COUNT(usec);
  72. ulong now, last = read_timer();
  73. while (tmo > 0) {
  74. now = read_timer();
  75. if (now > last) /* normal (non rollover) */
  76. tmo -= now - last;
  77. else /* rollover */
  78. tmo -= TIMER_LOAD_VAL - last + now;
  79. last = now;
  80. }
  81. }
  82. /*
  83. * This function is derived from PowerPC code (read timebase as long long).
  84. * On ARM it just returns the timer value.
  85. */
  86. unsigned long long get_ticks(void)
  87. {
  88. return get_timer(0);
  89. }
  90. /*
  91. * This function is derived from PowerPC code (timebase clock frequency).
  92. * On ARM it returns the number of timer ticks per second.
  93. */
  94. ulong get_tbclk(void)
  95. {
  96. return CONFIG_SYS_HZ;
  97. }