lowlevel_init.S 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
  4. */
  5. #include <config.h>
  6. #include <generated/asm-offsets.h>
  7. #include <asm/macro.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include "apf27.h"
  10. .macro init_aipi
  11. /*
  12. * setup AIPI1 and AIPI2
  13. */
  14. write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
  15. write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
  16. write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
  17. write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
  18. /* Change SDRAM signal strengh */
  19. ldr r0, =GPCR
  20. ldr r1, =ACFG_GPCR_VAL
  21. ldr r5, [r0]
  22. orr r5, r5, r1
  23. str r5, [r0]
  24. .endm /* init_aipi */
  25. .macro init_clock
  26. ldr r0, =CSCR
  27. /* disable MPLL/SPLL first */
  28. ldr r1, [r0]
  29. bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
  30. str r1, [r0]
  31. /*
  32. * pll clock initialization predefined in apf27.h
  33. */
  34. write32 MPCTL0, ACFG_MPCTL0_VAL
  35. write32 SPCTL0, ACFG_SPCTL0_VAL
  36. write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
  37. /*
  38. * add some delay here
  39. */
  40. mov r1, #0x1000
  41. 1: subs r1, r1, #0x1
  42. bne 1b
  43. /* peripheral clock divider */
  44. write32 PCDR0, ACFG_PCDR0_VAL
  45. write32 PCDR1, ACFG_PCDR1_VAL
  46. /* Configure PCCR0 and PCCR1 */
  47. write32 PCCR0, ACFG_PCCR0_VAL
  48. write32 PCCR1, ACFG_PCCR1_VAL
  49. .endm /* init_clock */
  50. .macro init_ddr
  51. /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
  52. ldr r0, =IMX_ESD_BASE
  53. ldr r4, =ESDMISC_SDRAM_RDY
  54. 2: ldr r1, [r0, #ESDMISC_ROF]
  55. ands r1, r1, r4
  56. bpl 2b
  57. /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
  58. ldr r0, =IMX_ESD_BASE
  59. ldr r4, =ACFG_ESDMISC_VAL
  60. orr r1, r4, #ESDMISC_MDDR_DL_RST
  61. str r1, [r0, #ESDMISC_ROF]
  62. /* Hold for more than 200ns */
  63. ldr r1, =0x10000
  64. 1: subs r1, r1, #0x1
  65. bne 1b
  66. str r4, [r0]
  67. ldr r0, =IMX_ESD_BASE
  68. ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
  69. str r1, [r0, #ESDCFG0_ROF]
  70. ldr r0, =IMX_ESD_BASE
  71. ldr r1, =ACFG_PRECHARGE_CMD
  72. str r1, [r0, #ESDCTL0_ROF]
  73. /* write8(0xA0001000, any value) */
  74. ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
  75. strb r2, [r1]
  76. ldr r1, =ACFG_AUTOREFRESH_CMD
  77. str r1, [r0, #ESDCTL0_ROF]
  78. ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
  79. ldr r6,=0x7 /* load loop counter */
  80. 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
  81. subs r6,r6,#1
  82. bne 1b
  83. ldr r1, =ACFG_SET_MODE_REG_CMD
  84. str r1, [r0, #ESDCTL0_ROF]
  85. /* set standard mode register */
  86. ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
  87. strb r2, [r4]
  88. /* set extended mode register */
  89. ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
  90. strb r5, [r4]
  91. ldr r1, =ACFG_NORMAL_RW_CMD
  92. str r1, [r0, #ESDCTL0_ROF]
  93. /* 2nd sdram */
  94. ldr r0, =IMX_ESD_BASE
  95. ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
  96. str r1, [r0, #ESDCFG1_ROF]
  97. ldr r0, =IMX_ESD_BASE
  98. ldr r1, =ACFG_PRECHARGE_CMD
  99. str r1, [r0, #ESDCTL1_ROF]
  100. /* write8(0xB0001000, any value) */
  101. ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
  102. strb r2, [r1]
  103. ldr r1, =ACFG_AUTOREFRESH_CMD
  104. str r1, [r0, #ESDCTL1_ROF]
  105. ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
  106. ldr r6,=0x7 /* load loop counter */
  107. 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
  108. subs r6,r6,#1
  109. bne 1b
  110. ldr r1, =ACFG_SET_MODE_REG_CMD
  111. str r1, [r0, #ESDCTL1_ROF]
  112. /* set standard mode register */
  113. ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
  114. strb r2, [r4]
  115. /* set extended mode register */
  116. ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
  117. strb r2, [r4]
  118. ldr r1, =ACFG_NORMAL_RW_CMD
  119. str r1, [r0, #ESDCTL1_ROF]
  120. .endm /* init_ddr */
  121. .globl lowlevel_init
  122. lowlevel_init:
  123. init_aipi
  124. init_clock
  125. #ifdef CONFIG_SPL_BUILD
  126. init_ddr
  127. #endif
  128. mov pc, lr