fpga.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002-2013
  4. * Eric Jarrige <eric.jarrige@armadeus.org>
  5. *
  6. * based on the files by
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com
  8. * and
  9. * Keith Outwater, keith_outwater@mvis.com
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <linux/delay.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <command.h>
  18. #include <config.h>
  19. #include "fpga.h"
  20. #include <spartan3.h>
  21. #include "apf27.h"
  22. /*
  23. * Note that these are pointers to code that is in Flash. They will be
  24. * relocated at runtime.
  25. * Spartan2 code is used to download our Spartan 3 :) code is compatible.
  26. * Just take care about the file size
  27. */
  28. xilinx_spartan3_slave_parallel_fns fpga_fns = {
  29. fpga_pre_fn,
  30. fpga_pgm_fn,
  31. fpga_init_fn,
  32. NULL,
  33. fpga_done_fn,
  34. fpga_clk_fn,
  35. fpga_cs_fn,
  36. fpga_wr_fn,
  37. fpga_rdata_fn,
  38. fpga_wdata_fn,
  39. fpga_busy_fn,
  40. fpga_abort_fn,
  41. fpga_post_fn,
  42. };
  43. xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  44. {xilinx_spartan3,
  45. slave_parallel,
  46. 1196128l/8,
  47. (void *)&fpga_fns,
  48. 0,
  49. &spartan3_op,
  50. "3s200aft256"}
  51. };
  52. /*
  53. * Initialize GPIO port B before download
  54. */
  55. int fpga_pre_fn(int cookie)
  56. {
  57. /* Initialize GPIO pins */
  58. gpio_set_value(ACFG_FPGA_PWR, 1);
  59. imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
  60. imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
  61. imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  62. imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  63. imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  64. imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  65. imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
  66. gpio_set_value(ACFG_FPGA_RESET, 1);
  67. imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  68. imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  69. gpio_set_value(ACFG_FPGA_PRG, 1);
  70. gpio_set_value(ACFG_FPGA_CLK, 1);
  71. gpio_set_value(ACFG_FPGA_RW, 1);
  72. gpio_set_value(ACFG_FPGA_CS, 1);
  73. gpio_set_value(ACFG_FPGA_SUSPEND, 0);
  74. gpio_set_value(ACFG_FPGA_PWR, 0);
  75. udelay(30000); /*wait until supply started*/
  76. return cookie;
  77. }
  78. /*
  79. * Set the FPGA's active-low program line to the specified level
  80. */
  81. int fpga_pgm_fn(int assert, int flush, int cookie)
  82. {
  83. debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
  84. assert ? "high" : "low");
  85. gpio_set_value(ACFG_FPGA_PRG, !assert);
  86. return assert;
  87. }
  88. /*
  89. * Set the FPGA's active-high clock line to the specified level
  90. */
  91. int fpga_clk_fn(int assert_clk, int flush, int cookie)
  92. {
  93. debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
  94. assert_clk ? "high" : "low");
  95. gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
  96. return assert_clk;
  97. }
  98. /*
  99. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  100. * asserted (low).
  101. */
  102. int fpga_init_fn(int cookie)
  103. {
  104. int value;
  105. debug("%s:%d: INIT check... ", __func__, __LINE__);
  106. value = gpio_get_value(ACFG_FPGA_INIT);
  107. /* printf("init value read %x",value); */
  108. #ifdef CONFIG_SYS_FPGA_IS_PROTO
  109. return value;
  110. #else
  111. return !value;
  112. #endif
  113. }
  114. /*
  115. * Test the state of the active-high FPGA DONE pin
  116. */
  117. int fpga_done_fn(int cookie)
  118. {
  119. debug("%s:%d: DONE check... %s", __func__, __LINE__,
  120. gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
  121. return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
  122. }
  123. /*
  124. * Set the FPGA's wr line to the specified level
  125. */
  126. int fpga_wr_fn(int assert_write, int flush, int cookie)
  127. {
  128. debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
  129. assert_write ? "high" : "low");
  130. gpio_set_value(ACFG_FPGA_RW, !assert_write);
  131. return assert_write;
  132. }
  133. int fpga_cs_fn(int assert_cs, int flush, int cookie)
  134. {
  135. debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
  136. assert_cs ? "high" : "low");
  137. gpio_set_value(ACFG_FPGA_CS, !assert_cs);
  138. return assert_cs;
  139. }
  140. int fpga_rdata_fn(unsigned char *data, int cookie)
  141. {
  142. debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
  143. *((char *)ACFG_FPGA_RDATA));
  144. *data = (unsigned char)
  145. ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
  146. return *data;
  147. }
  148. int fpga_wdata_fn(unsigned char data, int flush, int cookie)
  149. {
  150. debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
  151. data);
  152. *((unsigned short *)ACFG_FPGA_WDATA) = data;
  153. return data;
  154. }
  155. int fpga_abort_fn(int cookie)
  156. {
  157. return fpga_post_fn(cookie);
  158. }
  159. int fpga_busy_fn(int cookie)
  160. {
  161. return 1;
  162. }
  163. int fpga_post_fn(int cookie)
  164. {
  165. debug("%s:%d: FPGA POST ", __func__, __LINE__);
  166. imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
  167. imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
  168. imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
  169. gpio_set_value(ACFG_FPGA_PRG, 1);
  170. gpio_set_value(ACFG_FPGA_RESET, 0);
  171. imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  172. return cookie;
  173. }
  174. void apf27_fpga_setup(void)
  175. {
  176. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  177. struct system_control_regs *system =
  178. (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
  179. /* Configure FPGA CLKO */
  180. writel(ACFG_CCSR_VAL, &pll->ccsr);
  181. /* Configure strentgh for FPGA */
  182. writel(ACFG_DSCR10_VAL, &system->dscr10);
  183. writel(ACFG_DSCR3_VAL, &system->dscr3);
  184. writel(ACFG_DSCR7_VAL, &system->dscr7);
  185. writel(ACFG_DSCR2_VAL, &system->dscr2);
  186. }
  187. /*
  188. * Initialize the fpga. Return 1 on success, 0 on failure.
  189. */
  190. void APF27_init_fpga(void)
  191. {
  192. int i;
  193. apf27_fpga_setup();
  194. fpga_init();
  195. for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
  196. debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
  197. fpga_add(fpga_xilinx, &fpga[i]);
  198. }
  199. return;
  200. }