apf27.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
  4. */
  5. #ifndef __APF27_H
  6. #define __APF27_H
  7. /* FPGA program pin configuration */
  8. #define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
  9. #define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
  10. #define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
  11. #define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */
  12. #define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */
  13. #define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
  14. #define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
  15. #define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
  16. #define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
  17. #define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
  18. #define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
  19. /* MMC pin */
  20. #define PC_PWRON (GPIO_PORTF | 16)
  21. /*
  22. * MPU CLOCK source before PLL
  23. * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
  24. */
  25. #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
  26. #define ACFG_MPCTL1_VAL 0
  27. #define CONFIG_MPLL_FREQ 399
  28. #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
  29. /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
  30. #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
  31. #define ACFG_SPCTL1_VAL 0
  32. #define CONFIG_SPLL_FREQ 300 /* MHz */
  33. /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
  34. #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
  35. /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
  36. #define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */
  37. #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
  38. #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
  39. #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
  40. #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
  41. #define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */
  42. #define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */
  43. #define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */
  44. #define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */
  45. #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
  46. #define CONFIG_CLK0_EN 1 /* CLK0 enabled */
  47. /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
  48. #define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */
  49. /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
  50. #define CONFIG_USB_FREQ 60 /* 60 MHz */
  51. /*
  52. * SDRAM
  53. */
  54. #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
  55. /* micron 64MB */
  56. #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
  57. * column address bits
  58. */
  59. #define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13
  60. * row address bits
  61. */
  62. #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
  63. * 2=4096 3=8192 refresh
  64. */
  65. #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
  66. * down delay
  67. */
  68. #define ACFG_SDRAM_W2R_DELAY 1 /* write to read
  69. * cycle delay > 0
  70. */
  71. #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
  72. #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
  73. * cycle delay 1..4
  74. */
  75. #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
  76. * SDRAM: 0=1ck 1=2ck
  77. */
  78. #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
  79. #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
  80. #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
  81. #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
  82. * refresh to command)
  83. */
  84. #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
  85. * estimated fo CL=1
  86. * 0=force 3 for lpddr
  87. */
  88. #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
  89. * 3=Eighth 4=Sixteenth
  90. */
  91. #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
  92. * 2=quater 3=Eighth
  93. */
  94. #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
  95. #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
  96. * 0 = Burst mode
  97. */
  98. #endif
  99. #if (ACFG_SDRAM_MBYTE_SYZE == 128)
  100. /* micron 128MB */
  101. #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
  102. * column address bits
  103. */
  104. #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
  105. * row address bits
  106. */
  107. #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
  108. * 2=4096 3=8192 refresh
  109. */
  110. #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
  111. * down delay
  112. */
  113. #define ACFG_SDRAM_W2R_DELAY 1 /* write to read
  114. * cycle delay > 0
  115. */
  116. #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
  117. #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
  118. * cycle delay 1..4
  119. */
  120. #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
  121. * SDRAM: 0=1ck 1=2ck
  122. */
  123. #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
  124. #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
  125. #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
  126. #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
  127. * refresh to command)
  128. */
  129. #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
  130. * estimated fo CL=1
  131. * 0=force 3 for lpddr
  132. */
  133. #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
  134. * 3=Eighth 4=Sixteenth
  135. */
  136. #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
  137. * 2=quater 3=Eighth
  138. */
  139. #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
  140. #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
  141. * 0 = Burst mode
  142. */
  143. #endif
  144. #if (ACFG_SDRAM_MBYTE_SYZE == 256)
  145. /* micron 256MB */
  146. #define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11
  147. * column address bits
  148. */
  149. #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
  150. * row address bits
  151. */
  152. #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
  153. * 2=4096 3=8192 refresh
  154. */
  155. #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
  156. * down delay
  157. */
  158. #define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle
  159. * delay > 0
  160. */
  161. #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
  162. #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
  163. * cycle delay 1..4
  164. */
  165. #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
  166. * SDRAM: 0=1ck 1=2ck
  167. */
  168. #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
  169. #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
  170. #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
  171. #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
  172. * refresh to command)
  173. */
  174. #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
  175. * estimated fo CL=1
  176. * 0=force 3 for lpddr
  177. */
  178. #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
  179. * 3=Eighth 4=Sixteenth
  180. */
  181. #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength
  182. * 1=half
  183. * 2=quater
  184. * 3=Eighth
  185. */
  186. #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
  187. #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
  188. * 0 = Burst mode
  189. */
  190. #endif
  191. /*
  192. * External interface
  193. */
  194. /*
  195. * CSCRxU_VAL:
  196. * 31| x | x | x x |x x x x| x x | x | x |x x x x|16
  197. * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
  198. *
  199. * 15| x x | x x x x x x | x | x x x x | x x x x |0
  200. * | CNC | WSC |EW | WWS | EDC |
  201. *
  202. * CSCRxL_VAL:
  203. * 31| x x x x | x x x x | x x x x | x x x x |16
  204. * | OEA | OEN | EBWA | EBWN |
  205. * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0
  206. * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN|
  207. *
  208. * CSCRxA_VAL:
  209. * 31| x x x x | x x x x | x x x x | x x x x |16
  210. * | EBRA | EBRN | RWA | RWN |
  211. * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0
  212. * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
  213. */
  214. /* CS0 configuration for 16 bit nor flash */
  215. #define ACFG_CS0U_VAL 0x0000CC03
  216. #define ACFG_CS0L_VAL 0xa0330D01
  217. #define ACFG_CS0A_VAL 0x00220800
  218. #define ACFG_CS1U_VAL 0x00000f00
  219. #define ACFG_CS1L_VAL 0x00000D01
  220. #define ACFG_CS1A_VAL 0
  221. #define ACFG_CS2U_VAL 0
  222. #define ACFG_CS2L_VAL 0
  223. #define ACFG_CS2A_VAL 0
  224. #define ACFG_CS3U_VAL 0
  225. #define ACFG_CS3L_VAL 0
  226. #define ACFG_CS3A_VAL 0
  227. #define ACFG_CS4U_VAL 0
  228. #define ACFG_CS4L_VAL 0
  229. #define ACFG_CS4A_VAL 0
  230. /* FPGA 16 bit data bus */
  231. #define ACFG_CS5U_VAL 0x00000600
  232. #define ACFG_CS5L_VAL 0x00000D01
  233. #define ACFG_CS5A_VAL 0
  234. #define ACFG_EIM_VAL 0x00002200
  235. /*
  236. * FPGA specific settings
  237. */
  238. /* CLKO */
  239. #define ACFG_CCSR_VAL 0x00000305
  240. /* drive strength CLKO set to 2 */
  241. #define ACFG_DSCR10_VAL 0x00020000
  242. /* drive strength A1..A12 set to 2 */
  243. #define ACFG_DSCR3_VAL 0x02AAAAA8
  244. /* drive strength ctrl */
  245. #define ACFG_DSCR7_VAL 0x00020880
  246. /* drive strength data */
  247. #define ACFG_DSCR2_VAL 0xAAAAAAAA
  248. /*
  249. * Default configuration for GPIOs and peripherals
  250. */
  251. #define ACFG_DDIR_A_VAL 0x00000000
  252. #define ACFG_OCR1_A_VAL 0x00000000
  253. #define ACFG_OCR2_A_VAL 0x00000000
  254. #define ACFG_ICFA1_A_VAL 0xFFFFFFFF
  255. #define ACFG_ICFA2_A_VAL 0xFFFFFFFF
  256. #define ACFG_ICFB1_A_VAL 0xFFFFFFFF
  257. #define ACFG_ICFB2_A_VAL 0xFFFFFFFF
  258. #define ACFG_DR_A_VAL 0x00000000
  259. #define ACFG_GIUS_A_VAL 0xFFFFFFFF
  260. #define ACFG_ICR1_A_VAL 0x00000000
  261. #define ACFG_ICR2_A_VAL 0x00000000
  262. #define ACFG_IMR_A_VAL 0x00000000
  263. #define ACFG_GPR_A_VAL 0x00000000
  264. #define ACFG_PUEN_A_VAL 0xFFFFFFFF
  265. #define ACFG_DDIR_B_VAL 0x00000000
  266. #define ACFG_OCR1_B_VAL 0x00000000
  267. #define ACFG_OCR2_B_VAL 0x00000000
  268. #define ACFG_ICFA1_B_VAL 0xFFFFFFFF
  269. #define ACFG_ICFA2_B_VAL 0xFFFFFFFF
  270. #define ACFG_ICFB1_B_VAL 0xFFFFFFFF
  271. #define ACFG_ICFB2_B_VAL 0xFFFFFFFF
  272. #define ACFG_DR_B_VAL 0x00000000
  273. #define ACFG_GIUS_B_VAL 0xFF3FFFF0
  274. #define ACFG_ICR1_B_VAL 0x00000000
  275. #define ACFG_ICR2_B_VAL 0x00000000
  276. #define ACFG_IMR_B_VAL 0x00000000
  277. #define ACFG_GPR_B_VAL 0x00000000
  278. #define ACFG_PUEN_B_VAL 0xFFFFFFFF
  279. #define ACFG_DDIR_C_VAL 0x00000000
  280. #define ACFG_OCR1_C_VAL 0x00000000
  281. #define ACFG_OCR2_C_VAL 0x00000000
  282. #define ACFG_ICFA1_C_VAL 0xFFFFFFFF
  283. #define ACFG_ICFA2_C_VAL 0xFFFFFFFF
  284. #define ACFG_ICFB1_C_VAL 0xFFFFFFFF
  285. #define ACFG_ICFB2_C_VAL 0xFFFFFFFF
  286. #define ACFG_DR_C_VAL 0x00000000
  287. #define ACFG_GIUS_C_VAL 0xFFFFC07F
  288. #define ACFG_ICR1_C_VAL 0x00000000
  289. #define ACFG_ICR2_C_VAL 0x00000000
  290. #define ACFG_IMR_C_VAL 0x00000000
  291. #define ACFG_GPR_C_VAL 0x00000000
  292. #define ACFG_PUEN_C_VAL 0xFFFFFF87
  293. #define ACFG_DDIR_D_VAL 0x00000000
  294. #define ACFG_OCR1_D_VAL 0x00000000
  295. #define ACFG_OCR2_D_VAL 0x00000000
  296. #define ACFG_ICFA1_D_VAL 0xFFFFFFFF
  297. #define ACFG_ICFA2_D_VAL 0xFFFFFFFF
  298. #define ACFG_ICFB1_D_VAL 0xFFFFFFFF
  299. #define ACFG_ICFB2_D_VAL 0xFFFFFFFF
  300. #define ACFG_DR_D_VAL 0x00000000
  301. #define ACFG_GIUS_D_VAL 0xFFFFFFFF
  302. #define ACFG_ICR1_D_VAL 0x00000000
  303. #define ACFG_ICR2_D_VAL 0x00000000
  304. #define ACFG_IMR_D_VAL 0x00000000
  305. #define ACFG_GPR_D_VAL 0x00000000
  306. #define ACFG_PUEN_D_VAL 0xFFFFFFFF
  307. #define ACFG_DDIR_E_VAL 0x00000000
  308. #define ACFG_OCR1_E_VAL 0x00000000
  309. #define ACFG_OCR2_E_VAL 0x00000000
  310. #define ACFG_ICFA1_E_VAL 0xFFFFFFFF
  311. #define ACFG_ICFA2_E_VAL 0xFFFFFFFF
  312. #define ACFG_ICFB1_E_VAL 0xFFFFFFFF
  313. #define ACFG_ICFB2_E_VAL 0xFFFFFFFF
  314. #define ACFG_DR_E_VAL 0x00000000
  315. #define ACFG_GIUS_E_VAL 0xFCFFCCF8
  316. #define ACFG_ICR1_E_VAL 0x00000000
  317. #define ACFG_ICR2_E_VAL 0x00000000
  318. #define ACFG_IMR_E_VAL 0x00000000
  319. #define ACFG_GPR_E_VAL 0x00000000
  320. #define ACFG_PUEN_E_VAL 0xFFFFFFFF
  321. #define ACFG_DDIR_F_VAL 0x00000000
  322. #define ACFG_OCR1_F_VAL 0x00000000
  323. #define ACFG_OCR2_F_VAL 0x00000000
  324. #define ACFG_ICFA1_F_VAL 0xFFFFFFFF
  325. #define ACFG_ICFA2_F_VAL 0xFFFFFFFF
  326. #define ACFG_ICFB1_F_VAL 0xFFFFFFFF
  327. #define ACFG_ICFB2_F_VAL 0xFFFFFFFF
  328. #define ACFG_DR_F_VAL 0x00000000
  329. #define ACFG_GIUS_F_VAL 0xFF7F8000
  330. #define ACFG_ICR1_F_VAL 0x00000000
  331. #define ACFG_ICR2_F_VAL 0x00000000
  332. #define ACFG_IMR_F_VAL 0x00000000
  333. #define ACFG_GPR_F_VAL 0x00000000
  334. #define ACFG_PUEN_F_VAL 0xFFFFFFFF
  335. /* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
  336. #define ACFG_GPCR_VAL 0x0003000F
  337. #define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
  338. /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
  339. #if (CONFIG_NR_DRAM_BANKS == 1)
  340. #define ACFG_FMCR_VAL 0xFFFFFFF9
  341. #elif (CONFIG_NR_DRAM_BANKS == 2)
  342. #define ACFG_FMCR_VAL 0xFFFFFFFB
  343. #endif
  344. #define ACFG_AIPI1_PSR0_VAL 0x20040304
  345. #define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB
  346. #define ACFG_AIPI2_PSR0_VAL 0x00000000
  347. #define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF
  348. /* PCCR enable DMA FEC I2C1 IIM SDHC1 */
  349. #define ACFG_PCCR0_VAL 0x05070410
  350. #define ACFG_PCCR1_VAL 0xA14A0608
  351. /*
  352. * From here, there should not be any user configuration.
  353. * All Equations are automatic
  354. */
  355. /* fixme none integer value (7.5ns) => 2*hclock = 15ns */
  356. #define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
  357. /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
  358. #define CSCR_MASK 0x0300800D
  359. #define ACFG_CSCR_VAL \
  360. (CSCR_MASK \
  361. |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \
  362. |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \
  363. |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
  364. /* SSIx CLKO NFC H264 MSHC */
  365. #define ACFG_PCDR0_VAL\
  366. (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \
  367. |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \
  368. |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
  369. |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
  370. |(((CONFIG_CLK0_DIV)&0x07)<<22)\
  371. |(((CONFIG_CLK0_EN)&0x01)<<25)\
  372. |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
  373. /* PERCLKx */
  374. #define ACFG_PCDR1_VAL\
  375. (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \
  376. |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \
  377. |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \
  378. |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
  379. /* SDRAM controller programming Values */
  380. #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
  381. (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
  382. #define REG_FIELD_SCL_VAL 3
  383. #define REG_FIELD_SCLIMX_VAL 0
  384. #else
  385. #define REG_FIELD_SCL_VAL\
  386. ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
  387. ACFG_2XHCLK_LGTH)
  388. #define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
  389. #endif
  390. #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
  391. #define REG_FIELD_SRC_VAL 0
  392. #else
  393. #define REG_FIELD_SRC_VAL\
  394. ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
  395. ACFG_2XHCLK_LGTH)
  396. #endif
  397. /* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
  398. #define REG_ESDCTL_BASE_CONFIG (0x80020485\
  399. | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
  400. | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
  401. | (((ACFG_SDRAM_REFRESH)&0x7)<<13))
  402. #define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
  403. #define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
  404. #define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
  405. #define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
  406. /* ESDRAMC Configuration Registers : force CL=3 to lpddr */
  407. #define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\
  408. | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
  409. ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
  410. | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
  411. | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
  412. ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
  413. | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
  414. | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\
  415. | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
  416. ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
  417. | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
  418. ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
  419. | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
  420. | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
  421. ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \
  422. | (((REG_FIELD_SRC_VAL)&0x0F)<<0))
  423. /* Issue Mode register Command to SDRAM */
  424. #define ACFG_SDRAM_MODE_REGISTER_VAL\
  425. ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
  426. | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
  427. | ((0)<<(3)) /* sequentiql access */ \
  428. /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
  429. /* Issue Extended Mode register Command to SDRAM */
  430. #define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\
  431. ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\
  432. | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\
  433. | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))
  434. /* Issue Precharge all Command to SDRAM */
  435. #define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
  436. #endif /* __APF27_H */