rk_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * spi driver for rockchip
  4. *
  5. * (C) 2019 Theobroma Systems Design und Consulting GmbH
  6. *
  7. * (C) Copyright 2015 Google, Inc
  8. *
  9. * (C) Copyright 2008-2013 Rockchip Electronics
  10. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  11. */
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <dt-structs.h>
  16. #include <errno.h>
  17. #include <log.h>
  18. #include <spi.h>
  19. #include <time.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <asm/io.h>
  23. #include <asm/arch-rockchip/clock.h>
  24. #include <asm/arch-rockchip/periph.h>
  25. #include <dm/pinctrl.h>
  26. #include "rk_spi.h"
  27. /* Change to 1 to output registers at the start of each transaction */
  28. #define DEBUG_RK_SPI 0
  29. /*
  30. * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
  31. * the controller seems to hang when given 0x10000, so stick with this for now.
  32. */
  33. #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
  34. struct rockchip_spi_params {
  35. /* RXFIFO overruns and TXFIFO underruns stop the master clock */
  36. bool master_manages_fifo;
  37. };
  38. struct rockchip_spi_plat {
  39. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  40. struct dtd_rockchip_rk3288_spi of_plat;
  41. #endif
  42. s32 frequency; /* Default clock frequency, -1 for none */
  43. fdt_addr_t base;
  44. uint deactivate_delay_us; /* Delay to wait after deactivate */
  45. uint activate_delay_us; /* Delay to wait after activate */
  46. };
  47. struct rockchip_spi_priv {
  48. struct rockchip_spi *regs;
  49. struct clk clk;
  50. unsigned int max_freq;
  51. unsigned int mode;
  52. ulong last_transaction_us; /* Time of last transaction end */
  53. unsigned int speed_hz;
  54. unsigned int last_speed_hz;
  55. uint input_rate;
  56. };
  57. #define SPI_FIFO_DEPTH 32
  58. static void rkspi_dump_regs(struct rockchip_spi *regs)
  59. {
  60. debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  61. debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  62. debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  63. debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  64. debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  65. debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  66. debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  67. debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  68. debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  69. debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  70. debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  71. debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  72. debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  73. debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  74. debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  75. }
  76. static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  77. {
  78. writel(enable ? 1 : 0, &regs->enr);
  79. }
  80. static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  81. {
  82. /*
  83. * We should try not to exceed the speed requested by the caller:
  84. * when selecting a divider, we need to make sure we round up.
  85. */
  86. uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  87. /* The baudrate register (BAUDR) is defined as a 32bit register where
  88. * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  89. * 16bits with 'Fsclk_out' defined as follows:
  90. *
  91. * Fsclk_out = Fspi_clk/ SCKDV
  92. * Where SCKDV is any even value between 2 and 65534.
  93. */
  94. if (clk_div > 0xfffe) {
  95. clk_div = 0xfffe;
  96. debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
  97. __func__, speed, priv->input_rate / clk_div);
  98. }
  99. /* Round up to the next even 16bit number */
  100. clk_div = (clk_div + 1) & 0xfffe;
  101. debug("spi speed %u, div %u\n", speed, clk_div);
  102. clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
  103. priv->last_speed_hz = speed;
  104. }
  105. static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  106. {
  107. unsigned long start;
  108. start = get_timer(0);
  109. while (readl(&regs->sr) & SR_BUSY) {
  110. if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  111. debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  112. return -ETIMEDOUT;
  113. }
  114. }
  115. return 0;
  116. }
  117. static void spi_cs_activate(struct udevice *dev, uint cs)
  118. {
  119. struct udevice *bus = dev->parent;
  120. struct rockchip_spi_plat *plat = dev_get_plat(bus);
  121. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  122. struct rockchip_spi *regs = priv->regs;
  123. /* If it's too soon to do another transaction, wait */
  124. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  125. ulong delay_us; /* The delay completed so far */
  126. delay_us = timer_get_us() - priv->last_transaction_us;
  127. if (delay_us < plat->deactivate_delay_us) {
  128. ulong additional_delay_us =
  129. plat->deactivate_delay_us - delay_us;
  130. debug("%s: delaying by %ld us\n",
  131. __func__, additional_delay_us);
  132. udelay(additional_delay_us);
  133. }
  134. }
  135. debug("activate cs%u\n", cs);
  136. writel(1 << cs, &regs->ser);
  137. if (plat->activate_delay_us)
  138. udelay(plat->activate_delay_us);
  139. }
  140. static void spi_cs_deactivate(struct udevice *dev, uint cs)
  141. {
  142. struct udevice *bus = dev->parent;
  143. struct rockchip_spi_plat *plat = dev_get_plat(bus);
  144. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  145. struct rockchip_spi *regs = priv->regs;
  146. debug("deactivate cs%u\n", cs);
  147. writel(0, &regs->ser);
  148. /* Remember time of this transaction so we can honour the bus delay */
  149. if (plat->deactivate_delay_us)
  150. priv->last_transaction_us = timer_get_us();
  151. }
  152. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  153. static int conv_of_plat(struct udevice *dev)
  154. {
  155. struct rockchip_spi_plat *plat = dev_get_plat(dev);
  156. struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
  157. struct rockchip_spi_priv *priv = dev_get_priv(dev);
  158. int ret;
  159. plat->base = dtplat->reg[0];
  160. plat->frequency = 20000000;
  161. ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
  162. if (ret < 0)
  163. return ret;
  164. return 0;
  165. }
  166. #endif
  167. static int rockchip_spi_of_to_plat(struct udevice *bus)
  168. {
  169. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  170. struct rockchip_spi_plat *plat = dev_get_plat(bus);
  171. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  172. int ret;
  173. plat->base = dev_read_addr(bus);
  174. ret = clk_get_by_index(bus, 0, &priv->clk);
  175. if (ret < 0) {
  176. debug("%s: Could not get clock for %s: %d\n", __func__,
  177. bus->name, ret);
  178. return ret;
  179. }
  180. plat->frequency =
  181. dev_read_u32_default(bus, "spi-max-frequency", 50000000);
  182. plat->deactivate_delay_us =
  183. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  184. plat->activate_delay_us =
  185. dev_read_u32_default(bus, "spi-activate-delay", 0);
  186. debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  187. __func__, (uint)plat->base, plat->frequency,
  188. plat->deactivate_delay_us);
  189. #endif
  190. return 0;
  191. }
  192. static int rockchip_spi_calc_modclk(ulong max_freq)
  193. {
  194. /*
  195. * While this is not strictly correct for the RK3368, as the
  196. * GPLL will be 576MHz, things will still work, as the
  197. * clk_set_rate(...) implementation in our clock-driver will
  198. * chose the next closest rate not exceeding what we request
  199. * based on the output of this function.
  200. */
  201. unsigned div;
  202. const unsigned long gpll_hz = 594000000UL;
  203. /*
  204. * We need to find an input clock that provides at least twice
  205. * the maximum frequency and can be generated from the assumed
  206. * speed of GPLL (594MHz) using an integer divider.
  207. *
  208. * To give us more achievable bitrates at higher speeds (these
  209. * are generated by dividing by an even 16-bit integer from
  210. * this frequency), we try to have an input frequency of at
  211. * least 4x our max_freq.
  212. */
  213. div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
  214. return gpll_hz / div;
  215. }
  216. static int rockchip_spi_probe(struct udevice *bus)
  217. {
  218. struct rockchip_spi_plat *plat = dev_get_plat(bus);
  219. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  220. int ret;
  221. debug("%s: probe\n", __func__);
  222. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  223. ret = conv_of_plat(bus);
  224. if (ret)
  225. return ret;
  226. #endif
  227. priv->regs = (struct rockchip_spi *)plat->base;
  228. priv->last_transaction_us = timer_get_us();
  229. priv->max_freq = plat->frequency;
  230. /* Clamp the value from the DTS against any hardware limits */
  231. if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
  232. priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
  233. /* Find a module-input clock that fits with the max_freq setting */
  234. ret = clk_set_rate(&priv->clk,
  235. rockchip_spi_calc_modclk(priv->max_freq));
  236. if (ret < 0) {
  237. debug("%s: Failed to set clock: %d\n", __func__, ret);
  238. return ret;
  239. }
  240. priv->input_rate = ret;
  241. debug("%s: rate = %u\n", __func__, priv->input_rate);
  242. return 0;
  243. }
  244. static int rockchip_spi_claim_bus(struct udevice *dev)
  245. {
  246. struct udevice *bus = dev->parent;
  247. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  248. struct rockchip_spi *regs = priv->regs;
  249. uint ctrlr0;
  250. /* Disable the SPI hardware */
  251. rkspi_enable_chip(regs, false);
  252. if (priv->speed_hz != priv->last_speed_hz)
  253. rkspi_set_clk(priv, priv->speed_hz);
  254. /* Operation Mode */
  255. ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
  256. /* Data Frame Size */
  257. ctrlr0 |= DFS_8BIT << DFS_SHIFT;
  258. /* set SPI mode 0..3 */
  259. if (priv->mode & SPI_CPOL)
  260. ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
  261. if (priv->mode & SPI_CPHA)
  262. ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
  263. /* Chip Select Mode */
  264. ctrlr0 |= CSM_KEEP << CSM_SHIFT;
  265. /* SSN to Sclk_out delay */
  266. ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
  267. /* Serial Endian Mode */
  268. ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
  269. /* First Bit Mode */
  270. ctrlr0 |= FBM_MSB << FBM_SHIFT;
  271. /* Byte and Halfword Transform */
  272. ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
  273. /* Rxd Sample Delay */
  274. ctrlr0 |= 0 << RXDSD_SHIFT;
  275. /* Frame Format */
  276. ctrlr0 |= FRF_SPI << FRF_SHIFT;
  277. /* Tx and Rx mode */
  278. ctrlr0 |= TMOD_TR << TMOD_SHIFT;
  279. writel(ctrlr0, &regs->ctrlr0);
  280. return 0;
  281. }
  282. static int rockchip_spi_release_bus(struct udevice *dev)
  283. {
  284. struct udevice *bus = dev->parent;
  285. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  286. rkspi_enable_chip(priv->regs, false);
  287. return 0;
  288. }
  289. static inline int rockchip_spi_16bit_reader(struct udevice *dev,
  290. u8 **din, int *len)
  291. {
  292. struct udevice *bus = dev->parent;
  293. const struct rockchip_spi_params * const data =
  294. (void *)dev_get_driver_data(bus);
  295. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  296. struct rockchip_spi *regs = priv->regs;
  297. const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
  298. #if defined(DEBUG)
  299. u32 statistics_rxlevels[33] = { };
  300. #endif
  301. u32 frames = *len / 2;
  302. u8 *in = (u8 *)(*din);
  303. u32 max_chunk_size = SPI_FIFO_DEPTH;
  304. if (!frames)
  305. return 0;
  306. /*
  307. * If we know that the hardware will manage RXFIFO overruns
  308. * (i.e. stop the SPI clock until there's space in the FIFO),
  309. * we the allow largest possible chunk size that can be
  310. * represented in CTRLR1.
  311. */
  312. if (data && data->master_manages_fifo)
  313. max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
  314. // rockchip_spi_configure(dev, mode, size)
  315. rkspi_enable_chip(regs, false);
  316. clrsetbits_le32(&regs->ctrlr0,
  317. TMOD_MASK << TMOD_SHIFT,
  318. TMOD_RO << TMOD_SHIFT);
  319. /* 16bit data frame size */
  320. clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
  321. /* Update caller's context */
  322. const u32 bytes_to_process = 2 * frames;
  323. *din += bytes_to_process;
  324. *len -= bytes_to_process;
  325. /* Process our frames */
  326. while (frames) {
  327. u32 chunk_size = min(frames, max_chunk_size);
  328. frames -= chunk_size;
  329. writew(chunk_size - 1, &regs->ctrlr1);
  330. rkspi_enable_chip(regs, true);
  331. do {
  332. u32 rx_level = readw(&regs->rxflr);
  333. #if defined(DEBUG)
  334. statistics_rxlevels[rx_level]++;
  335. #endif
  336. chunk_size -= rx_level;
  337. while (rx_level--) {
  338. u16 val = readw(regs->rxdr);
  339. *in++ = val & 0xff;
  340. *in++ = val >> 8;
  341. }
  342. } while (chunk_size);
  343. rkspi_enable_chip(regs, false);
  344. }
  345. #if defined(DEBUG)
  346. debug("%s: observed rx_level during processing:\n", __func__);
  347. for (int i = 0; i <= 32; ++i)
  348. if (statistics_rxlevels[i])
  349. debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
  350. #endif
  351. /* Restore the original transfer setup and return error-free. */
  352. writel(saved_ctrlr0, &regs->ctrlr0);
  353. return 0;
  354. }
  355. static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
  356. const void *dout, void *din, unsigned long flags)
  357. {
  358. struct udevice *bus = dev->parent;
  359. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  360. struct rockchip_spi *regs = priv->regs;
  361. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  362. int len = bitlen >> 3;
  363. const u8 *out = dout;
  364. u8 *in = din;
  365. int toread, towrite;
  366. int ret = 0;
  367. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  368. len, flags);
  369. if (DEBUG_RK_SPI)
  370. rkspi_dump_regs(regs);
  371. /* Assert CS before transfer */
  372. if (flags & SPI_XFER_BEGIN)
  373. spi_cs_activate(dev, slave_plat->cs);
  374. /*
  375. * To ensure fast loading of firmware images (e.g. full U-Boot
  376. * stage, ATF, Linux kernel) from SPI flash, we optimise the
  377. * case of read-only transfers by using the full 16bits of each
  378. * FIFO element.
  379. */
  380. if (!out)
  381. ret = rockchip_spi_16bit_reader(dev, &in, &len);
  382. /* This is the original 8bit reader/writer code */
  383. while (len > 0) {
  384. int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
  385. rkspi_enable_chip(regs, false);
  386. writel(todo - 1, &regs->ctrlr1);
  387. rkspi_enable_chip(regs, true);
  388. toread = todo;
  389. towrite = todo;
  390. while (toread || towrite) {
  391. u32 status = readl(&regs->sr);
  392. if (towrite && !(status & SR_TF_FULL)) {
  393. writel(out ? *out++ : 0, regs->txdr);
  394. towrite--;
  395. }
  396. if (toread && !(status & SR_RF_EMPT)) {
  397. u32 byte = readl(regs->rxdr);
  398. if (in)
  399. *in++ = byte;
  400. toread--;
  401. }
  402. }
  403. /*
  404. * In case that there's a transmit-component, we need to wait
  405. * until the control goes idle before we can disable the SPI
  406. * control logic (as this will implictly flush the FIFOs).
  407. */
  408. if (out) {
  409. ret = rkspi_wait_till_not_busy(regs);
  410. if (ret)
  411. break;
  412. }
  413. len -= todo;
  414. }
  415. /* Deassert CS after transfer */
  416. if (flags & SPI_XFER_END)
  417. spi_cs_deactivate(dev, slave_plat->cs);
  418. rkspi_enable_chip(regs, false);
  419. return ret;
  420. }
  421. static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
  422. {
  423. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  424. /* Clamp to the maximum frequency specified in the DTS */
  425. if (speed > priv->max_freq)
  426. speed = priv->max_freq;
  427. priv->speed_hz = speed;
  428. return 0;
  429. }
  430. static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
  431. {
  432. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  433. priv->mode = mode;
  434. return 0;
  435. }
  436. static const struct dm_spi_ops rockchip_spi_ops = {
  437. .claim_bus = rockchip_spi_claim_bus,
  438. .release_bus = rockchip_spi_release_bus,
  439. .xfer = rockchip_spi_xfer,
  440. .set_speed = rockchip_spi_set_speed,
  441. .set_mode = rockchip_spi_set_mode,
  442. /*
  443. * cs_info is not needed, since we require all chip selects to be
  444. * in the device tree explicitly
  445. */
  446. };
  447. const struct rockchip_spi_params rk3399_spi_params = {
  448. .master_manages_fifo = true,
  449. };
  450. static const struct udevice_id rockchip_spi_ids[] = {
  451. { .compatible = "rockchip,rk3066-spi" },
  452. { .compatible = "rockchip,rk3288-spi" },
  453. { .compatible = "rockchip,rk3328-spi" },
  454. { .compatible = "rockchip,rk3368-spi",
  455. .data = (ulong)&rk3399_spi_params },
  456. { .compatible = "rockchip,rk3399-spi",
  457. .data = (ulong)&rk3399_spi_params },
  458. { }
  459. };
  460. U_BOOT_DRIVER(rockchip_rk3288_spi) = {
  461. .name = "rockchip_rk3288_spi",
  462. .id = UCLASS_SPI,
  463. .of_match = rockchip_spi_ids,
  464. .ops = &rockchip_spi_ops,
  465. .of_to_plat = rockchip_spi_of_to_plat,
  466. .plat_auto = sizeof(struct rockchip_spi_plat),
  467. .priv_auto = sizeof(struct rockchip_spi_priv),
  468. .probe = rockchip_spi_probe,
  469. };
  470. DM_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3368_spi)