pinctrl-mxs.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <dm/device_compat.h>
  9. #include <dm/devres.h>
  10. #include <linux/io.h>
  11. #include <linux/err.h>
  12. #include <dm.h>
  13. #include <dm/pinctrl.h>
  14. #include <dm/read.h>
  15. #include "pinctrl-mxs.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. struct mxs_pinctrl_priv {
  18. void __iomem *base;
  19. const struct mxs_regs *regs;
  20. };
  21. static unsigned long mxs_dt_node_to_map(struct udevice *conf)
  22. {
  23. unsigned long config = 0;
  24. int ret;
  25. u32 val;
  26. ret = dev_read_u32(conf, "fsl,drive-strength", &val);
  27. if (!ret)
  28. config = val | MA_PRESENT;
  29. ret = dev_read_u32(conf, "fsl,voltage", &val);
  30. if (!ret)
  31. config |= val << VOL_SHIFT | VOL_PRESENT;
  32. ret = dev_read_u32(conf, "fsl,pull-up", &val);
  33. if (!ret)
  34. config |= val << PULL_SHIFT | PULL_PRESENT;
  35. return config;
  36. }
  37. static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin)
  38. {
  39. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  40. int muxsel = MUXID_TO_MUXSEL(val), shift;
  41. void __iomem *reg;
  42. reg = iomux->base + iomux->regs->muxsel;
  43. reg += bank * 0x20 + pin / 16 * 0x10;
  44. shift = pin % 16 * 2;
  45. mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg);
  46. debug(" mux %d,", muxsel);
  47. return 0;
  48. }
  49. static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
  50. {
  51. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  52. u32 *pin_data, val, ma, vol, pull;
  53. int npins, size, i, ret;
  54. unsigned long config;
  55. debug("\n%s: set state: %s\n", __func__, conf->name);
  56. size = dev_read_size(conf, "fsl,pinmux-ids");
  57. if (size < 0)
  58. return size;
  59. if (!size || size % sizeof(int)) {
  60. dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n",
  61. conf->name);
  62. return -EINVAL;
  63. }
  64. npins = size / sizeof(int);
  65. pin_data = devm_kzalloc(dev, size, 0);
  66. if (!pin_data)
  67. return -ENOMEM;
  68. ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins);
  69. if (ret) {
  70. dev_err(dev, "Error reading pin data.\n");
  71. devm_kfree(dev, pin_data);
  72. return -EINVAL;
  73. }
  74. config = mxs_dt_node_to_map(conf);
  75. ma = CONFIG_TO_MA(config);
  76. vol = CONFIG_TO_VOL(config);
  77. pull = CONFIG_TO_PULL(config);
  78. for (i = 0; i < npins; i++) {
  79. int pinid, bank, pin, shift;
  80. void __iomem *reg;
  81. val = pin_data[i];
  82. pinid = MUXID_TO_PINID(val);
  83. bank = PINID_TO_BANK(pinid);
  84. pin = PINID_TO_PIN(pinid);
  85. debug("(val: 0x%x) pin %d,", val, pinid);
  86. /* Setup pinmux */
  87. mxs_pinctrl_set_mux(dev, val, bank, pin);
  88. debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull);
  89. /* drive */
  90. reg = iomux->base + iomux->regs->drive;
  91. reg += bank * 0x40 + pin / 8 * 0x10;
  92. /* mA */
  93. if (config & MA_PRESENT) {
  94. shift = pin % 8 * 4;
  95. mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
  96. }
  97. /* vol */
  98. if (config & VOL_PRESENT) {
  99. shift = pin % 8 * 4 + 2;
  100. if (vol)
  101. writel(1 << shift, reg + SET);
  102. else
  103. writel(1 << shift, reg + CLR);
  104. }
  105. /* pull */
  106. if (config & PULL_PRESENT) {
  107. reg = iomux->base + iomux->regs->pull;
  108. reg += bank * 0x10;
  109. shift = pin;
  110. if (pull)
  111. writel(1 << shift, reg + SET);
  112. else
  113. writel(1 << shift, reg + CLR);
  114. }
  115. }
  116. devm_kfree(dev, pin_data);
  117. return 0;
  118. }
  119. static struct pinctrl_ops mxs_pinctrl_ops = {
  120. .set_state = mxs_pinctrl_set_state,
  121. };
  122. static int mxs_pinctrl_probe(struct udevice *dev)
  123. {
  124. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  125. iomux->base = dev_read_addr_ptr(dev);
  126. iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev);
  127. return 0;
  128. }
  129. static const struct mxs_regs imx23_regs = {
  130. .muxsel = 0x100,
  131. .drive = 0x200,
  132. .pull = 0x400,
  133. };
  134. static const struct mxs_regs imx28_regs = {
  135. .muxsel = 0x100,
  136. .drive = 0x300,
  137. .pull = 0x600,
  138. };
  139. static const struct udevice_id mxs_pinctrl_match[] = {
  140. { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs },
  141. { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs },
  142. { /* sentinel */ }
  143. };
  144. U_BOOT_DRIVER(fsl_imx23_pinctrl) = {
  145. .name = "fsl_imx23_pinctrl",
  146. .id = UCLASS_PINCTRL,
  147. .of_match = of_match_ptr(mxs_pinctrl_match),
  148. .probe = mxs_pinctrl_probe,
  149. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  150. .bind = dm_scan_fdt_dev,
  151. #endif
  152. .priv_auto = sizeof(struct mxs_pinctrl_priv),
  153. .ops = &mxs_pinctrl_ops,
  154. };
  155. DM_DRIVER_ALIAS(fsl_imx23_pinctrl, fsl_imx28_pinctrl)