devkit3250_spl.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Timll DevKit3250 board support, SPL board configuration
  4. *
  5. * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/emc.h>
  12. #include <asm/arch-lpc32xx/gpio.h>
  13. #include <spl.h>
  14. static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
  15. /*
  16. * SDRAM K4S561632N-LC60 settings are selected in assumption that
  17. * SDRAM clock may be set up to 166 MHz, however at the moment
  18. * it is 104 MHz. Most delay values are converted to be a multiple of
  19. * base clock, and precise pinned values are not needed here.
  20. */
  21. struct emc_dram_settings dram_64mb = {
  22. .cmddelay = 0x0001C000,
  23. .config0 = 0x00005682,
  24. .rascas0 = 0x00000302,
  25. .rdconfig = 0x00000011, /* undocumented but crucial value */
  26. .trp = 83333333,
  27. .tras = 23809524,
  28. .tsrex = 12500000,
  29. .twr = 83000000, /* tWR = tRDL = 2 CLK */
  30. .trc = 15384616,
  31. .trfc = 15384616,
  32. .txsr = 12500000,
  33. .trrd = 1,
  34. .tmrd = 1,
  35. .tcdlr = 0,
  36. .refresh = 130000, /* 800 clock cycles */
  37. .mode = 0x00018000,
  38. .emode = 0x02000000,
  39. };
  40. void spl_board_init(void)
  41. {
  42. /* First of all silence buzzer controlled by GPO_20 */
  43. writel((1 << 20), &gpio->p3_outp_clr);
  44. lpc32xx_uart_init(CONFIG_CONS_INDEX);
  45. preloader_console_init();
  46. ddr_init(&dram_64mb);
  47. /*
  48. * NAND initialization is done by nand_init(),
  49. * here just enable NAND SLC clocks
  50. */
  51. lpc32xx_slc_nand_init();
  52. }
  53. u32 spl_boot_device(void)
  54. {
  55. return BOOT_DEVICE_NAND;
  56. }