devkit3250.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Embest/Timll DevKit3250 board support
  4. *
  5. * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/emc.h>
  13. #include <asm/arch/wdt.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <linux/delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
  19. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  20. static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
  21. void reset_periph(void)
  22. {
  23. /* This function resets peripherals by triggering RESOUT_N */
  24. setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
  25. writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
  26. udelay(300);
  27. writel(0, &wdt->mctrl);
  28. clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
  29. /* Such a long delay is needed to initialize SMSC phy */
  30. udelay(10000);
  31. }
  32. int board_early_init_f(void)
  33. {
  34. lpc32xx_uart_init(CONFIG_CONS_INDEX);
  35. lpc32xx_i2c_init(1);
  36. lpc32xx_i2c_init(2);
  37. lpc32xx_ssp_init();
  38. lpc32xx_mac_init();
  39. /*
  40. * nWP may be controlled by GPO19, but unpopulated by default R23
  41. * makes no sense to configure this GPIO level, nWP is always high
  42. */
  43. lpc32xx_slc_nand_init();
  44. return 0;
  45. }
  46. int board_init(void)
  47. {
  48. /* adress of boot parameters */
  49. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  50. #ifdef CONFIG_SYS_FLASH_CFI
  51. /* Use 16-bit memory interface for NOR Flash */
  52. emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
  53. /* Change the NOR timings to optimum value to get maximum bandwidth */
  54. emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
  55. emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
  56. emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
  57. emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
  58. emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
  59. emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
  60. #endif
  61. return 0;
  62. }
  63. int dram_init(void)
  64. {
  65. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  66. CONFIG_SYS_SDRAM_SIZE);
  67. return 0;
  68. }