devices.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <ns16550.h>
  8. #include <dm/platform_data/lpc32xx_hsuart.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/uart.h>
  11. #include <asm/arch/mux.h>
  12. #include <asm/io.h>
  13. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  14. static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
  15. static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
  16. void lpc32xx_uart_init(unsigned int uart_id)
  17. {
  18. if (uart_id < 1 || uart_id > 7)
  19. return;
  20. /* Disable loopback mode, if it is set by S1L bootloader */
  21. clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
  22. if (uart_id < 3 || uart_id > 6)
  23. return;
  24. /* Enable UART system clock */
  25. setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
  26. /* Set UART into autoclock mode */
  27. clrsetbits_le32(&ctrl->clkmode,
  28. UART_CLKMODE_MASK(uart_id),
  29. UART_CLKMODE_AUTO(uart_id));
  30. /* Bypass pre-divider of UART clock */
  31. writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
  32. &clk->u3clk + (uart_id - 3));
  33. }
  34. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  35. static const struct ns16550_plat lpc32xx_uart[] = {
  36. { .base = UART3_BASE, .reg_shift = 2,
  37. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  38. { .base = UART4_BASE, .reg_shift = 2,
  39. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  40. { .base = UART5_BASE, .reg_shift = 2,
  41. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  42. { .base = UART6_BASE, .reg_shift = 2,
  43. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  44. };
  45. #if defined(CONFIG_LPC32XX_HSUART)
  46. static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
  47. { HS_UART1_BASE, },
  48. { HS_UART2_BASE, },
  49. { HS_UART7_BASE, },
  50. };
  51. #endif
  52. U_BOOT_DRVINFOS(lpc32xx_uarts) = {
  53. #if defined(CONFIG_LPC32XX_HSUART)
  54. { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
  55. { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
  56. #endif
  57. { "ns16550_serial", &lpc32xx_uart[0], },
  58. { "ns16550_serial", &lpc32xx_uart[1], },
  59. { "ns16550_serial", &lpc32xx_uart[2], },
  60. { "ns16550_serial", &lpc32xx_uart[3], },
  61. #if defined(CONFIG_LPC32XX_HSUART)
  62. { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
  63. #endif
  64. };
  65. #endif
  66. void lpc32xx_dma_init(void)
  67. {
  68. /* Enable DMA interface */
  69. writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
  70. }
  71. void lpc32xx_mac_init(void)
  72. {
  73. /* Enable MAC interface */
  74. writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
  75. #if defined(CONFIG_RMII)
  76. | CLK_MAC_RMII,
  77. #else
  78. | CLK_MAC_MII,
  79. #endif
  80. &clk->macclk_ctrl);
  81. }
  82. void lpc32xx_mlc_nand_init(void)
  83. {
  84. /* Enable NAND interface */
  85. writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
  86. }
  87. void lpc32xx_slc_nand_init(void)
  88. {
  89. /* Enable SLC NAND interface */
  90. writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
  91. }
  92. void lpc32xx_usb_init(void)
  93. {
  94. /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
  95. clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
  96. }
  97. void lpc32xx_i2c_init(unsigned int devnum)
  98. {
  99. /* Enable I2C interface */
  100. uint32_t ctrl = readl(&clk->i2cclk_ctrl);
  101. if (devnum == 1)
  102. ctrl |= CLK_I2C1_ENABLE;
  103. if (devnum == 2)
  104. ctrl |= CLK_I2C2_ENABLE;
  105. writel(ctrl, &clk->i2cclk_ctrl);
  106. }
  107. U_BOOT_DRVINFO(lpc32xx_gpios) = {
  108. .name = "gpio_lpc32xx"
  109. };
  110. /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
  111. #define P_MUX_SET_SSP0 0x1600
  112. void lpc32xx_ssp_init(void)
  113. {
  114. /* Enable SSP0 interface */
  115. writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
  116. /* Mux SSP0 pins */
  117. writel(P_MUX_SET_SSP0, &mux->p_mux_set);
  118. }