designware_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Designware master SPI core controller driver
  4. *
  5. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  6. *
  7. * Very loosely based on the Linux driver:
  8. * drivers/spi/spi-dw.c, which is:
  9. * Copyright (c) 2009, Intel Corporation.
  10. */
  11. #include <common.h>
  12. #include <asm-generic/gpio.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <malloc.h>
  17. #include <spi.h>
  18. #include <fdtdec.h>
  19. #include <reset.h>
  20. #include <linux/compat.h>
  21. #include <linux/iopoll.h>
  22. #include <asm/io.h>
  23. /* Register offsets */
  24. #define DW_SPI_CTRL0 0x00
  25. #define DW_SPI_CTRL1 0x04
  26. #define DW_SPI_SSIENR 0x08
  27. #define DW_SPI_MWCR 0x0c
  28. #define DW_SPI_SER 0x10
  29. #define DW_SPI_BAUDR 0x14
  30. #define DW_SPI_TXFLTR 0x18
  31. #define DW_SPI_RXFLTR 0x1c
  32. #define DW_SPI_TXFLR 0x20
  33. #define DW_SPI_RXFLR 0x24
  34. #define DW_SPI_SR 0x28
  35. #define DW_SPI_IMR 0x2c
  36. #define DW_SPI_ISR 0x30
  37. #define DW_SPI_RISR 0x34
  38. #define DW_SPI_TXOICR 0x38
  39. #define DW_SPI_RXOICR 0x3c
  40. #define DW_SPI_RXUICR 0x40
  41. #define DW_SPI_MSTICR 0x44
  42. #define DW_SPI_ICR 0x48
  43. #define DW_SPI_DMACR 0x4c
  44. #define DW_SPI_DMATDLR 0x50
  45. #define DW_SPI_DMARDLR 0x54
  46. #define DW_SPI_IDR 0x58
  47. #define DW_SPI_VERSION 0x5c
  48. #define DW_SPI_DR 0x60
  49. /* Bit fields in CTRLR0 */
  50. #define SPI_DFS_OFFSET 0
  51. #define SPI_FRF_OFFSET 4
  52. #define SPI_FRF_SPI 0x0
  53. #define SPI_FRF_SSP 0x1
  54. #define SPI_FRF_MICROWIRE 0x2
  55. #define SPI_FRF_RESV 0x3
  56. #define SPI_MODE_OFFSET 6
  57. #define SPI_SCPH_OFFSET 6
  58. #define SPI_SCOL_OFFSET 7
  59. #define SPI_TMOD_OFFSET 8
  60. #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
  61. #define SPI_TMOD_TR 0x0 /* xmit & recv */
  62. #define SPI_TMOD_TO 0x1 /* xmit only */
  63. #define SPI_TMOD_RO 0x2 /* recv only */
  64. #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
  65. #define SPI_SLVOE_OFFSET 10
  66. #define SPI_SRL_OFFSET 11
  67. #define SPI_CFS_OFFSET 12
  68. /* Bit fields in SR, 7 bits */
  69. #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
  70. #define SR_BUSY BIT(0)
  71. #define SR_TF_NOT_FULL BIT(1)
  72. #define SR_TF_EMPT BIT(2)
  73. #define SR_RF_NOT_EMPT BIT(3)
  74. #define SR_RF_FULL BIT(4)
  75. #define SR_TX_ERR BIT(5)
  76. #define SR_DCOL BIT(6)
  77. #define RX_TIMEOUT 1000 /* timeout in ms */
  78. struct dw_spi_platdata {
  79. s32 frequency; /* Default clock frequency, -1 for none */
  80. void __iomem *regs;
  81. };
  82. struct dw_spi_priv {
  83. void __iomem *regs;
  84. unsigned int freq; /* Default frequency */
  85. unsigned int mode;
  86. struct clk clk;
  87. unsigned long bus_clk_rate;
  88. struct gpio_desc cs_gpio; /* External chip-select gpio */
  89. int bits_per_word;
  90. u8 cs; /* chip select pin */
  91. u8 tmode; /* TR/TO/RO/EEPROM */
  92. u8 type; /* SPI/SSP/MicroWire */
  93. int len;
  94. u32 fifo_len; /* depth of the FIFO buffer */
  95. void *tx;
  96. void *tx_end;
  97. void *rx;
  98. void *rx_end;
  99. struct reset_ctl_bulk resets;
  100. };
  101. static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
  102. {
  103. return __raw_readl(priv->regs + offset);
  104. }
  105. static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
  106. {
  107. __raw_writel(val, priv->regs + offset);
  108. }
  109. static int request_gpio_cs(struct udevice *bus)
  110. {
  111. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  112. struct dw_spi_priv *priv = dev_get_priv(bus);
  113. int ret;
  114. /* External chip select gpio line is optional */
  115. ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
  116. if (ret == -ENOENT)
  117. return 0;
  118. if (ret < 0) {
  119. printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
  120. return ret;
  121. }
  122. if (dm_gpio_is_valid(&priv->cs_gpio)) {
  123. dm_gpio_set_dir_flags(&priv->cs_gpio,
  124. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  125. }
  126. debug("%s: used external gpio for CS management\n", __func__);
  127. #endif
  128. return 0;
  129. }
  130. static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  131. {
  132. struct dw_spi_platdata *plat = bus->platdata;
  133. plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
  134. /* Use 500KHz as a suitable default */
  135. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  136. 500000);
  137. debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
  138. plat->frequency);
  139. return request_gpio_cs(bus);
  140. }
  141. static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
  142. {
  143. dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
  144. }
  145. /* Restart the controller, disable all interrupts, clean rx fifo */
  146. static void spi_hw_init(struct dw_spi_priv *priv)
  147. {
  148. spi_enable_chip(priv, 0);
  149. dw_write(priv, DW_SPI_IMR, 0xff);
  150. spi_enable_chip(priv, 1);
  151. /*
  152. * Try to detect the FIFO depth if not set by interface driver,
  153. * the depth could be from 2 to 256 from HW spec
  154. */
  155. if (!priv->fifo_len) {
  156. u32 fifo;
  157. for (fifo = 1; fifo < 256; fifo++) {
  158. dw_write(priv, DW_SPI_TXFLTR, fifo);
  159. if (fifo != dw_read(priv, DW_SPI_TXFLTR))
  160. break;
  161. }
  162. priv->fifo_len = (fifo == 1) ? 0 : fifo;
  163. dw_write(priv, DW_SPI_TXFLTR, 0);
  164. }
  165. debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
  166. }
  167. /*
  168. * We define dw_spi_get_clk function as 'weak' as some targets
  169. * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
  170. * and implement dw_spi_get_clk their own way in their clock manager.
  171. */
  172. __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
  173. {
  174. struct dw_spi_priv *priv = dev_get_priv(bus);
  175. int ret;
  176. ret = clk_get_by_index(bus, 0, &priv->clk);
  177. if (ret)
  178. return ret;
  179. ret = clk_enable(&priv->clk);
  180. if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
  181. return ret;
  182. *rate = clk_get_rate(&priv->clk);
  183. if (!*rate)
  184. goto err_rate;
  185. debug("%s: get spi controller clk via device tree: %lu Hz\n",
  186. __func__, *rate);
  187. return 0;
  188. err_rate:
  189. clk_disable(&priv->clk);
  190. clk_free(&priv->clk);
  191. return -EINVAL;
  192. }
  193. static int dw_spi_reset(struct udevice *bus)
  194. {
  195. int ret;
  196. struct dw_spi_priv *priv = dev_get_priv(bus);
  197. ret = reset_get_bulk(bus, &priv->resets);
  198. if (ret) {
  199. /*
  200. * Return 0 if error due to !CONFIG_DM_RESET and reset
  201. * DT property is not present.
  202. */
  203. if (ret == -ENOENT || ret == -ENOTSUPP)
  204. return 0;
  205. dev_warn(bus, "Can't get reset: %d\n", ret);
  206. return ret;
  207. }
  208. ret = reset_deassert_bulk(&priv->resets);
  209. if (ret) {
  210. reset_release_bulk(&priv->resets);
  211. dev_err(bus, "Failed to reset: %d\n", ret);
  212. return ret;
  213. }
  214. return 0;
  215. }
  216. static int dw_spi_probe(struct udevice *bus)
  217. {
  218. struct dw_spi_platdata *plat = dev_get_platdata(bus);
  219. struct dw_spi_priv *priv = dev_get_priv(bus);
  220. int ret;
  221. priv->regs = plat->regs;
  222. priv->freq = plat->frequency;
  223. ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
  224. if (ret)
  225. return ret;
  226. ret = dw_spi_reset(bus);
  227. if (ret)
  228. return ret;
  229. /* Currently only bits_per_word == 8 supported */
  230. priv->bits_per_word = 8;
  231. priv->tmode = 0; /* Tx & Rx */
  232. /* Basic HW init */
  233. spi_hw_init(priv);
  234. return 0;
  235. }
  236. /* Return the max entries we can fill into tx fifo */
  237. static inline u32 tx_max(struct dw_spi_priv *priv)
  238. {
  239. u32 tx_left, tx_room, rxtx_gap;
  240. tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
  241. tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
  242. /*
  243. * Another concern is about the tx/rx mismatch, we
  244. * thought about using (priv->fifo_len - rxflr - txflr) as
  245. * one maximum value for tx, but it doesn't cover the
  246. * data which is out of tx/rx fifo and inside the
  247. * shift registers. So a control from sw point of
  248. * view is taken.
  249. */
  250. rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
  251. (priv->bits_per_word >> 3);
  252. return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
  253. }
  254. /* Return the max entries we should read out of rx fifo */
  255. static inline u32 rx_max(struct dw_spi_priv *priv)
  256. {
  257. u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
  258. return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
  259. }
  260. static void dw_writer(struct dw_spi_priv *priv)
  261. {
  262. u32 max = tx_max(priv);
  263. u16 txw = 0;
  264. while (max--) {
  265. /* Set the tx word if the transfer's original "tx" is not null */
  266. if (priv->tx_end - priv->len) {
  267. if (priv->bits_per_word == 8)
  268. txw = *(u8 *)(priv->tx);
  269. else
  270. txw = *(u16 *)(priv->tx);
  271. }
  272. dw_write(priv, DW_SPI_DR, txw);
  273. debug("%s: tx=0x%02x\n", __func__, txw);
  274. priv->tx += priv->bits_per_word >> 3;
  275. }
  276. }
  277. static void dw_reader(struct dw_spi_priv *priv)
  278. {
  279. u32 max = rx_max(priv);
  280. u16 rxw;
  281. while (max--) {
  282. rxw = dw_read(priv, DW_SPI_DR);
  283. debug("%s: rx=0x%02x\n", __func__, rxw);
  284. /* Care about rx if the transfer's original "rx" is not null */
  285. if (priv->rx_end - priv->len) {
  286. if (priv->bits_per_word == 8)
  287. *(u8 *)(priv->rx) = rxw;
  288. else
  289. *(u16 *)(priv->rx) = rxw;
  290. }
  291. priv->rx += priv->bits_per_word >> 3;
  292. }
  293. }
  294. static int poll_transfer(struct dw_spi_priv *priv)
  295. {
  296. do {
  297. dw_writer(priv);
  298. dw_reader(priv);
  299. } while (priv->rx_end > priv->rx);
  300. return 0;
  301. }
  302. /*
  303. * We define external_cs_manage function as 'weak' as some targets
  304. * (like MSCC Ocelot) don't control the external CS pin using a GPIO
  305. * controller. These SoCs use specific registers to control by
  306. * software the SPI pins (and especially the CS).
  307. */
  308. __weak void external_cs_manage(struct udevice *dev, bool on)
  309. {
  310. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  311. struct dw_spi_priv *priv = dev_get_priv(dev->parent);
  312. if (!dm_gpio_is_valid(&priv->cs_gpio))
  313. return;
  314. dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
  315. #endif
  316. }
  317. static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  318. const void *dout, void *din, unsigned long flags)
  319. {
  320. struct udevice *bus = dev->parent;
  321. struct dw_spi_priv *priv = dev_get_priv(bus);
  322. const u8 *tx = dout;
  323. u8 *rx = din;
  324. int ret = 0;
  325. u32 cr0 = 0;
  326. u32 val;
  327. u32 cs;
  328. /* spi core configured to do 8 bit transfers */
  329. if (bitlen % 8) {
  330. debug("Non byte aligned SPI transfer.\n");
  331. return -1;
  332. }
  333. /* Start the transaction if necessary. */
  334. if (flags & SPI_XFER_BEGIN)
  335. external_cs_manage(dev, false);
  336. cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
  337. (priv->mode << SPI_MODE_OFFSET) |
  338. (priv->tmode << SPI_TMOD_OFFSET);
  339. if (rx && tx)
  340. priv->tmode = SPI_TMOD_TR;
  341. else if (rx)
  342. priv->tmode = SPI_TMOD_RO;
  343. else
  344. /*
  345. * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
  346. * any data which breaks our logic in poll_transfer() above.
  347. */
  348. priv->tmode = SPI_TMOD_TR;
  349. cr0 &= ~SPI_TMOD_MASK;
  350. cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
  351. priv->len = bitlen >> 3;
  352. debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
  353. priv->tx = (void *)tx;
  354. priv->tx_end = priv->tx + priv->len;
  355. priv->rx = rx;
  356. priv->rx_end = priv->rx + priv->len;
  357. /* Disable controller before writing control registers */
  358. spi_enable_chip(priv, 0);
  359. debug("%s: cr0=%08x\n", __func__, cr0);
  360. /* Reprogram cr0 only if changed */
  361. if (dw_read(priv, DW_SPI_CTRL0) != cr0)
  362. dw_write(priv, DW_SPI_CTRL0, cr0);
  363. /*
  364. * Configure the desired SS (slave select 0...3) in the controller
  365. * The DW SPI controller will activate and deactivate this CS
  366. * automatically. So no cs_activate() etc is needed in this driver.
  367. */
  368. cs = spi_chip_select(dev);
  369. dw_write(priv, DW_SPI_SER, 1 << cs);
  370. /* Enable controller after writing control registers */
  371. spi_enable_chip(priv, 1);
  372. /* Start transfer in a polling loop */
  373. ret = poll_transfer(priv);
  374. /*
  375. * Wait for current transmit operation to complete.
  376. * Otherwise if some data still exists in Tx FIFO it can be
  377. * silently flushed, i.e. dropped on disabling of the controller,
  378. * which happens when writing 0 to DW_SPI_SSIENR which happens
  379. * in the beginning of new transfer.
  380. */
  381. if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
  382. (val & SR_TF_EMPT) && !(val & SR_BUSY),
  383. RX_TIMEOUT * 1000)) {
  384. ret = -ETIMEDOUT;
  385. }
  386. /* Stop the transaction if necessary */
  387. if (flags & SPI_XFER_END)
  388. external_cs_manage(dev, true);
  389. return ret;
  390. }
  391. static int dw_spi_set_speed(struct udevice *bus, uint speed)
  392. {
  393. struct dw_spi_platdata *plat = bus->platdata;
  394. struct dw_spi_priv *priv = dev_get_priv(bus);
  395. u16 clk_div;
  396. if (speed > plat->frequency)
  397. speed = plat->frequency;
  398. /* Disable controller before writing control registers */
  399. spi_enable_chip(priv, 0);
  400. /* clk_div doesn't support odd number */
  401. clk_div = priv->bus_clk_rate / speed;
  402. clk_div = (clk_div + 1) & 0xfffe;
  403. dw_write(priv, DW_SPI_BAUDR, clk_div);
  404. /* Enable controller after writing control registers */
  405. spi_enable_chip(priv, 1);
  406. priv->freq = speed;
  407. debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
  408. priv->freq, clk_div);
  409. return 0;
  410. }
  411. static int dw_spi_set_mode(struct udevice *bus, uint mode)
  412. {
  413. struct dw_spi_priv *priv = dev_get_priv(bus);
  414. /*
  415. * Can't set mode yet. Since this depends on if rx, tx, or
  416. * rx & tx is requested. So we have to defer this to the
  417. * real transfer function.
  418. */
  419. priv->mode = mode;
  420. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  421. return 0;
  422. }
  423. static int dw_spi_remove(struct udevice *bus)
  424. {
  425. struct dw_spi_priv *priv = dev_get_priv(bus);
  426. int ret;
  427. ret = reset_release_bulk(&priv->resets);
  428. if (ret)
  429. return ret;
  430. #if CONFIG_IS_ENABLED(CLK)
  431. ret = clk_disable(&priv->clk);
  432. if (ret)
  433. return ret;
  434. ret = clk_free(&priv->clk);
  435. if (ret)
  436. return ret;
  437. #endif
  438. return 0;
  439. }
  440. static const struct dm_spi_ops dw_spi_ops = {
  441. .xfer = dw_spi_xfer,
  442. .set_speed = dw_spi_set_speed,
  443. .set_mode = dw_spi_set_mode,
  444. /*
  445. * cs_info is not needed, since we require all chip selects to be
  446. * in the device tree explicitly
  447. */
  448. };
  449. static const struct udevice_id dw_spi_ids[] = {
  450. { .compatible = "snps,dw-apb-ssi" },
  451. { }
  452. };
  453. U_BOOT_DRIVER(dw_spi) = {
  454. .name = "dw_spi",
  455. .id = UCLASS_SPI,
  456. .of_match = dw_spi_ids,
  457. .ops = &dw_spi_ops,
  458. .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
  459. .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
  460. .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
  461. .probe = dw_spi_probe,
  462. .remove = dw_spi_remove,
  463. };