atmel_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Atmel Corporation
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <fdtdec.h>
  9. #include <spi.h>
  10. #include <malloc.h>
  11. #include <wait_bit.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/hardware.h>
  15. #ifdef CONFIG_DM_SPI
  16. #include <asm/arch/at91_spi.h>
  17. #endif
  18. #if CONFIG_IS_ENABLED(DM_GPIO)
  19. #include <asm/gpio.h>
  20. #endif
  21. #include "atmel_spi.h"
  22. #ifndef CONFIG_DM_SPI
  23. static int spi_has_wdrbt(struct atmel_spi_slave *slave)
  24. {
  25. unsigned int ver;
  26. ver = spi_readl(slave, VERSION);
  27. return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
  28. }
  29. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  30. unsigned int max_hz, unsigned int mode)
  31. {
  32. struct atmel_spi_slave *as;
  33. unsigned int scbr;
  34. u32 csrx;
  35. void *regs;
  36. if (!spi_cs_is_valid(bus, cs))
  37. return NULL;
  38. switch (bus) {
  39. case 0:
  40. regs = (void *)ATMEL_BASE_SPI0;
  41. break;
  42. #ifdef ATMEL_BASE_SPI1
  43. case 1:
  44. regs = (void *)ATMEL_BASE_SPI1;
  45. break;
  46. #endif
  47. #ifdef ATMEL_BASE_SPI2
  48. case 2:
  49. regs = (void *)ATMEL_BASE_SPI2;
  50. break;
  51. #endif
  52. #ifdef ATMEL_BASE_SPI3
  53. case 3:
  54. regs = (void *)ATMEL_BASE_SPI3;
  55. break;
  56. #endif
  57. default:
  58. return NULL;
  59. }
  60. scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
  61. if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
  62. /* Too low max SCK rate */
  63. return NULL;
  64. if (scbr < 1)
  65. scbr = 1;
  66. csrx = ATMEL_SPI_CSRx_SCBR(scbr);
  67. csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
  68. if (!(mode & SPI_CPHA))
  69. csrx |= ATMEL_SPI_CSRx_NCPHA;
  70. if (mode & SPI_CPOL)
  71. csrx |= ATMEL_SPI_CSRx_CPOL;
  72. as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
  73. if (!as)
  74. return NULL;
  75. as->regs = regs;
  76. as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
  77. | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
  78. if (spi_has_wdrbt(as))
  79. as->mr |= ATMEL_SPI_MR_WDRBT;
  80. spi_writel(as, CSR(cs), csrx);
  81. return &as->slave;
  82. }
  83. void spi_free_slave(struct spi_slave *slave)
  84. {
  85. struct atmel_spi_slave *as = to_atmel_spi(slave);
  86. free(as);
  87. }
  88. int spi_claim_bus(struct spi_slave *slave)
  89. {
  90. struct atmel_spi_slave *as = to_atmel_spi(slave);
  91. /* Enable the SPI hardware */
  92. spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
  93. /*
  94. * Select the slave. This should set SCK to the correct
  95. * initial state, etc.
  96. */
  97. spi_writel(as, MR, as->mr);
  98. return 0;
  99. }
  100. void spi_release_bus(struct spi_slave *slave)
  101. {
  102. struct atmel_spi_slave *as = to_atmel_spi(slave);
  103. /* Disable the SPI hardware */
  104. spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
  105. }
  106. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  107. const void *dout, void *din, unsigned long flags)
  108. {
  109. struct atmel_spi_slave *as = to_atmel_spi(slave);
  110. unsigned int len_tx;
  111. unsigned int len_rx;
  112. unsigned int len;
  113. u32 status;
  114. const u8 *txp = dout;
  115. u8 *rxp = din;
  116. u8 value;
  117. if (bitlen == 0)
  118. /* Finish any previously submitted transfers */
  119. goto out;
  120. /*
  121. * TODO: The controller can do non-multiple-of-8 bit
  122. * transfers, but this driver currently doesn't support it.
  123. *
  124. * It's also not clear how such transfers are supposed to be
  125. * represented as a stream of bytes...this is a limitation of
  126. * the current SPI interface.
  127. */
  128. if (bitlen % 8) {
  129. /* Errors always terminate an ongoing transfer */
  130. flags |= SPI_XFER_END;
  131. goto out;
  132. }
  133. len = bitlen / 8;
  134. /*
  135. * The controller can do automatic CS control, but it is
  136. * somewhat quirky, and it doesn't really buy us much anyway
  137. * in the context of U-Boot.
  138. */
  139. if (flags & SPI_XFER_BEGIN) {
  140. spi_cs_activate(slave);
  141. /*
  142. * sometimes the RDR is not empty when we get here,
  143. * in theory that should not happen, but it DOES happen.
  144. * Read it here to be on the safe side.
  145. * That also clears the OVRES flag. Required if the
  146. * following loop exits due to OVRES!
  147. */
  148. spi_readl(as, RDR);
  149. }
  150. for (len_tx = 0, len_rx = 0; len_rx < len; ) {
  151. status = spi_readl(as, SR);
  152. if (status & ATMEL_SPI_SR_OVRES)
  153. return -1;
  154. if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
  155. if (txp)
  156. value = *txp++;
  157. else
  158. value = 0;
  159. spi_writel(as, TDR, value);
  160. len_tx++;
  161. }
  162. if (status & ATMEL_SPI_SR_RDRF) {
  163. value = spi_readl(as, RDR);
  164. if (rxp)
  165. *rxp++ = value;
  166. len_rx++;
  167. }
  168. }
  169. out:
  170. if (flags & SPI_XFER_END) {
  171. /*
  172. * Wait until the transfer is completely done before
  173. * we deactivate CS.
  174. */
  175. do {
  176. status = spi_readl(as, SR);
  177. } while (!(status & ATMEL_SPI_SR_TXEMPTY));
  178. spi_cs_deactivate(slave);
  179. }
  180. return 0;
  181. }
  182. #else
  183. #define MAX_CS_COUNT 4
  184. struct atmel_spi_platdata {
  185. struct at91_spi *regs;
  186. };
  187. struct atmel_spi_priv {
  188. unsigned int freq; /* Default frequency */
  189. unsigned int mode;
  190. ulong bus_clk_rate;
  191. #if CONFIG_IS_ENABLED(DM_GPIO)
  192. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  193. #endif
  194. };
  195. static int atmel_spi_claim_bus(struct udevice *dev)
  196. {
  197. struct udevice *bus = dev_get_parent(dev);
  198. struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
  199. struct atmel_spi_priv *priv = dev_get_priv(bus);
  200. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  201. struct at91_spi *reg_base = bus_plat->regs;
  202. u32 cs = slave_plat->cs;
  203. u32 freq = priv->freq;
  204. u32 scbr, csrx, mode;
  205. scbr = (priv->bus_clk_rate + freq - 1) / freq;
  206. if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
  207. return -EINVAL;
  208. if (scbr < 1)
  209. scbr = 1;
  210. csrx = ATMEL_SPI_CSRx_SCBR(scbr);
  211. csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
  212. if (!(priv->mode & SPI_CPHA))
  213. csrx |= ATMEL_SPI_CSRx_NCPHA;
  214. if (priv->mode & SPI_CPOL)
  215. csrx |= ATMEL_SPI_CSRx_CPOL;
  216. writel(csrx, &reg_base->csr[cs]);
  217. mode = ATMEL_SPI_MR_MSTR |
  218. ATMEL_SPI_MR_MODFDIS |
  219. ATMEL_SPI_MR_WDRBT |
  220. ATMEL_SPI_MR_PCS(~(1 << cs));
  221. writel(mode, &reg_base->mr);
  222. writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr);
  223. return 0;
  224. }
  225. static int atmel_spi_release_bus(struct udevice *dev)
  226. {
  227. struct udevice *bus = dev_get_parent(dev);
  228. struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
  229. writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
  230. return 0;
  231. }
  232. static void atmel_spi_cs_activate(struct udevice *dev)
  233. {
  234. #if CONFIG_IS_ENABLED(DM_GPIO)
  235. struct udevice *bus = dev_get_parent(dev);
  236. struct atmel_spi_priv *priv = dev_get_priv(bus);
  237. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  238. u32 cs = slave_plat->cs;
  239. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  240. return;
  241. dm_gpio_set_value(&priv->cs_gpios[cs], 0);
  242. #endif
  243. }
  244. static void atmel_spi_cs_deactivate(struct udevice *dev)
  245. {
  246. #if CONFIG_IS_ENABLED(DM_GPIO)
  247. struct udevice *bus = dev_get_parent(dev);
  248. struct atmel_spi_priv *priv = dev_get_priv(bus);
  249. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  250. u32 cs = slave_plat->cs;
  251. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  252. return;
  253. dm_gpio_set_value(&priv->cs_gpios[cs], 1);
  254. #endif
  255. }
  256. static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
  257. const void *dout, void *din, unsigned long flags)
  258. {
  259. struct udevice *bus = dev_get_parent(dev);
  260. struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
  261. struct at91_spi *reg_base = bus_plat->regs;
  262. u32 len_tx, len_rx, len;
  263. u32 status;
  264. const u8 *txp = dout;
  265. u8 *rxp = din;
  266. u8 value;
  267. if (bitlen == 0)
  268. goto out;
  269. /*
  270. * The controller can do non-multiple-of-8 bit
  271. * transfers, but this driver currently doesn't support it.
  272. *
  273. * It's also not clear how such transfers are supposed to be
  274. * represented as a stream of bytes...this is a limitation of
  275. * the current SPI interface.
  276. */
  277. if (bitlen % 8) {
  278. /* Errors always terminate an ongoing transfer */
  279. flags |= SPI_XFER_END;
  280. goto out;
  281. }
  282. len = bitlen / 8;
  283. /*
  284. * The controller can do automatic CS control, but it is
  285. * somewhat quirky, and it doesn't really buy us much anyway
  286. * in the context of U-Boot.
  287. */
  288. if (flags & SPI_XFER_BEGIN) {
  289. atmel_spi_cs_activate(dev);
  290. /*
  291. * sometimes the RDR is not empty when we get here,
  292. * in theory that should not happen, but it DOES happen.
  293. * Read it here to be on the safe side.
  294. * That also clears the OVRES flag. Required if the
  295. * following loop exits due to OVRES!
  296. */
  297. readl(&reg_base->rdr);
  298. }
  299. for (len_tx = 0, len_rx = 0; len_rx < len; ) {
  300. status = readl(&reg_base->sr);
  301. if (status & ATMEL_SPI_SR_OVRES)
  302. return -1;
  303. if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
  304. if (txp)
  305. value = *txp++;
  306. else
  307. value = 0;
  308. writel(value, &reg_base->tdr);
  309. len_tx++;
  310. }
  311. if (status & ATMEL_SPI_SR_RDRF) {
  312. value = readl(&reg_base->rdr);
  313. if (rxp)
  314. *rxp++ = value;
  315. len_rx++;
  316. }
  317. }
  318. out:
  319. if (flags & SPI_XFER_END) {
  320. /*
  321. * Wait until the transfer is completely done before
  322. * we deactivate CS.
  323. */
  324. wait_for_bit_le32(&reg_base->sr,
  325. ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
  326. atmel_spi_cs_deactivate(dev);
  327. }
  328. return 0;
  329. }
  330. static int atmel_spi_set_speed(struct udevice *bus, uint speed)
  331. {
  332. struct atmel_spi_priv *priv = dev_get_priv(bus);
  333. priv->freq = speed;
  334. return 0;
  335. }
  336. static int atmel_spi_set_mode(struct udevice *bus, uint mode)
  337. {
  338. struct atmel_spi_priv *priv = dev_get_priv(bus);
  339. priv->mode = mode;
  340. return 0;
  341. }
  342. static const struct dm_spi_ops atmel_spi_ops = {
  343. .claim_bus = atmel_spi_claim_bus,
  344. .release_bus = atmel_spi_release_bus,
  345. .xfer = atmel_spi_xfer,
  346. .set_speed = atmel_spi_set_speed,
  347. .set_mode = atmel_spi_set_mode,
  348. /*
  349. * cs_info is not needed, since we require all chip selects to be
  350. * in the device tree explicitly
  351. */
  352. };
  353. static int atmel_spi_enable_clk(struct udevice *bus)
  354. {
  355. struct atmel_spi_priv *priv = dev_get_priv(bus);
  356. struct clk clk;
  357. ulong clk_rate;
  358. int ret;
  359. ret = clk_get_by_index(bus, 0, &clk);
  360. if (ret)
  361. return -EINVAL;
  362. ret = clk_enable(&clk);
  363. if (ret)
  364. return ret;
  365. clk_rate = clk_get_rate(&clk);
  366. if (!clk_rate)
  367. return -EINVAL;
  368. priv->bus_clk_rate = clk_rate;
  369. clk_free(&clk);
  370. return 0;
  371. }
  372. static int atmel_spi_probe(struct udevice *bus)
  373. {
  374. struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
  375. int ret;
  376. ret = atmel_spi_enable_clk(bus);
  377. if (ret)
  378. return ret;
  379. bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
  380. #if CONFIG_IS_ENABLED(DM_GPIO)
  381. struct atmel_spi_priv *priv = dev_get_priv(bus);
  382. int i;
  383. ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
  384. ARRAY_SIZE(priv->cs_gpios), 0);
  385. if (ret < 0) {
  386. pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
  387. return ret;
  388. }
  389. for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
  390. if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
  391. continue;
  392. dm_gpio_set_dir_flags(&priv->cs_gpios[i],
  393. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  394. }
  395. #endif
  396. writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
  397. return 0;
  398. }
  399. static const struct udevice_id atmel_spi_ids[] = {
  400. { .compatible = "atmel,at91rm9200-spi" },
  401. { }
  402. };
  403. U_BOOT_DRIVER(atmel_spi) = {
  404. .name = "atmel_spi",
  405. .id = UCLASS_SPI,
  406. .of_match = atmel_spi_ids,
  407. .ops = &atmel_spi_ops,
  408. .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
  409. .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
  410. .probe = atmel_spi_probe,
  411. };
  412. #endif