fec_mxc.c 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  4. * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  5. * (C) Copyright 2008 Armadeus Systems nc
  6. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <malloc.h>
  14. #include <memalign.h>
  15. #include <miiphy.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <power/regulator.h>
  19. #include <asm/io.h>
  20. #include <linux/errno.h>
  21. #include <linux/compiler.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include <asm/mach-imx/sys_proto.h>
  25. #include <asm-generic/gpio.h>
  26. #include "fec_mxc.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * Timeout the transfer after 5 mS. This is usually a bit more, since
  30. * the code in the tightloops this timeout is used in adds some overhead.
  31. */
  32. #define FEC_XFER_TIMEOUT 5000
  33. /*
  34. * The standard 32-byte DMA alignment does not work on mx6solox, which requires
  35. * 64-byte alignment in the DMA RX FEC buffer.
  36. * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
  37. * satisfies the alignment on other SoCs (32-bytes)
  38. */
  39. #define FEC_DMA_RX_MINALIGN 64
  40. #ifndef CONFIG_MII
  41. #error "CONFIG_MII has to be defined!"
  42. #endif
  43. #ifndef CONFIG_FEC_XCV_TYPE
  44. #define CONFIG_FEC_XCV_TYPE MII100
  45. #endif
  46. /*
  47. * The i.MX28 operates with packets in big endian. We need to swap them before
  48. * sending and after receiving.
  49. */
  50. #ifdef CONFIG_MX28
  51. #define CONFIG_FEC_MXC_SWAP_PACKET
  52. #endif
  53. #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
  54. /* Check various alignment issues at compile time */
  55. #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
  56. #error "ARCH_DMA_MINALIGN must be multiple of 16!"
  57. #endif
  58. #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
  59. (PKTALIGN % ARCH_DMA_MINALIGN != 0))
  60. #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
  61. #endif
  62. #undef DEBUG
  63. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  64. static void swap_packet(uint32_t *packet, int length)
  65. {
  66. int i;
  67. for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
  68. packet[i] = __swab32(packet[i]);
  69. }
  70. #endif
  71. /* MII-interface related functions */
  72. static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
  73. uint8_t regaddr)
  74. {
  75. uint32_t reg; /* convenient holder for the PHY register */
  76. uint32_t phy; /* convenient holder for the PHY */
  77. uint32_t start;
  78. int val;
  79. /*
  80. * reading from any PHY's register is done by properly
  81. * programming the FEC's MII data register.
  82. */
  83. writel(FEC_IEVENT_MII, &eth->ievent);
  84. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  85. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  86. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
  87. phy | reg, &eth->mii_data);
  88. /* wait for the related interrupt */
  89. start = get_timer(0);
  90. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  91. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  92. printf("Read MDIO failed...\n");
  93. return -1;
  94. }
  95. }
  96. /* clear mii interrupt bit */
  97. writel(FEC_IEVENT_MII, &eth->ievent);
  98. /* it's now safe to read the PHY's register */
  99. val = (unsigned short)readl(&eth->mii_data);
  100. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  101. regaddr, val);
  102. return val;
  103. }
  104. #ifndef imx_get_fecclk
  105. u32 __weak imx_get_fecclk(void)
  106. {
  107. return 0;
  108. }
  109. #endif
  110. static int fec_get_clk_rate(void *udev, int idx)
  111. {
  112. struct fec_priv *fec;
  113. struct udevice *dev;
  114. int ret;
  115. if (IS_ENABLED(CONFIG_IMX8) ||
  116. CONFIG_IS_ENABLED(CLK_CCF)) {
  117. dev = udev;
  118. if (!dev) {
  119. ret = uclass_get_device(UCLASS_ETH, idx, &dev);
  120. if (ret < 0) {
  121. debug("Can't get FEC udev: %d\n", ret);
  122. return ret;
  123. }
  124. }
  125. fec = dev_get_priv(dev);
  126. if (fec)
  127. return fec->clk_rate;
  128. return -EINVAL;
  129. } else {
  130. return imx_get_fecclk();
  131. }
  132. }
  133. static void fec_mii_setspeed(struct ethernet_regs *eth)
  134. {
  135. /*
  136. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  137. * and do not drop the Preamble.
  138. *
  139. * The i.MX28 and i.MX6 types have another field in the MSCR (aka
  140. * MII_SPEED) register that defines the MDIO output hold time. Earlier
  141. * versions are RAZ there, so just ignore the difference and write the
  142. * register always.
  143. * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
  144. * HOLDTIME + 1 is the number of clk cycles the fec is holding the
  145. * output.
  146. * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
  147. * Given that ceil(clkrate / 5000000) <= 64, the calculation for
  148. * holdtime cannot result in a value greater than 3.
  149. */
  150. u32 pclk;
  151. u32 speed;
  152. u32 hold;
  153. int ret;
  154. ret = fec_get_clk_rate(NULL, 0);
  155. if (ret < 0) {
  156. printf("Can't find FEC0 clk rate: %d\n", ret);
  157. return;
  158. }
  159. pclk = ret;
  160. speed = DIV_ROUND_UP(pclk, 5000000);
  161. hold = DIV_ROUND_UP(pclk, 100000000) - 1;
  162. #ifdef FEC_QUIRK_ENET_MAC
  163. speed--;
  164. #endif
  165. writel(speed << 1 | hold << 8, &eth->mii_speed);
  166. debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
  167. }
  168. static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
  169. uint8_t regaddr, uint16_t data)
  170. {
  171. uint32_t reg; /* convenient holder for the PHY register */
  172. uint32_t phy; /* convenient holder for the PHY */
  173. uint32_t start;
  174. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  175. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  176. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  177. FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
  178. /* wait for the MII interrupt */
  179. start = get_timer(0);
  180. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  181. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  182. printf("Write MDIO failed...\n");
  183. return -1;
  184. }
  185. }
  186. /* clear MII interrupt bit */
  187. writel(FEC_IEVENT_MII, &eth->ievent);
  188. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  189. regaddr, data);
  190. return 0;
  191. }
  192. static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
  193. int regaddr)
  194. {
  195. return fec_mdio_read(bus->priv, phyaddr, regaddr);
  196. }
  197. static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
  198. int regaddr, u16 data)
  199. {
  200. return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
  201. }
  202. #ifndef CONFIG_PHYLIB
  203. static int miiphy_restart_aneg(struct eth_device *dev)
  204. {
  205. int ret = 0;
  206. #if !defined(CONFIG_FEC_MXC_NO_ANEG)
  207. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  208. struct ethernet_regs *eth = fec->bus->priv;
  209. /*
  210. * Wake up from sleep if necessary
  211. * Reset PHY, then delay 300ns
  212. */
  213. #ifdef CONFIG_MX27
  214. fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
  215. #endif
  216. fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
  217. udelay(1000);
  218. /* Set the auto-negotiation advertisement register bits */
  219. fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
  220. LPA_100FULL | LPA_100HALF | LPA_10FULL |
  221. LPA_10HALF | PHY_ANLPAR_PSB_802_3);
  222. fec_mdio_write(eth, fec->phy_id, MII_BMCR,
  223. BMCR_ANENABLE | BMCR_ANRESTART);
  224. if (fec->mii_postcall)
  225. ret = fec->mii_postcall(fec->phy_id);
  226. #endif
  227. return ret;
  228. }
  229. #ifndef CONFIG_FEC_FIXED_SPEED
  230. static int miiphy_wait_aneg(struct eth_device *dev)
  231. {
  232. uint32_t start;
  233. int status;
  234. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  235. struct ethernet_regs *eth = fec->bus->priv;
  236. /* Wait for AN completion */
  237. start = get_timer(0);
  238. do {
  239. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  240. printf("%s: Autonegotiation timeout\n", dev->name);
  241. return -1;
  242. }
  243. status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
  244. if (status < 0) {
  245. printf("%s: Autonegotiation failed. status: %d\n",
  246. dev->name, status);
  247. return -1;
  248. }
  249. } while (!(status & BMSR_LSTATUS));
  250. return 0;
  251. }
  252. #endif /* CONFIG_FEC_FIXED_SPEED */
  253. #endif
  254. static int fec_rx_task_enable(struct fec_priv *fec)
  255. {
  256. writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
  257. return 0;
  258. }
  259. static int fec_rx_task_disable(struct fec_priv *fec)
  260. {
  261. return 0;
  262. }
  263. static int fec_tx_task_enable(struct fec_priv *fec)
  264. {
  265. writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
  266. return 0;
  267. }
  268. static int fec_tx_task_disable(struct fec_priv *fec)
  269. {
  270. return 0;
  271. }
  272. /**
  273. * Initialize receive task's buffer descriptors
  274. * @param[in] fec all we know about the device yet
  275. * @param[in] count receive buffer count to be allocated
  276. * @param[in] dsize desired size of each receive buffer
  277. * @return 0 on success
  278. *
  279. * Init all RX descriptors to default values.
  280. */
  281. static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  282. {
  283. uint32_t size;
  284. ulong data;
  285. int i;
  286. /*
  287. * Reload the RX descriptors with default values and wipe
  288. * the RX buffers.
  289. */
  290. size = roundup(dsize, ARCH_DMA_MINALIGN);
  291. for (i = 0; i < count; i++) {
  292. data = fec->rbd_base[i].data_pointer;
  293. memset((void *)data, 0, dsize);
  294. flush_dcache_range(data, data + size);
  295. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  296. fec->rbd_base[i].data_length = 0;
  297. }
  298. /* Mark the last RBD to close the ring. */
  299. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  300. fec->rbd_index = 0;
  301. flush_dcache_range((ulong)fec->rbd_base,
  302. (ulong)fec->rbd_base + size);
  303. }
  304. /**
  305. * Initialize transmit task's buffer descriptors
  306. * @param[in] fec all we know about the device yet
  307. *
  308. * Transmit buffers are created externally. We only have to init the BDs here.\n
  309. * Note: There is a race condition in the hardware. When only one BD is in
  310. * use it must be marked with the WRAP bit to use it for every transmitt.
  311. * This bit in combination with the READY bit results into double transmit
  312. * of each data buffer. It seems the state machine checks READY earlier then
  313. * resetting it after the first transfer.
  314. * Using two BDs solves this issue.
  315. */
  316. static void fec_tbd_init(struct fec_priv *fec)
  317. {
  318. ulong addr = (ulong)fec->tbd_base;
  319. unsigned size = roundup(2 * sizeof(struct fec_bd),
  320. ARCH_DMA_MINALIGN);
  321. memset(fec->tbd_base, 0, size);
  322. fec->tbd_base[0].status = 0;
  323. fec->tbd_base[1].status = FEC_TBD_WRAP;
  324. fec->tbd_index = 0;
  325. flush_dcache_range(addr, addr + size);
  326. }
  327. /**
  328. * Mark the given read buffer descriptor as free
  329. * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  330. * @param[in] prbd buffer descriptor to mark free again
  331. */
  332. static void fec_rbd_clean(int last, struct fec_bd *prbd)
  333. {
  334. unsigned short flags = FEC_RBD_EMPTY;
  335. if (last)
  336. flags |= FEC_RBD_WRAP;
  337. writew(flags, &prbd->status);
  338. writew(0, &prbd->data_length);
  339. }
  340. static int fec_get_hwaddr(int dev_id, unsigned char *mac)
  341. {
  342. imx_get_mac_from_fuse(dev_id, mac);
  343. return !is_valid_ethaddr(mac);
  344. }
  345. #ifdef CONFIG_DM_ETH
  346. static int fecmxc_set_hwaddr(struct udevice *dev)
  347. #else
  348. static int fec_set_hwaddr(struct eth_device *dev)
  349. #endif
  350. {
  351. #ifdef CONFIG_DM_ETH
  352. struct fec_priv *fec = dev_get_priv(dev);
  353. struct eth_pdata *pdata = dev_get_platdata(dev);
  354. uchar *mac = pdata->enetaddr;
  355. #else
  356. uchar *mac = dev->enetaddr;
  357. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  358. #endif
  359. writel(0, &fec->eth->iaddr1);
  360. writel(0, &fec->eth->iaddr2);
  361. writel(0, &fec->eth->gaddr1);
  362. writel(0, &fec->eth->gaddr2);
  363. /* Set physical address */
  364. writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
  365. &fec->eth->paddr1);
  366. writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
  367. return 0;
  368. }
  369. /* Do initial configuration of the FEC registers */
  370. static void fec_reg_setup(struct fec_priv *fec)
  371. {
  372. uint32_t rcntrl;
  373. /* Set interrupt mask register */
  374. writel(0x00000000, &fec->eth->imask);
  375. /* Clear FEC-Lite interrupt event register(IEVENT) */
  376. writel(0xffffffff, &fec->eth->ievent);
  377. /* Set FEC-Lite receive control register(R_CNTRL): */
  378. /* Start with frame length = 1518, common for all modes. */
  379. rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
  380. if (fec->xcv_type != SEVENWIRE) /* xMII modes */
  381. rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
  382. if (fec->xcv_type == RGMII)
  383. rcntrl |= FEC_RCNTRL_RGMII;
  384. else if (fec->xcv_type == RMII)
  385. rcntrl |= FEC_RCNTRL_RMII;
  386. writel(rcntrl, &fec->eth->r_cntrl);
  387. }
  388. /**
  389. * Start the FEC engine
  390. * @param[in] dev Our device to handle
  391. */
  392. #ifdef CONFIG_DM_ETH
  393. static int fec_open(struct udevice *dev)
  394. #else
  395. static int fec_open(struct eth_device *edev)
  396. #endif
  397. {
  398. #ifdef CONFIG_DM_ETH
  399. struct fec_priv *fec = dev_get_priv(dev);
  400. #else
  401. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  402. #endif
  403. int speed;
  404. ulong addr, size;
  405. int i;
  406. debug("fec_open: fec_open(dev)\n");
  407. /* full-duplex, heartbeat disabled */
  408. writel(1 << 2, &fec->eth->x_cntrl);
  409. fec->rbd_index = 0;
  410. /* Invalidate all descriptors */
  411. for (i = 0; i < FEC_RBD_NUM - 1; i++)
  412. fec_rbd_clean(0, &fec->rbd_base[i]);
  413. fec_rbd_clean(1, &fec->rbd_base[i]);
  414. /* Flush the descriptors into RAM */
  415. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
  416. ARCH_DMA_MINALIGN);
  417. addr = (ulong)fec->rbd_base;
  418. flush_dcache_range(addr, addr + size);
  419. #ifdef FEC_QUIRK_ENET_MAC
  420. /* Enable ENET HW endian SWAP */
  421. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
  422. &fec->eth->ecntrl);
  423. /* Enable ENET store and forward mode */
  424. writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
  425. &fec->eth->x_wmrk);
  426. #endif
  427. /* Enable FEC-Lite controller */
  428. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
  429. &fec->eth->ecntrl);
  430. #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
  431. udelay(100);
  432. /* setup the MII gasket for RMII mode */
  433. /* disable the gasket */
  434. writew(0, &fec->eth->miigsk_enr);
  435. /* wait for the gasket to be disabled */
  436. while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
  437. udelay(2);
  438. /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
  439. writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
  440. /* re-enable the gasket */
  441. writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
  442. /* wait until MII gasket is ready */
  443. int max_loops = 10;
  444. while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
  445. if (--max_loops <= 0) {
  446. printf("WAIT for MII Gasket ready timed out\n");
  447. break;
  448. }
  449. }
  450. #endif
  451. #ifdef CONFIG_PHYLIB
  452. {
  453. /* Start up the PHY */
  454. int ret = phy_startup(fec->phydev);
  455. if (ret) {
  456. printf("Could not initialize PHY %s\n",
  457. fec->phydev->dev->name);
  458. return ret;
  459. }
  460. speed = fec->phydev->speed;
  461. }
  462. #elif CONFIG_FEC_FIXED_SPEED
  463. speed = CONFIG_FEC_FIXED_SPEED;
  464. #else
  465. miiphy_wait_aneg(edev);
  466. speed = miiphy_speed(edev->name, fec->phy_id);
  467. miiphy_duplex(edev->name, fec->phy_id);
  468. #endif
  469. #ifdef FEC_QUIRK_ENET_MAC
  470. {
  471. u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
  472. u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
  473. if (speed == _1000BASET)
  474. ecr |= FEC_ECNTRL_SPEED;
  475. else if (speed != _100BASET)
  476. rcr |= FEC_RCNTRL_RMII_10T;
  477. writel(ecr, &fec->eth->ecntrl);
  478. writel(rcr, &fec->eth->r_cntrl);
  479. }
  480. #endif
  481. debug("%s:Speed=%i\n", __func__, speed);
  482. /* Enable SmartDMA receive task */
  483. fec_rx_task_enable(fec);
  484. udelay(100000);
  485. return 0;
  486. }
  487. #ifdef CONFIG_DM_ETH
  488. static int fecmxc_init(struct udevice *dev)
  489. #else
  490. static int fec_init(struct eth_device *dev, bd_t *bd)
  491. #endif
  492. {
  493. #ifdef CONFIG_DM_ETH
  494. struct fec_priv *fec = dev_get_priv(dev);
  495. #else
  496. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  497. #endif
  498. u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
  499. u8 *i;
  500. ulong addr;
  501. /* Initialize MAC address */
  502. #ifdef CONFIG_DM_ETH
  503. fecmxc_set_hwaddr(dev);
  504. #else
  505. fec_set_hwaddr(dev);
  506. #endif
  507. /* Setup transmit descriptors, there are two in total. */
  508. fec_tbd_init(fec);
  509. /* Setup receive descriptors. */
  510. fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
  511. fec_reg_setup(fec);
  512. if (fec->xcv_type != SEVENWIRE)
  513. fec_mii_setspeed(fec->bus->priv);
  514. /* Set Opcode/Pause Duration Register */
  515. writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
  516. writel(0x2, &fec->eth->x_wmrk);
  517. /* Set multicast address filter */
  518. writel(0x00000000, &fec->eth->gaddr1);
  519. writel(0x00000000, &fec->eth->gaddr2);
  520. /* Do not access reserved register */
  521. if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
  522. /* clear MIB RAM */
  523. for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
  524. writel(0, i);
  525. /* FIFO receive start register */
  526. writel(0x520, &fec->eth->r_fstart);
  527. }
  528. /* size and address of each buffer */
  529. writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
  530. addr = (ulong)fec->tbd_base;
  531. writel((uint32_t)addr, &fec->eth->etdsr);
  532. addr = (ulong)fec->rbd_base;
  533. writel((uint32_t)addr, &fec->eth->erdsr);
  534. #ifndef CONFIG_PHYLIB
  535. if (fec->xcv_type != SEVENWIRE)
  536. miiphy_restart_aneg(dev);
  537. #endif
  538. fec_open(dev);
  539. return 0;
  540. }
  541. /**
  542. * Halt the FEC engine
  543. * @param[in] dev Our device to handle
  544. */
  545. #ifdef CONFIG_DM_ETH
  546. static void fecmxc_halt(struct udevice *dev)
  547. #else
  548. static void fec_halt(struct eth_device *dev)
  549. #endif
  550. {
  551. #ifdef CONFIG_DM_ETH
  552. struct fec_priv *fec = dev_get_priv(dev);
  553. #else
  554. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  555. #endif
  556. int counter = 0xffff;
  557. /* issue graceful stop command to the FEC transmitter if necessary */
  558. writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
  559. &fec->eth->x_cntrl);
  560. debug("eth_halt: wait for stop regs\n");
  561. /* wait for graceful stop to register */
  562. while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
  563. udelay(1);
  564. /* Disable SmartDMA tasks */
  565. fec_tx_task_disable(fec);
  566. fec_rx_task_disable(fec);
  567. /*
  568. * Disable the Ethernet Controller
  569. * Note: this will also reset the BD index counter!
  570. */
  571. writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
  572. &fec->eth->ecntrl);
  573. fec->rbd_index = 0;
  574. fec->tbd_index = 0;
  575. debug("eth_halt: done\n");
  576. }
  577. /**
  578. * Transmit one frame
  579. * @param[in] dev Our ethernet device to handle
  580. * @param[in] packet Pointer to the data to be transmitted
  581. * @param[in] length Data count in bytes
  582. * @return 0 on success
  583. */
  584. #ifdef CONFIG_DM_ETH
  585. static int fecmxc_send(struct udevice *dev, void *packet, int length)
  586. #else
  587. static int fec_send(struct eth_device *dev, void *packet, int length)
  588. #endif
  589. {
  590. unsigned int status;
  591. u32 size;
  592. ulong addr, end;
  593. int timeout = FEC_XFER_TIMEOUT;
  594. int ret = 0;
  595. /*
  596. * This routine transmits one frame. This routine only accepts
  597. * 6-byte Ethernet addresses.
  598. */
  599. #ifdef CONFIG_DM_ETH
  600. struct fec_priv *fec = dev_get_priv(dev);
  601. #else
  602. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  603. #endif
  604. /*
  605. * Check for valid length of data.
  606. */
  607. if ((length > 1500) || (length <= 0)) {
  608. printf("Payload (%d) too large\n", length);
  609. return -1;
  610. }
  611. /*
  612. * Setup the transmit buffer. We are always using the first buffer for
  613. * transmission, the second will be empty and only used to stop the DMA
  614. * engine. We also flush the packet to RAM here to avoid cache trouble.
  615. */
  616. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  617. swap_packet((uint32_t *)packet, length);
  618. #endif
  619. addr = (ulong)packet;
  620. end = roundup(addr + length, ARCH_DMA_MINALIGN);
  621. addr &= ~(ARCH_DMA_MINALIGN - 1);
  622. flush_dcache_range(addr, end);
  623. writew(length, &fec->tbd_base[fec->tbd_index].data_length);
  624. writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
  625. /*
  626. * update BD's status now
  627. * This block:
  628. * - is always the last in a chain (means no chain)
  629. * - should transmitt the CRC
  630. * - might be the last BD in the list, so the address counter should
  631. * wrap (-> keep the WRAP flag)
  632. */
  633. status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
  634. status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  635. writew(status, &fec->tbd_base[fec->tbd_index].status);
  636. /*
  637. * Flush data cache. This code flushes both TX descriptors to RAM.
  638. * After this code, the descriptors will be safely in RAM and we
  639. * can start DMA.
  640. */
  641. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  642. addr = (ulong)fec->tbd_base;
  643. flush_dcache_range(addr, addr + size);
  644. /*
  645. * Below we read the DMA descriptor's last four bytes back from the
  646. * DRAM. This is important in order to make sure that all WRITE
  647. * operations on the bus that were triggered by previous cache FLUSH
  648. * have completed.
  649. *
  650. * Otherwise, on MX28, it is possible to observe a corruption of the
  651. * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
  652. * for the bus structure of MX28. The scenario is as follows:
  653. *
  654. * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
  655. * to DRAM due to flush_dcache_range()
  656. * 2) ARM core writes the FEC registers via AHB_ARB2
  657. * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
  658. *
  659. * Note that 2) does sometimes finish before 1) due to reordering of
  660. * WRITE accesses on the AHB bus, therefore triggering 3) before the
  661. * DMA descriptor is fully written into DRAM. This results in occasional
  662. * corruption of the DMA descriptor.
  663. */
  664. readl(addr + size - 4);
  665. /* Enable SmartDMA transmit task */
  666. fec_tx_task_enable(fec);
  667. /*
  668. * Wait until frame is sent. On each turn of the wait cycle, we must
  669. * invalidate data cache to see what's really in RAM. Also, we need
  670. * barrier here.
  671. */
  672. while (--timeout) {
  673. if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
  674. break;
  675. }
  676. if (!timeout) {
  677. ret = -EINVAL;
  678. goto out;
  679. }
  680. /*
  681. * The TDAR bit is cleared when the descriptors are all out from TX
  682. * but on mx6solox we noticed that the READY bit is still not cleared
  683. * right after TDAR.
  684. * These are two distinct signals, and in IC simulation, we found that
  685. * TDAR always gets cleared prior than the READY bit of last BD becomes
  686. * cleared.
  687. * In mx6solox, we use a later version of FEC IP. It looks like that
  688. * this intrinsic behaviour of TDAR bit has changed in this newer FEC
  689. * version.
  690. *
  691. * Fix this by polling the READY bit of BD after the TDAR polling,
  692. * which covers the mx6solox case and does not harm the other SoCs.
  693. */
  694. timeout = FEC_XFER_TIMEOUT;
  695. while (--timeout) {
  696. invalidate_dcache_range(addr, addr + size);
  697. if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
  698. FEC_TBD_READY))
  699. break;
  700. }
  701. if (!timeout)
  702. ret = -EINVAL;
  703. out:
  704. debug("fec_send: status 0x%x index %d ret %i\n",
  705. readw(&fec->tbd_base[fec->tbd_index].status),
  706. fec->tbd_index, ret);
  707. /* for next transmission use the other buffer */
  708. if (fec->tbd_index)
  709. fec->tbd_index = 0;
  710. else
  711. fec->tbd_index = 1;
  712. return ret;
  713. }
  714. /**
  715. * Pull one frame from the card
  716. * @param[in] dev Our ethernet device to handle
  717. * @return Length of packet read
  718. */
  719. #ifdef CONFIG_DM_ETH
  720. static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
  721. #else
  722. static int fec_recv(struct eth_device *dev)
  723. #endif
  724. {
  725. #ifdef CONFIG_DM_ETH
  726. struct fec_priv *fec = dev_get_priv(dev);
  727. #else
  728. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  729. #endif
  730. struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
  731. unsigned long ievent;
  732. int frame_length, len = 0;
  733. uint16_t bd_status;
  734. ulong addr, size, end;
  735. int i;
  736. #ifdef CONFIG_DM_ETH
  737. *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
  738. if (*packetp == 0) {
  739. printf("%s: error allocating packetp\n", __func__);
  740. return -ENOMEM;
  741. }
  742. #else
  743. ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
  744. #endif
  745. /* Check if any critical events have happened */
  746. ievent = readl(&fec->eth->ievent);
  747. writel(ievent, &fec->eth->ievent);
  748. debug("fec_recv: ievent 0x%lx\n", ievent);
  749. if (ievent & FEC_IEVENT_BABR) {
  750. #ifdef CONFIG_DM_ETH
  751. fecmxc_halt(dev);
  752. fecmxc_init(dev);
  753. #else
  754. fec_halt(dev);
  755. fec_init(dev, fec->bd);
  756. #endif
  757. printf("some error: 0x%08lx\n", ievent);
  758. return 0;
  759. }
  760. if (ievent & FEC_IEVENT_HBERR) {
  761. /* Heartbeat error */
  762. writel(0x00000001 | readl(&fec->eth->x_cntrl),
  763. &fec->eth->x_cntrl);
  764. }
  765. if (ievent & FEC_IEVENT_GRA) {
  766. /* Graceful stop complete */
  767. if (readl(&fec->eth->x_cntrl) & 0x00000001) {
  768. #ifdef CONFIG_DM_ETH
  769. fecmxc_halt(dev);
  770. #else
  771. fec_halt(dev);
  772. #endif
  773. writel(~0x00000001 & readl(&fec->eth->x_cntrl),
  774. &fec->eth->x_cntrl);
  775. #ifdef CONFIG_DM_ETH
  776. fecmxc_init(dev);
  777. #else
  778. fec_init(dev, fec->bd);
  779. #endif
  780. }
  781. }
  782. /*
  783. * Read the buffer status. Before the status can be read, the data cache
  784. * must be invalidated, because the data in RAM might have been changed
  785. * by DMA. The descriptors are properly aligned to cachelines so there's
  786. * no need to worry they'd overlap.
  787. *
  788. * WARNING: By invalidating the descriptor here, we also invalidate
  789. * the descriptors surrounding this one. Therefore we can NOT change the
  790. * contents of this descriptor nor the surrounding ones. The problem is
  791. * that in order to mark the descriptor as processed, we need to change
  792. * the descriptor. The solution is to mark the whole cache line when all
  793. * descriptors in the cache line are processed.
  794. */
  795. addr = (ulong)rbd;
  796. addr &= ~(ARCH_DMA_MINALIGN - 1);
  797. size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  798. invalidate_dcache_range(addr, addr + size);
  799. bd_status = readw(&rbd->status);
  800. debug("fec_recv: status 0x%x\n", bd_status);
  801. if (!(bd_status & FEC_RBD_EMPTY)) {
  802. if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
  803. ((readw(&rbd->data_length) - 4) > 14)) {
  804. /* Get buffer address and size */
  805. addr = readl(&rbd->data_pointer);
  806. frame_length = readw(&rbd->data_length) - 4;
  807. /* Invalidate data cache over the buffer */
  808. end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
  809. addr &= ~(ARCH_DMA_MINALIGN - 1);
  810. invalidate_dcache_range(addr, end);
  811. /* Fill the buffer and pass it to upper layers */
  812. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  813. swap_packet((uint32_t *)addr, frame_length);
  814. #endif
  815. #ifdef CONFIG_DM_ETH
  816. memcpy(*packetp, (char *)addr, frame_length);
  817. #else
  818. memcpy(buff, (char *)addr, frame_length);
  819. net_process_received_packet(buff, frame_length);
  820. #endif
  821. len = frame_length;
  822. } else {
  823. if (bd_status & FEC_RBD_ERR)
  824. debug("error frame: 0x%08lx 0x%08x\n",
  825. addr, bd_status);
  826. }
  827. /*
  828. * Free the current buffer, restart the engine and move forward
  829. * to the next buffer. Here we check if the whole cacheline of
  830. * descriptors was already processed and if so, we mark it free
  831. * as whole.
  832. */
  833. size = RXDESC_PER_CACHELINE - 1;
  834. if ((fec->rbd_index & size) == size) {
  835. i = fec->rbd_index - size;
  836. addr = (ulong)&fec->rbd_base[i];
  837. for (; i <= fec->rbd_index ; i++) {
  838. fec_rbd_clean(i == (FEC_RBD_NUM - 1),
  839. &fec->rbd_base[i]);
  840. }
  841. flush_dcache_range(addr,
  842. addr + ARCH_DMA_MINALIGN);
  843. }
  844. fec_rx_task_enable(fec);
  845. fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
  846. }
  847. debug("fec_recv: stop\n");
  848. return len;
  849. }
  850. static void fec_set_dev_name(char *dest, int dev_id)
  851. {
  852. sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
  853. }
  854. static int fec_alloc_descs(struct fec_priv *fec)
  855. {
  856. unsigned int size;
  857. int i;
  858. uint8_t *data;
  859. ulong addr;
  860. /* Allocate TX descriptors. */
  861. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  862. fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
  863. if (!fec->tbd_base)
  864. goto err_tx;
  865. /* Allocate RX descriptors. */
  866. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  867. fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
  868. if (!fec->rbd_base)
  869. goto err_rx;
  870. memset(fec->rbd_base, 0, size);
  871. /* Allocate RX buffers. */
  872. /* Maximum RX buffer size. */
  873. size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
  874. for (i = 0; i < FEC_RBD_NUM; i++) {
  875. data = memalign(FEC_DMA_RX_MINALIGN, size);
  876. if (!data) {
  877. printf("%s: error allocating rxbuf %d\n", __func__, i);
  878. goto err_ring;
  879. }
  880. memset(data, 0, size);
  881. addr = (ulong)data;
  882. fec->rbd_base[i].data_pointer = (uint32_t)addr;
  883. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  884. fec->rbd_base[i].data_length = 0;
  885. /* Flush the buffer to memory. */
  886. flush_dcache_range(addr, addr + size);
  887. }
  888. /* Mark the last RBD to close the ring. */
  889. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  890. fec->rbd_index = 0;
  891. fec->tbd_index = 0;
  892. return 0;
  893. err_ring:
  894. for (; i >= 0; i--) {
  895. addr = fec->rbd_base[i].data_pointer;
  896. free((void *)addr);
  897. }
  898. free(fec->rbd_base);
  899. err_rx:
  900. free(fec->tbd_base);
  901. err_tx:
  902. return -ENOMEM;
  903. }
  904. static void fec_free_descs(struct fec_priv *fec)
  905. {
  906. int i;
  907. ulong addr;
  908. for (i = 0; i < FEC_RBD_NUM; i++) {
  909. addr = fec->rbd_base[i].data_pointer;
  910. free((void *)addr);
  911. }
  912. free(fec->rbd_base);
  913. free(fec->tbd_base);
  914. }
  915. struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
  916. {
  917. struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
  918. struct mii_dev *bus;
  919. int ret;
  920. bus = mdio_alloc();
  921. if (!bus) {
  922. printf("mdio_alloc failed\n");
  923. return NULL;
  924. }
  925. bus->read = fec_phy_read;
  926. bus->write = fec_phy_write;
  927. bus->priv = eth;
  928. fec_set_dev_name(bus->name, dev_id);
  929. ret = mdio_register(bus);
  930. if (ret) {
  931. printf("mdio_register failed\n");
  932. free(bus);
  933. return NULL;
  934. }
  935. fec_mii_setspeed(eth);
  936. return bus;
  937. }
  938. #ifndef CONFIG_DM_ETH
  939. #ifdef CONFIG_PHYLIB
  940. int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
  941. struct mii_dev *bus, struct phy_device *phydev)
  942. #else
  943. static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
  944. struct mii_dev *bus, int phy_id)
  945. #endif
  946. {
  947. struct eth_device *edev;
  948. struct fec_priv *fec;
  949. unsigned char ethaddr[6];
  950. char mac[16];
  951. uint32_t start;
  952. int ret = 0;
  953. /* create and fill edev struct */
  954. edev = (struct eth_device *)malloc(sizeof(struct eth_device));
  955. if (!edev) {
  956. puts("fec_mxc: not enough malloc memory for eth_device\n");
  957. ret = -ENOMEM;
  958. goto err1;
  959. }
  960. fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
  961. if (!fec) {
  962. puts("fec_mxc: not enough malloc memory for fec_priv\n");
  963. ret = -ENOMEM;
  964. goto err2;
  965. }
  966. memset(edev, 0, sizeof(*edev));
  967. memset(fec, 0, sizeof(*fec));
  968. ret = fec_alloc_descs(fec);
  969. if (ret)
  970. goto err3;
  971. edev->priv = fec;
  972. edev->init = fec_init;
  973. edev->send = fec_send;
  974. edev->recv = fec_recv;
  975. edev->halt = fec_halt;
  976. edev->write_hwaddr = fec_set_hwaddr;
  977. fec->eth = (struct ethernet_regs *)(ulong)base_addr;
  978. fec->bd = bd;
  979. fec->xcv_type = CONFIG_FEC_XCV_TYPE;
  980. /* Reset chip. */
  981. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
  982. start = get_timer(0);
  983. while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
  984. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  985. printf("FEC MXC: Timeout resetting chip\n");
  986. goto err4;
  987. }
  988. udelay(10);
  989. }
  990. fec_reg_setup(fec);
  991. fec_set_dev_name(edev->name, dev_id);
  992. fec->dev_id = (dev_id == -1) ? 0 : dev_id;
  993. fec->bus = bus;
  994. fec_mii_setspeed(bus->priv);
  995. #ifdef CONFIG_PHYLIB
  996. fec->phydev = phydev;
  997. phy_connect_dev(phydev, edev);
  998. /* Configure phy */
  999. phy_config(phydev);
  1000. #else
  1001. fec->phy_id = phy_id;
  1002. #endif
  1003. eth_register(edev);
  1004. /* only support one eth device, the index number pointed by dev_id */
  1005. edev->index = fec->dev_id;
  1006. if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
  1007. debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
  1008. memcpy(edev->enetaddr, ethaddr, 6);
  1009. if (fec->dev_id)
  1010. sprintf(mac, "eth%daddr", fec->dev_id);
  1011. else
  1012. strcpy(mac, "ethaddr");
  1013. if (!env_get(mac))
  1014. eth_env_set_enetaddr(mac, ethaddr);
  1015. }
  1016. return ret;
  1017. err4:
  1018. fec_free_descs(fec);
  1019. err3:
  1020. free(fec);
  1021. err2:
  1022. free(edev);
  1023. err1:
  1024. return ret;
  1025. }
  1026. int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
  1027. {
  1028. uint32_t base_mii;
  1029. struct mii_dev *bus = NULL;
  1030. #ifdef CONFIG_PHYLIB
  1031. struct phy_device *phydev = NULL;
  1032. #endif
  1033. int ret;
  1034. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1035. /*
  1036. * The i.MX28 has two ethernet interfaces, but they are not equal.
  1037. * Only the first one can access the MDIO bus.
  1038. */
  1039. base_mii = CONFIG_FEC_MXC_MDIO_BASE;
  1040. #else
  1041. base_mii = addr;
  1042. #endif
  1043. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  1044. bus = fec_get_miibus(base_mii, dev_id);
  1045. if (!bus)
  1046. return -ENOMEM;
  1047. #ifdef CONFIG_PHYLIB
  1048. phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
  1049. if (!phydev) {
  1050. mdio_unregister(bus);
  1051. free(bus);
  1052. return -ENOMEM;
  1053. }
  1054. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  1055. #else
  1056. ret = fec_probe(bd, dev_id, addr, bus, phy_id);
  1057. #endif
  1058. if (ret) {
  1059. #ifdef CONFIG_PHYLIB
  1060. free(phydev);
  1061. #endif
  1062. mdio_unregister(bus);
  1063. free(bus);
  1064. }
  1065. return ret;
  1066. }
  1067. #ifdef CONFIG_FEC_MXC_PHYADDR
  1068. int fecmxc_initialize(bd_t *bd)
  1069. {
  1070. return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
  1071. IMX_FEC_BASE);
  1072. }
  1073. #endif
  1074. #ifndef CONFIG_PHYLIB
  1075. int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
  1076. {
  1077. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  1078. fec->mii_postcall = cb;
  1079. return 0;
  1080. }
  1081. #endif
  1082. #else
  1083. static int fecmxc_read_rom_hwaddr(struct udevice *dev)
  1084. {
  1085. struct fec_priv *priv = dev_get_priv(dev);
  1086. struct eth_pdata *pdata = dev_get_platdata(dev);
  1087. return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
  1088. }
  1089. static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
  1090. {
  1091. if (packet)
  1092. free(packet);
  1093. return 0;
  1094. }
  1095. static const struct eth_ops fecmxc_ops = {
  1096. .start = fecmxc_init,
  1097. .send = fecmxc_send,
  1098. .recv = fecmxc_recv,
  1099. .free_pkt = fecmxc_free_pkt,
  1100. .stop = fecmxc_halt,
  1101. .write_hwaddr = fecmxc_set_hwaddr,
  1102. .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
  1103. };
  1104. static int device_get_phy_addr(struct udevice *dev)
  1105. {
  1106. struct ofnode_phandle_args phandle_args;
  1107. int reg;
  1108. if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  1109. &phandle_args)) {
  1110. debug("Failed to find phy-handle");
  1111. return -ENODEV;
  1112. }
  1113. reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
  1114. return reg;
  1115. }
  1116. static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
  1117. {
  1118. struct phy_device *phydev;
  1119. int addr;
  1120. addr = device_get_phy_addr(dev);
  1121. #ifdef CONFIG_FEC_MXC_PHYADDR
  1122. addr = CONFIG_FEC_MXC_PHYADDR;
  1123. #endif
  1124. phydev = phy_connect(priv->bus, addr, dev, priv->interface);
  1125. if (!phydev)
  1126. return -ENODEV;
  1127. priv->phydev = phydev;
  1128. phy_config(phydev);
  1129. return 0;
  1130. }
  1131. #if CONFIG_IS_ENABLED(DM_GPIO)
  1132. /* FEC GPIO reset */
  1133. static void fec_gpio_reset(struct fec_priv *priv)
  1134. {
  1135. debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
  1136. if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
  1137. dm_gpio_set_value(&priv->phy_reset_gpio, 1);
  1138. mdelay(priv->reset_delay);
  1139. dm_gpio_set_value(&priv->phy_reset_gpio, 0);
  1140. if (priv->reset_post_delay)
  1141. mdelay(priv->reset_post_delay);
  1142. }
  1143. }
  1144. #endif
  1145. static int fecmxc_probe(struct udevice *dev)
  1146. {
  1147. struct eth_pdata *pdata = dev_get_platdata(dev);
  1148. struct fec_priv *priv = dev_get_priv(dev);
  1149. struct mii_dev *bus = NULL;
  1150. uint32_t start;
  1151. int ret;
  1152. if (IS_ENABLED(CONFIG_IMX8)) {
  1153. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1154. if (ret < 0) {
  1155. debug("Can't get FEC ipg clk: %d\n", ret);
  1156. return ret;
  1157. }
  1158. ret = clk_enable(&priv->ipg_clk);
  1159. if (ret < 0) {
  1160. debug("Can't enable FEC ipg clk: %d\n", ret);
  1161. return ret;
  1162. }
  1163. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1164. } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
  1165. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1166. if (ret < 0) {
  1167. debug("Can't get FEC ipg clk: %d\n", ret);
  1168. return ret;
  1169. }
  1170. ret = clk_enable(&priv->ipg_clk);
  1171. if(ret)
  1172. return ret;
  1173. ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
  1174. if (ret < 0) {
  1175. debug("Can't get FEC ahb clk: %d\n", ret);
  1176. return ret;
  1177. }
  1178. ret = clk_enable(&priv->ahb_clk);
  1179. if (ret)
  1180. return ret;
  1181. ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
  1182. if (!ret) {
  1183. ret = clk_enable(&priv->clk_enet_out);
  1184. if (ret)
  1185. return ret;
  1186. }
  1187. ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
  1188. if (!ret) {
  1189. ret = clk_enable(&priv->clk_ref);
  1190. if (ret)
  1191. return ret;
  1192. }
  1193. ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
  1194. if (!ret) {
  1195. ret = clk_enable(&priv->clk_ptp);
  1196. if (ret)
  1197. return ret;
  1198. }
  1199. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1200. }
  1201. ret = fec_alloc_descs(priv);
  1202. if (ret)
  1203. return ret;
  1204. #ifdef CONFIG_DM_REGULATOR
  1205. if (priv->phy_supply) {
  1206. ret = regulator_set_enable(priv->phy_supply, true);
  1207. if (ret) {
  1208. printf("%s: Error enabling phy supply\n", dev->name);
  1209. return ret;
  1210. }
  1211. }
  1212. #endif
  1213. #if CONFIG_IS_ENABLED(DM_GPIO)
  1214. fec_gpio_reset(priv);
  1215. #endif
  1216. /* Reset chip. */
  1217. writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
  1218. &priv->eth->ecntrl);
  1219. start = get_timer(0);
  1220. while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
  1221. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  1222. printf("FEC MXC: Timeout reseting chip\n");
  1223. goto err_timeout;
  1224. }
  1225. udelay(10);
  1226. }
  1227. fec_reg_setup(priv);
  1228. priv->dev_id = dev->seq;
  1229. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1230. bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
  1231. #else
  1232. bus = fec_get_miibus((ulong)priv->eth, dev->seq);
  1233. #endif
  1234. if (!bus) {
  1235. ret = -ENOMEM;
  1236. goto err_mii;
  1237. }
  1238. priv->bus = bus;
  1239. priv->interface = pdata->phy_interface;
  1240. switch (priv->interface) {
  1241. case PHY_INTERFACE_MODE_MII:
  1242. priv->xcv_type = MII100;
  1243. break;
  1244. case PHY_INTERFACE_MODE_RMII:
  1245. priv->xcv_type = RMII;
  1246. break;
  1247. case PHY_INTERFACE_MODE_RGMII:
  1248. case PHY_INTERFACE_MODE_RGMII_ID:
  1249. case PHY_INTERFACE_MODE_RGMII_RXID:
  1250. case PHY_INTERFACE_MODE_RGMII_TXID:
  1251. priv->xcv_type = RGMII;
  1252. break;
  1253. default:
  1254. priv->xcv_type = CONFIG_FEC_XCV_TYPE;
  1255. printf("Unsupported interface type %d defaulting to %d\n",
  1256. priv->interface, priv->xcv_type);
  1257. break;
  1258. }
  1259. ret = fec_phy_init(priv, dev);
  1260. if (ret)
  1261. goto err_phy;
  1262. return 0;
  1263. err_phy:
  1264. mdio_unregister(bus);
  1265. free(bus);
  1266. err_mii:
  1267. err_timeout:
  1268. fec_free_descs(priv);
  1269. return ret;
  1270. }
  1271. static int fecmxc_remove(struct udevice *dev)
  1272. {
  1273. struct fec_priv *priv = dev_get_priv(dev);
  1274. free(priv->phydev);
  1275. fec_free_descs(priv);
  1276. mdio_unregister(priv->bus);
  1277. mdio_free(priv->bus);
  1278. #ifdef CONFIG_DM_REGULATOR
  1279. if (priv->phy_supply)
  1280. regulator_set_enable(priv->phy_supply, false);
  1281. #endif
  1282. return 0;
  1283. }
  1284. static int fecmxc_ofdata_to_platdata(struct udevice *dev)
  1285. {
  1286. int ret = 0;
  1287. struct eth_pdata *pdata = dev_get_platdata(dev);
  1288. struct fec_priv *priv = dev_get_priv(dev);
  1289. const char *phy_mode;
  1290. pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
  1291. priv->eth = (struct ethernet_regs *)pdata->iobase;
  1292. pdata->phy_interface = -1;
  1293. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1294. NULL);
  1295. if (phy_mode)
  1296. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1297. if (pdata->phy_interface == -1) {
  1298. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1299. return -EINVAL;
  1300. }
  1301. #ifdef CONFIG_DM_REGULATOR
  1302. device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  1303. #endif
  1304. #if CONFIG_IS_ENABLED(DM_GPIO)
  1305. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1306. &priv->phy_reset_gpio, GPIOD_IS_OUT);
  1307. if (ret < 0)
  1308. return 0; /* property is optional, don't return error! */
  1309. priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
  1310. if (priv->reset_delay > 1000) {
  1311. printf("FEC MXC: phy reset duration should be <= 1000ms\n");
  1312. /* property value wrong, use default value */
  1313. priv->reset_delay = 1;
  1314. }
  1315. priv->reset_post_delay = dev_read_u32_default(dev,
  1316. "phy-reset-post-delay",
  1317. 0);
  1318. if (priv->reset_post_delay > 1000) {
  1319. printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
  1320. /* property value wrong, use default value */
  1321. priv->reset_post_delay = 0;
  1322. }
  1323. #endif
  1324. return 0;
  1325. }
  1326. static const struct udevice_id fecmxc_ids[] = {
  1327. { .compatible = "fsl,imx28-fec" },
  1328. { .compatible = "fsl,imx6q-fec" },
  1329. { .compatible = "fsl,imx6sl-fec" },
  1330. { .compatible = "fsl,imx6sx-fec" },
  1331. { .compatible = "fsl,imx6ul-fec" },
  1332. { .compatible = "fsl,imx53-fec" },
  1333. { .compatible = "fsl,imx7d-fec" },
  1334. { .compatible = "fsl,mvf600-fec" },
  1335. { }
  1336. };
  1337. U_BOOT_DRIVER(fecmxc_gem) = {
  1338. .name = "fecmxc",
  1339. .id = UCLASS_ETH,
  1340. .of_match = fecmxc_ids,
  1341. .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
  1342. .probe = fecmxc_probe,
  1343. .remove = fecmxc_remove,
  1344. .ops = &fecmxc_ops,
  1345. .priv_auto_alloc_size = sizeof(struct fec_priv),
  1346. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1347. };
  1348. #endif