designware.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef _DW_ETH_H
  7. #define _DW_ETH_H
  8. #if CONFIG_IS_ENABLED(DM_GPIO)
  9. #include <asm-generic/gpio.h>
  10. #endif
  11. #define CONFIG_TX_DESCR_NUM 16
  12. #define CONFIG_RX_DESCR_NUM 16
  13. #define CONFIG_ETH_BUFSIZE 2048
  14. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  15. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  16. #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
  17. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  18. struct eth_mac_regs {
  19. u32 conf; /* 0x00 */
  20. u32 framefilt; /* 0x04 */
  21. u32 hashtablehigh; /* 0x08 */
  22. u32 hashtablelow; /* 0x0c */
  23. u32 miiaddr; /* 0x10 */
  24. u32 miidata; /* 0x14 */
  25. u32 flowcontrol; /* 0x18 */
  26. u32 vlantag; /* 0x1c */
  27. u32 version; /* 0x20 */
  28. u8 reserved_1[20];
  29. u32 intreg; /* 0x38 */
  30. u32 intmask; /* 0x3c */
  31. u32 macaddr0hi; /* 0x40 */
  32. u32 macaddr0lo; /* 0x44 */
  33. };
  34. /* MAC configuration register definitions */
  35. #define FRAMEBURSTENABLE (1 << 21)
  36. #define MII_PORTSELECT (1 << 15)
  37. #define FES_100 (1 << 14)
  38. #define DISABLERXOWN (1 << 13)
  39. #define FULLDPLXMODE (1 << 11)
  40. #define RXENABLE (1 << 2)
  41. #define TXENABLE (1 << 3)
  42. /* MII address register definitions */
  43. #define MII_BUSY (1 << 0)
  44. #define MII_WRITE (1 << 1)
  45. #define MII_CLKRANGE_60_100M (0)
  46. #define MII_CLKRANGE_100_150M (0x4)
  47. #define MII_CLKRANGE_20_35M (0x8)
  48. #define MII_CLKRANGE_35_60M (0xC)
  49. #define MII_CLKRANGE_150_250M (0x10)
  50. #define MII_CLKRANGE_250_300M (0x14)
  51. #define MIIADDRSHIFT (11)
  52. #define MIIREGSHIFT (6)
  53. #define MII_REGMSK (0x1F << 6)
  54. #define MII_ADDRMSK (0x1F << 11)
  55. struct eth_dma_regs {
  56. u32 busmode; /* 0x00 */
  57. u32 txpolldemand; /* 0x04 */
  58. u32 rxpolldemand; /* 0x08 */
  59. u32 rxdesclistaddr; /* 0x0c */
  60. u32 txdesclistaddr; /* 0x10 */
  61. u32 status; /* 0x14 */
  62. u32 opmode; /* 0x18 */
  63. u32 intenable; /* 0x1c */
  64. u32 reserved1[2];
  65. u32 axibus; /* 0x28 */
  66. u32 reserved2[7];
  67. u32 currhosttxdesc; /* 0x48 */
  68. u32 currhostrxdesc; /* 0x4c */
  69. u32 currhosttxbuffaddr; /* 0x50 */
  70. u32 currhostrxbuffaddr; /* 0x54 */
  71. };
  72. #define DW_DMA_BASE_OFFSET (0x1000)
  73. /* Default DMA Burst length */
  74. #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
  75. #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
  76. #endif
  77. /* Bus mode register definitions */
  78. #define FIXEDBURST (1 << 16)
  79. #define PRIORXTX_41 (3 << 14)
  80. #define PRIORXTX_31 (2 << 14)
  81. #define PRIORXTX_21 (1 << 14)
  82. #define PRIORXTX_11 (0 << 14)
  83. #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
  84. #define RXHIGHPRIO (1 << 1)
  85. #define DMAMAC_SRST (1 << 0)
  86. /* Poll demand definitions */
  87. #define POLL_DATA (0xFFFFFFFF)
  88. /* Operation mode definitions */
  89. #define STOREFORWARD (1 << 21)
  90. #define FLUSHTXFIFO (1 << 20)
  91. #define TXSTART (1 << 13)
  92. #define TXSECONDFRAME (1 << 2)
  93. #define RXSTART (1 << 1)
  94. /* Descriptior related definitions */
  95. #define MAC_MAX_FRAME_SZ (1600)
  96. struct dmamacdescr {
  97. u32 txrx_status;
  98. u32 dmamac_cntl;
  99. u32 dmamac_addr;
  100. u32 dmamac_next;
  101. } __aligned(ARCH_DMA_MINALIGN);
  102. /*
  103. * txrx_status definitions
  104. */
  105. /* tx status bits definitions */
  106. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  107. #define DESC_TXSTS_OWNBYDMA (1 << 31)
  108. #define DESC_TXSTS_TXINT (1 << 30)
  109. #define DESC_TXSTS_TXLAST (1 << 29)
  110. #define DESC_TXSTS_TXFIRST (1 << 28)
  111. #define DESC_TXSTS_TXCRCDIS (1 << 27)
  112. #define DESC_TXSTS_TXPADDIS (1 << 26)
  113. #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
  114. #define DESC_TXSTS_TXRINGEND (1 << 21)
  115. #define DESC_TXSTS_TXCHAIN (1 << 20)
  116. #define DESC_TXSTS_MSK (0x1FFFF << 0)
  117. #else
  118. #define DESC_TXSTS_OWNBYDMA (1 << 31)
  119. #define DESC_TXSTS_MSK (0x1FFFF << 0)
  120. #endif
  121. /* rx status bits definitions */
  122. #define DESC_RXSTS_OWNBYDMA (1 << 31)
  123. #define DESC_RXSTS_DAFILTERFAIL (1 << 30)
  124. #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
  125. #define DESC_RXSTS_FRMLENSHFT (16)
  126. #define DESC_RXSTS_ERROR (1 << 15)
  127. #define DESC_RXSTS_RXTRUNCATED (1 << 14)
  128. #define DESC_RXSTS_SAFILTERFAIL (1 << 13)
  129. #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
  130. #define DESC_RXSTS_RXDAMAGED (1 << 11)
  131. #define DESC_RXSTS_RXVLANTAG (1 << 10)
  132. #define DESC_RXSTS_RXFIRST (1 << 9)
  133. #define DESC_RXSTS_RXLAST (1 << 8)
  134. #define DESC_RXSTS_RXIPC_GIANT (1 << 7)
  135. #define DESC_RXSTS_RXCOLLISION (1 << 6)
  136. #define DESC_RXSTS_RXFRAMEETHER (1 << 5)
  137. #define DESC_RXSTS_RXWATCHDOG (1 << 4)
  138. #define DESC_RXSTS_RXMIIERROR (1 << 3)
  139. #define DESC_RXSTS_RXDRIBBLING (1 << 2)
  140. #define DESC_RXSTS_RXCRC (1 << 1)
  141. /*
  142. * dmamac_cntl definitions
  143. */
  144. /* tx control bits definitions */
  145. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  146. #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
  147. #define DESC_TXCTRL_SIZE1SHFT (0)
  148. #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
  149. #define DESC_TXCTRL_SIZE2SHFT (16)
  150. #else
  151. #define DESC_TXCTRL_TXINT (1 << 31)
  152. #define DESC_TXCTRL_TXLAST (1 << 30)
  153. #define DESC_TXCTRL_TXFIRST (1 << 29)
  154. #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
  155. #define DESC_TXCTRL_TXCRCDIS (1 << 26)
  156. #define DESC_TXCTRL_TXRINGEND (1 << 25)
  157. #define DESC_TXCTRL_TXCHAIN (1 << 24)
  158. #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
  159. #define DESC_TXCTRL_SIZE1SHFT (0)
  160. #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
  161. #define DESC_TXCTRL_SIZE2SHFT (11)
  162. #endif
  163. /* rx control bits definitions */
  164. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  165. #define DESC_RXCTRL_RXINTDIS (1 << 31)
  166. #define DESC_RXCTRL_RXRINGEND (1 << 15)
  167. #define DESC_RXCTRL_RXCHAIN (1 << 14)
  168. #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
  169. #define DESC_RXCTRL_SIZE1SHFT (0)
  170. #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
  171. #define DESC_RXCTRL_SIZE2SHFT (16)
  172. #else
  173. #define DESC_RXCTRL_RXINTDIS (1 << 31)
  174. #define DESC_RXCTRL_RXRINGEND (1 << 25)
  175. #define DESC_RXCTRL_RXCHAIN (1 << 24)
  176. #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
  177. #define DESC_RXCTRL_SIZE1SHFT (0)
  178. #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
  179. #define DESC_RXCTRL_SIZE2SHFT (11)
  180. #endif
  181. struct dw_eth_dev {
  182. struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
  183. struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
  184. char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  185. char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  186. u32 interface;
  187. u32 max_speed;
  188. u32 tx_currdescnum;
  189. u32 rx_currdescnum;
  190. struct eth_mac_regs *mac_regs_p;
  191. struct eth_dma_regs *dma_regs_p;
  192. #ifndef CONFIG_DM_ETH
  193. struct eth_device *dev;
  194. #endif
  195. #if CONFIG_IS_ENABLED(DM_GPIO)
  196. struct gpio_desc reset_gpio;
  197. #endif
  198. #ifdef CONFIG_CLK
  199. struct clk *clocks; /* clock list */
  200. int clock_count; /* number of clock in clock list */
  201. #endif
  202. struct phy_device *phydev;
  203. struct mii_dev *bus;
  204. };
  205. #ifdef CONFIG_DM_ETH
  206. int designware_eth_ofdata_to_platdata(struct udevice *dev);
  207. int designware_eth_probe(struct udevice *dev);
  208. extern const struct eth_ops designware_eth_ops;
  209. struct dw_eth_pdata {
  210. struct eth_pdata eth_pdata;
  211. u32 reset_delays[3];
  212. };
  213. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
  214. int designware_eth_enable(struct dw_eth_dev *priv);
  215. int designware_eth_send(struct udevice *dev, void *packet, int length);
  216. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
  217. int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
  218. int length);
  219. void designware_eth_stop(struct udevice *dev);
  220. int designware_eth_write_hwaddr(struct udevice *dev);
  221. #endif
  222. #endif