omap_hsmmc.c 50 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. * Sukumar Ghorai <s-ghorai@ti.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation's version 2 of
  12. * the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <config.h>
  25. #include <common.h>
  26. #include <cpu_func.h>
  27. #include <malloc.h>
  28. #include <memalign.h>
  29. #include <mmc.h>
  30. #include <part.h>
  31. #include <i2c.h>
  32. #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33. #include <palmas.h>
  34. #endif
  35. #include <asm/io.h>
  36. #include <asm/arch/mmc_host_def.h>
  37. #ifdef CONFIG_OMAP54XX
  38. #include <asm/arch/mux_dra7xx.h>
  39. #include <asm/arch/dra7xx_iodelay.h>
  40. #endif
  41. #if !defined(CONFIG_SOC_KEYSTONE)
  42. #include <asm/gpio.h>
  43. #include <asm/arch/sys_proto.h>
  44. #endif
  45. #ifdef CONFIG_MMC_OMAP36XX_PINS
  46. #include <asm/arch/mux.h>
  47. #endif
  48. #include <dm.h>
  49. #include <power/regulator.h>
  50. #include <thermal.h>
  51. DECLARE_GLOBAL_DATA_PTR;
  52. /* simplify defines to OMAP_HSMMC_USE_GPIO */
  53. #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  54. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  55. #define OMAP_HSMMC_USE_GPIO
  56. #else
  57. #undef OMAP_HSMMC_USE_GPIO
  58. #endif
  59. /* common definitions for all OMAPs */
  60. #define SYSCTL_SRC (1 << 25)
  61. #define SYSCTL_SRD (1 << 26)
  62. #ifdef CONFIG_IODELAY_RECALIBRATION
  63. struct omap_hsmmc_pinctrl_state {
  64. struct pad_conf_entry *padconf;
  65. int npads;
  66. struct iodelay_cfg_entry *iodelay;
  67. int niodelays;
  68. };
  69. #endif
  70. struct omap_hsmmc_data {
  71. struct hsmmc *base_addr;
  72. #if !CONFIG_IS_ENABLED(DM_MMC)
  73. struct mmc_config cfg;
  74. #endif
  75. uint bus_width;
  76. uint clock;
  77. ushort last_cmd;
  78. #ifdef OMAP_HSMMC_USE_GPIO
  79. #if CONFIG_IS_ENABLED(DM_MMC)
  80. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  81. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  82. #else
  83. int cd_gpio;
  84. int wp_gpio;
  85. #endif
  86. #endif
  87. #if CONFIG_IS_ENABLED(DM_MMC)
  88. enum bus_mode mode;
  89. #endif
  90. u8 controller_flags;
  91. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  92. struct omap_hsmmc_adma_desc *adma_desc_table;
  93. uint desc_slot;
  94. #endif
  95. const char *hw_rev;
  96. struct udevice *pbias_supply;
  97. uint signal_voltage;
  98. #ifdef CONFIG_IODELAY_RECALIBRATION
  99. struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
  100. struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
  101. struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
  102. struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
  103. struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
  104. struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
  105. struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
  106. struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
  107. struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
  108. #endif
  109. };
  110. struct omap_mmc_of_data {
  111. u8 controller_flags;
  112. };
  113. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  114. struct omap_hsmmc_adma_desc {
  115. u8 attr;
  116. u8 reserved;
  117. u16 len;
  118. u32 addr;
  119. };
  120. #define ADMA_MAX_LEN 63488
  121. /* Decriptor table defines */
  122. #define ADMA_DESC_ATTR_VALID BIT(0)
  123. #define ADMA_DESC_ATTR_END BIT(1)
  124. #define ADMA_DESC_ATTR_INT BIT(2)
  125. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  126. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  127. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  128. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  129. #endif
  130. /* If we fail after 1 second wait, something is really bad */
  131. #define MAX_RETRY_MS 1000
  132. #define MMC_TIMEOUT_MS 20
  133. /* DMA transfers can take a long time if a lot a data is transferred.
  134. * The timeout must take in account the amount of data. Let's assume
  135. * that the time will never exceed 333 ms per MB (in other word we assume
  136. * that the bandwidth is always above 3MB/s).
  137. */
  138. #define DMA_TIMEOUT_PER_MB 333
  139. #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
  140. #define OMAP_HSMMC_NO_1_8_V BIT(1)
  141. #define OMAP_HSMMC_USE_ADMA BIT(2)
  142. #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
  143. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  144. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  145. unsigned int siz);
  146. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
  147. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
  148. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
  149. static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
  150. {
  151. #if CONFIG_IS_ENABLED(DM_MMC)
  152. return dev_get_priv(mmc->dev);
  153. #else
  154. return (struct omap_hsmmc_data *)mmc->priv;
  155. #endif
  156. }
  157. static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
  158. {
  159. #if CONFIG_IS_ENABLED(DM_MMC)
  160. struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
  161. return &plat->cfg;
  162. #else
  163. return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
  164. #endif
  165. }
  166. #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
  167. static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  168. {
  169. int ret;
  170. #if !CONFIG_IS_ENABLED(DM_GPIO)
  171. if (!gpio_is_valid(gpio))
  172. return -1;
  173. #endif
  174. ret = gpio_request(gpio, label);
  175. if (ret)
  176. return ret;
  177. ret = gpio_direction_input(gpio);
  178. if (ret)
  179. return ret;
  180. return gpio;
  181. }
  182. #endif
  183. static unsigned char mmc_board_init(struct mmc *mmc)
  184. {
  185. #if defined(CONFIG_OMAP34XX)
  186. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  187. t2_t *t2_base = (t2_t *)T2_BASE;
  188. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  189. u32 pbias_lite;
  190. #ifdef CONFIG_MMC_OMAP36XX_PINS
  191. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  192. #endif
  193. pbias_lite = readl(&t2_base->pbias_lite);
  194. pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
  195. #ifdef CONFIG_TARGET_OMAP3_CAIRO
  196. /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
  197. pbias_lite &= ~PBIASLITEVMODE0;
  198. #endif
  199. #ifdef CONFIG_TARGET_OMAP3_LOGIC
  200. /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
  201. pbias_lite &= ~PBIASLITEVMODE1;
  202. #endif
  203. #ifdef CONFIG_MMC_OMAP36XX_PINS
  204. if (get_cpu_family() == CPU_OMAP36XX) {
  205. /* Disable extended drain IO before changing PBIAS */
  206. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  207. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  208. }
  209. #endif
  210. writel(pbias_lite, &t2_base->pbias_lite);
  211. writel(pbias_lite | PBIASLITEPWRDNZ1 |
  212. PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  213. &t2_base->pbias_lite);
  214. #ifdef CONFIG_MMC_OMAP36XX_PINS
  215. if (get_cpu_family() == CPU_OMAP36XX)
  216. /* Enable extended drain IO after changing PBIAS */
  217. writel(wkup_ctrl |
  218. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  219. OMAP34XX_CTRL_WKUP_CTRL);
  220. #endif
  221. writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  222. &t2_base->devconf0);
  223. writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  224. &t2_base->devconf1);
  225. /* Change from default of 52MHz to 26MHz if necessary */
  226. if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
  227. writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
  228. &t2_base->ctl_prog_io1);
  229. writel(readl(&prcm_base->fclken1_core) |
  230. EN_MMC1 | EN_MMC2 | EN_MMC3,
  231. &prcm_base->fclken1_core);
  232. writel(readl(&prcm_base->iclken1_core) |
  233. EN_MMC1 | EN_MMC2 | EN_MMC3,
  234. &prcm_base->iclken1_core);
  235. #endif
  236. #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
  237. !CONFIG_IS_ENABLED(DM_REGULATOR)
  238. /* PBIAS config needed for MMC1 only */
  239. if (mmc_get_blk_desc(mmc)->devnum == 0)
  240. vmmc_pbias_config(LDO_VOLT_3V3);
  241. #endif
  242. return 0;
  243. }
  244. void mmc_init_stream(struct hsmmc *mmc_base)
  245. {
  246. ulong start;
  247. writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
  248. writel(MMC_CMD0, &mmc_base->cmd);
  249. start = get_timer(0);
  250. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  251. if (get_timer(0) - start > MAX_RETRY_MS) {
  252. printf("%s: timedout waiting for cc!\n", __func__);
  253. return;
  254. }
  255. }
  256. writel(CC_MASK, &mmc_base->stat)
  257. ;
  258. writel(MMC_CMD0, &mmc_base->cmd)
  259. ;
  260. start = get_timer(0);
  261. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  262. if (get_timer(0) - start > MAX_RETRY_MS) {
  263. printf("%s: timedout waiting for cc2!\n", __func__);
  264. return;
  265. }
  266. }
  267. writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
  268. }
  269. #if CONFIG_IS_ENABLED(DM_MMC)
  270. #ifdef CONFIG_IODELAY_RECALIBRATION
  271. static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
  272. {
  273. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  274. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  275. switch (priv->mode) {
  276. case MMC_HS_200:
  277. pinctrl_state = priv->hs200_1_8v_pinctrl_state;
  278. break;
  279. case UHS_SDR104:
  280. pinctrl_state = priv->sdr104_pinctrl_state;
  281. break;
  282. case UHS_SDR50:
  283. pinctrl_state = priv->sdr50_pinctrl_state;
  284. break;
  285. case UHS_DDR50:
  286. pinctrl_state = priv->ddr50_pinctrl_state;
  287. break;
  288. case UHS_SDR25:
  289. pinctrl_state = priv->sdr25_pinctrl_state;
  290. break;
  291. case UHS_SDR12:
  292. pinctrl_state = priv->sdr12_pinctrl_state;
  293. break;
  294. case SD_HS:
  295. case MMC_HS:
  296. case MMC_HS_52:
  297. pinctrl_state = priv->hs_pinctrl_state;
  298. break;
  299. case MMC_DDR_52:
  300. pinctrl_state = priv->ddr_1_8v_pinctrl_state;
  301. default:
  302. pinctrl_state = priv->default_pinctrl_state;
  303. break;
  304. }
  305. if (!pinctrl_state)
  306. pinctrl_state = priv->default_pinctrl_state;
  307. if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
  308. if (pinctrl_state->iodelay)
  309. late_recalibrate_iodelay(pinctrl_state->padconf,
  310. pinctrl_state->npads,
  311. pinctrl_state->iodelay,
  312. pinctrl_state->niodelays);
  313. else
  314. do_set_mux32((*ctrl)->control_padconf_core_base,
  315. pinctrl_state->padconf,
  316. pinctrl_state->npads);
  317. }
  318. }
  319. #endif
  320. static void omap_hsmmc_set_timing(struct mmc *mmc)
  321. {
  322. u32 val;
  323. struct hsmmc *mmc_base;
  324. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  325. mmc_base = priv->base_addr;
  326. omap_hsmmc_stop_clock(mmc_base);
  327. val = readl(&mmc_base->ac12);
  328. val &= ~AC12_UHSMC_MASK;
  329. priv->mode = mmc->selected_mode;
  330. if (mmc_is_mode_ddr(priv->mode))
  331. writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
  332. else
  333. writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
  334. switch (priv->mode) {
  335. case MMC_HS_200:
  336. case UHS_SDR104:
  337. val |= AC12_UHSMC_SDR104;
  338. break;
  339. case UHS_SDR50:
  340. val |= AC12_UHSMC_SDR50;
  341. break;
  342. case MMC_DDR_52:
  343. case UHS_DDR50:
  344. val |= AC12_UHSMC_DDR50;
  345. break;
  346. case SD_HS:
  347. case MMC_HS_52:
  348. case UHS_SDR25:
  349. val |= AC12_UHSMC_SDR25;
  350. break;
  351. case MMC_LEGACY:
  352. case MMC_HS:
  353. case SD_LEGACY:
  354. case UHS_SDR12:
  355. val |= AC12_UHSMC_SDR12;
  356. break;
  357. default:
  358. val |= AC12_UHSMC_RES;
  359. break;
  360. }
  361. writel(val, &mmc_base->ac12);
  362. #ifdef CONFIG_IODELAY_RECALIBRATION
  363. omap_hsmmc_io_recalibrate(mmc);
  364. #endif
  365. omap_hsmmc_start_clock(mmc_base);
  366. }
  367. static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
  368. {
  369. struct hsmmc *mmc_base;
  370. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  371. u32 hctl, ac12;
  372. mmc_base = priv->base_addr;
  373. hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
  374. ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
  375. switch (signal_voltage) {
  376. case MMC_SIGNAL_VOLTAGE_330:
  377. hctl |= SDVS_3V3;
  378. break;
  379. case MMC_SIGNAL_VOLTAGE_180:
  380. hctl |= SDVS_1V8;
  381. ac12 |= AC12_V1V8_SIGEN;
  382. break;
  383. }
  384. writel(hctl, &mmc_base->hctl);
  385. writel(ac12, &mmc_base->ac12);
  386. }
  387. static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
  388. {
  389. int ret = -ETIMEDOUT;
  390. u32 con;
  391. bool dat0_high;
  392. bool target_dat0_high = !!state;
  393. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  394. struct hsmmc *mmc_base = priv->base_addr;
  395. con = readl(&mmc_base->con);
  396. writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
  397. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  398. while (timeout_us--) {
  399. dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
  400. if (dat0_high == target_dat0_high) {
  401. ret = 0;
  402. break;
  403. }
  404. udelay(10);
  405. }
  406. writel(con, &mmc_base->con);
  407. return ret;
  408. }
  409. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  410. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  411. static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
  412. {
  413. int ret = 0;
  414. int uV = mV * 1000;
  415. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  416. if (!mmc->vqmmc_supply)
  417. return 0;
  418. /* Disable PBIAS */
  419. ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
  420. if (ret)
  421. return ret;
  422. /* Turn off IO voltage */
  423. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
  424. if (ret)
  425. return ret;
  426. /* Program a new IO voltage value */
  427. ret = regulator_set_value(mmc->vqmmc_supply, uV);
  428. if (ret)
  429. return ret;
  430. /* Turn on IO voltage */
  431. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
  432. if (ret)
  433. return ret;
  434. /* Program PBIAS voltage*/
  435. ret = regulator_set_value(priv->pbias_supply, uV);
  436. if (ret && ret != -ENOSYS)
  437. return ret;
  438. /* Enable PBIAS */
  439. ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
  440. if (ret)
  441. return ret;
  442. return 0;
  443. }
  444. #endif
  445. static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
  446. {
  447. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  448. struct hsmmc *mmc_base = priv->base_addr;
  449. int mv = mmc_voltage_to_mv(mmc->signal_voltage);
  450. u32 capa_mask;
  451. __maybe_unused u8 palmas_ldo_volt;
  452. u32 val;
  453. if (mv < 0)
  454. return -EINVAL;
  455. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  456. mv = 3300;
  457. capa_mask = VS33_3V3SUP;
  458. palmas_ldo_volt = LDO_VOLT_3V3;
  459. } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  460. capa_mask = VS18_1V8SUP;
  461. palmas_ldo_volt = LDO_VOLT_1V8;
  462. } else {
  463. return -EOPNOTSUPP;
  464. }
  465. val = readl(&mmc_base->capa);
  466. if (!(val & capa_mask))
  467. return -EOPNOTSUPP;
  468. priv->signal_voltage = mmc->signal_voltage;
  469. omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
  470. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  471. return omap_hsmmc_set_io_regulator(mmc, mv);
  472. #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
  473. defined(CONFIG_PALMAS_POWER)
  474. if (mmc_get_blk_desc(mmc)->devnum == 0)
  475. vmmc_pbias_config(palmas_ldo_volt);
  476. return 0;
  477. #else
  478. return 0;
  479. #endif
  480. }
  481. #endif
  482. static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
  483. {
  484. struct hsmmc *mmc_base;
  485. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  486. u32 val;
  487. mmc_base = priv->base_addr;
  488. val = readl(&mmc_base->capa);
  489. if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  490. val |= (VS33_3V3SUP | VS18_1V8SUP);
  491. } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
  492. val |= VS33_3V3SUP;
  493. val &= ~VS18_1V8SUP;
  494. } else {
  495. val |= VS18_1V8SUP;
  496. val &= ~VS33_3V3SUP;
  497. }
  498. writel(val, &mmc_base->capa);
  499. return val;
  500. }
  501. #ifdef MMC_SUPPORTS_TUNING
  502. static void omap_hsmmc_disable_tuning(struct mmc *mmc)
  503. {
  504. struct hsmmc *mmc_base;
  505. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  506. u32 val;
  507. mmc_base = priv->base_addr;
  508. val = readl(&mmc_base->ac12);
  509. val &= ~(AC12_SCLK_SEL);
  510. writel(val, &mmc_base->ac12);
  511. val = readl(&mmc_base->dll);
  512. val &= ~(DLL_FORCE_VALUE | DLL_SWT);
  513. writel(val, &mmc_base->dll);
  514. }
  515. static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
  516. {
  517. int i;
  518. struct hsmmc *mmc_base;
  519. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  520. u32 val;
  521. mmc_base = priv->base_addr;
  522. val = readl(&mmc_base->dll);
  523. val |= DLL_FORCE_VALUE;
  524. val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
  525. val |= (count << DLL_FORCE_SR_C_SHIFT);
  526. writel(val, &mmc_base->dll);
  527. val |= DLL_CALIB;
  528. writel(val, &mmc_base->dll);
  529. for (i = 0; i < 1000; i++) {
  530. if (readl(&mmc_base->dll) & DLL_CALIB)
  531. break;
  532. }
  533. val &= ~DLL_CALIB;
  534. writel(val, &mmc_base->dll);
  535. }
  536. static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
  537. {
  538. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  539. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  540. struct mmc *mmc = upriv->mmc;
  541. struct hsmmc *mmc_base;
  542. u32 val;
  543. u8 cur_match, prev_match = 0;
  544. int ret;
  545. u32 phase_delay = 0;
  546. u32 start_window = 0, max_window = 0;
  547. u32 length = 0, max_len = 0;
  548. bool single_point_failure = false;
  549. struct udevice *thermal_dev;
  550. int temperature;
  551. int i;
  552. mmc_base = priv->base_addr;
  553. val = readl(&mmc_base->capa2);
  554. /* clock tuning is not needed for upto 52MHz */
  555. if (!((mmc->selected_mode == MMC_HS_200) ||
  556. (mmc->selected_mode == UHS_SDR104) ||
  557. ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
  558. return 0;
  559. ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
  560. if (ret) {
  561. printf("Couldn't get thermal device for tuning\n");
  562. return ret;
  563. }
  564. ret = thermal_get_temp(thermal_dev, &temperature);
  565. if (ret) {
  566. printf("Couldn't get temperature for tuning\n");
  567. return ret;
  568. }
  569. val = readl(&mmc_base->dll);
  570. val |= DLL_SWT;
  571. writel(val, &mmc_base->dll);
  572. /*
  573. * Stage 1: Search for a maximum pass window ignoring any
  574. * any single point failures. If the tuning value ends up
  575. * near it, move away from it in stage 2 below
  576. */
  577. while (phase_delay <= MAX_PHASE_DELAY) {
  578. omap_hsmmc_set_dll(mmc, phase_delay);
  579. cur_match = !mmc_send_tuning(mmc, opcode, NULL);
  580. if (cur_match) {
  581. if (prev_match) {
  582. length++;
  583. } else if (single_point_failure) {
  584. /* ignore single point failure */
  585. length++;
  586. single_point_failure = false;
  587. } else {
  588. start_window = phase_delay;
  589. length = 1;
  590. }
  591. } else {
  592. single_point_failure = prev_match;
  593. }
  594. if (length > max_len) {
  595. max_window = start_window;
  596. max_len = length;
  597. }
  598. prev_match = cur_match;
  599. phase_delay += 4;
  600. }
  601. if (!max_len) {
  602. ret = -EIO;
  603. goto tuning_error;
  604. }
  605. val = readl(&mmc_base->ac12);
  606. if (!(val & AC12_SCLK_SEL)) {
  607. ret = -EIO;
  608. goto tuning_error;
  609. }
  610. /*
  611. * Assign tuning value as a ratio of maximum pass window based
  612. * on temperature
  613. */
  614. if (temperature < -20000)
  615. phase_delay = min(max_window + 4 * max_len - 24,
  616. max_window +
  617. DIV_ROUND_UP(13 * max_len, 16) * 4);
  618. else if (temperature < 20000)
  619. phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
  620. else if (temperature < 40000)
  621. phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
  622. else if (temperature < 70000)
  623. phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
  624. else if (temperature < 90000)
  625. phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
  626. else if (temperature < 120000)
  627. phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
  628. else
  629. phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
  630. /*
  631. * Stage 2: Search for a single point failure near the chosen tuning
  632. * value in two steps. First in the +3 to +10 range and then in the
  633. * +2 to -10 range. If found, move away from it in the appropriate
  634. * direction by the appropriate amount depending on the temperature.
  635. */
  636. for (i = 3; i <= 10; i++) {
  637. omap_hsmmc_set_dll(mmc, phase_delay + i);
  638. if (mmc_send_tuning(mmc, opcode, NULL)) {
  639. if (temperature < 10000)
  640. phase_delay += i + 6;
  641. else if (temperature < 20000)
  642. phase_delay += i - 12;
  643. else if (temperature < 70000)
  644. phase_delay += i - 8;
  645. else if (temperature < 90000)
  646. phase_delay += i - 6;
  647. else
  648. phase_delay += i - 6;
  649. goto single_failure_found;
  650. }
  651. }
  652. for (i = 2; i >= -10; i--) {
  653. omap_hsmmc_set_dll(mmc, phase_delay + i);
  654. if (mmc_send_tuning(mmc, opcode, NULL)) {
  655. if (temperature < 10000)
  656. phase_delay += i + 12;
  657. else if (temperature < 20000)
  658. phase_delay += i + 8;
  659. else if (temperature < 70000)
  660. phase_delay += i + 8;
  661. else if (temperature < 90000)
  662. phase_delay += i + 10;
  663. else
  664. phase_delay += i + 12;
  665. goto single_failure_found;
  666. }
  667. }
  668. single_failure_found:
  669. omap_hsmmc_set_dll(mmc, phase_delay);
  670. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  671. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  672. return 0;
  673. tuning_error:
  674. omap_hsmmc_disable_tuning(mmc);
  675. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  676. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  677. return ret;
  678. }
  679. #endif
  680. #endif
  681. static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
  682. {
  683. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  684. struct hsmmc *mmc_base = priv->base_addr;
  685. u32 irq_mask = INT_EN_MASK;
  686. /*
  687. * TODO: Errata i802 indicates only DCRC interrupts can occur during
  688. * tuning procedure and DCRC should be disabled. But see occurences
  689. * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
  690. * interrupts occur along with BRR, so the data is actually in the
  691. * buffer. It has to be debugged why these interrutps occur
  692. */
  693. if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
  694. irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
  695. writel(irq_mask, &mmc_base->ie);
  696. }
  697. static int omap_hsmmc_init_setup(struct mmc *mmc)
  698. {
  699. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  700. struct hsmmc *mmc_base;
  701. unsigned int reg_val;
  702. unsigned int dsor;
  703. ulong start;
  704. mmc_base = priv->base_addr;
  705. mmc_board_init(mmc);
  706. writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
  707. &mmc_base->sysconfig);
  708. start = get_timer(0);
  709. while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
  710. if (get_timer(0) - start > MAX_RETRY_MS) {
  711. printf("%s: timedout waiting for cc2!\n", __func__);
  712. return -ETIMEDOUT;
  713. }
  714. }
  715. writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
  716. start = get_timer(0);
  717. while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
  718. if (get_timer(0) - start > MAX_RETRY_MS) {
  719. printf("%s: timedout waiting for softresetall!\n",
  720. __func__);
  721. return -ETIMEDOUT;
  722. }
  723. }
  724. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  725. reg_val = readl(&mmc_base->hl_hwinfo);
  726. if (reg_val & MADMA_EN)
  727. priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
  728. #endif
  729. #if CONFIG_IS_ENABLED(DM_MMC)
  730. reg_val = omap_hsmmc_set_capabilities(mmc);
  731. omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
  732. MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
  733. #else
  734. writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
  735. writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
  736. &mmc_base->capa);
  737. #endif
  738. reg_val = readl(&mmc_base->con) & RESERVED_MASK;
  739. writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
  740. MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
  741. HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
  742. dsor = 240;
  743. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
  744. (ICE_STOP | DTO_15THDTO));
  745. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  746. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  747. start = get_timer(0);
  748. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  749. if (get_timer(0) - start > MAX_RETRY_MS) {
  750. printf("%s: timedout waiting for ics!\n", __func__);
  751. return -ETIMEDOUT;
  752. }
  753. }
  754. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  755. writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
  756. mmc_enable_irq(mmc, NULL);
  757. #if !CONFIG_IS_ENABLED(DM_MMC)
  758. mmc_init_stream(mmc_base);
  759. #endif
  760. return 0;
  761. }
  762. /*
  763. * MMC controller internal finite state machine reset
  764. *
  765. * Used to reset command or data internal state machines, using respectively
  766. * SRC or SRD bit of SYSCTL register
  767. */
  768. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
  769. {
  770. ulong start;
  771. mmc_reg_out(&mmc_base->sysctl, bit, bit);
  772. /*
  773. * CMD(DAT) lines reset procedures are slightly different
  774. * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
  775. * According to OMAP3 TRM:
  776. * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
  777. * returns to 0x0.
  778. * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
  779. * procedure steps must be as follows:
  780. * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
  781. * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
  782. * 2. Poll the SRC(SRD) bit until it is set to 0x1.
  783. * 3. Wait until the SRC (SRD) bit returns to 0x0
  784. * (reset procedure is completed).
  785. */
  786. #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  787. defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  788. if (!(readl(&mmc_base->sysctl) & bit)) {
  789. start = get_timer(0);
  790. while (!(readl(&mmc_base->sysctl) & bit)) {
  791. if (get_timer(0) - start > MMC_TIMEOUT_MS)
  792. return;
  793. }
  794. }
  795. #endif
  796. start = get_timer(0);
  797. while ((readl(&mmc_base->sysctl) & bit) != 0) {
  798. if (get_timer(0) - start > MAX_RETRY_MS) {
  799. printf("%s: timedout waiting for sysctl %x to clear\n",
  800. __func__, bit);
  801. return;
  802. }
  803. }
  804. }
  805. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  806. static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
  807. {
  808. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  809. struct omap_hsmmc_adma_desc *desc;
  810. u8 attr;
  811. desc = &priv->adma_desc_table[priv->desc_slot];
  812. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  813. if (!end)
  814. priv->desc_slot++;
  815. else
  816. attr |= ADMA_DESC_ATTR_END;
  817. desc->len = len;
  818. desc->addr = (u32)buf;
  819. desc->reserved = 0;
  820. desc->attr = attr;
  821. }
  822. static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
  823. struct mmc_data *data)
  824. {
  825. uint total_len = data->blocksize * data->blocks;
  826. uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
  827. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  828. int i = desc_count;
  829. char *buf;
  830. priv->desc_slot = 0;
  831. priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
  832. memalign(ARCH_DMA_MINALIGN, desc_count *
  833. sizeof(struct omap_hsmmc_adma_desc));
  834. if (data->flags & MMC_DATA_READ)
  835. buf = data->dest;
  836. else
  837. buf = (char *)data->src;
  838. while (--i) {
  839. omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
  840. buf += ADMA_MAX_LEN;
  841. total_len -= ADMA_MAX_LEN;
  842. }
  843. omap_hsmmc_adma_desc(mmc, buf, total_len, true);
  844. flush_dcache_range((long)priv->adma_desc_table,
  845. (long)priv->adma_desc_table +
  846. ROUND(desc_count *
  847. sizeof(struct omap_hsmmc_adma_desc),
  848. ARCH_DMA_MINALIGN));
  849. }
  850. static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
  851. {
  852. struct hsmmc *mmc_base;
  853. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  854. u32 val;
  855. char *buf;
  856. mmc_base = priv->base_addr;
  857. omap_hsmmc_prepare_adma_table(mmc, data);
  858. if (data->flags & MMC_DATA_READ)
  859. buf = data->dest;
  860. else
  861. buf = (char *)data->src;
  862. val = readl(&mmc_base->hctl);
  863. val |= DMA_SELECT;
  864. writel(val, &mmc_base->hctl);
  865. val = readl(&mmc_base->con);
  866. val |= DMA_MASTER;
  867. writel(val, &mmc_base->con);
  868. writel((u32)priv->adma_desc_table, &mmc_base->admasal);
  869. flush_dcache_range((u32)buf,
  870. (u32)buf +
  871. ROUND(data->blocksize * data->blocks,
  872. ARCH_DMA_MINALIGN));
  873. }
  874. static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
  875. {
  876. struct hsmmc *mmc_base;
  877. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  878. u32 val;
  879. mmc_base = priv->base_addr;
  880. val = readl(&mmc_base->con);
  881. val &= ~DMA_MASTER;
  882. writel(val, &mmc_base->con);
  883. val = readl(&mmc_base->hctl);
  884. val &= ~DMA_SELECT;
  885. writel(val, &mmc_base->hctl);
  886. kfree(priv->adma_desc_table);
  887. }
  888. #else
  889. #define omap_hsmmc_adma_desc
  890. #define omap_hsmmc_prepare_adma_table
  891. #define omap_hsmmc_prepare_data
  892. #define omap_hsmmc_dma_cleanup
  893. #endif
  894. #if !CONFIG_IS_ENABLED(DM_MMC)
  895. static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  896. struct mmc_data *data)
  897. {
  898. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  899. #else
  900. static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  901. struct mmc_data *data)
  902. {
  903. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  904. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  905. struct mmc *mmc = upriv->mmc;
  906. #endif
  907. struct hsmmc *mmc_base;
  908. unsigned int flags, mmc_stat;
  909. ulong start;
  910. priv->last_cmd = cmd->cmdidx;
  911. mmc_base = priv->base_addr;
  912. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  913. return 0;
  914. start = get_timer(0);
  915. while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
  916. if (get_timer(0) - start > MAX_RETRY_MS) {
  917. printf("%s: timedout waiting on cmd inhibit to clear\n",
  918. __func__);
  919. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  920. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  921. return -ETIMEDOUT;
  922. }
  923. }
  924. writel(0xFFFFFFFF, &mmc_base->stat);
  925. if (readl(&mmc_base->stat)) {
  926. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  927. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  928. }
  929. /*
  930. * CMDREG
  931. * CMDIDX[13:8] : Command index
  932. * DATAPRNT[5] : Data Present Select
  933. * ENCMDIDX[4] : Command Index Check Enable
  934. * ENCMDCRC[3] : Command CRC Check Enable
  935. * RSPTYP[1:0]
  936. * 00 = No Response
  937. * 01 = Length 136
  938. * 10 = Length 48
  939. * 11 = Length 48 Check busy after response
  940. */
  941. /* Delay added before checking the status of frq change
  942. * retry not supported by mmc.c(core file)
  943. */
  944. if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
  945. udelay(50000); /* wait 50 ms */
  946. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  947. flags = 0;
  948. else if (cmd->resp_type & MMC_RSP_136)
  949. flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
  950. else if (cmd->resp_type & MMC_RSP_BUSY)
  951. flags = RSP_TYPE_LGHT48B;
  952. else
  953. flags = RSP_TYPE_LGHT48;
  954. /* enable default flags */
  955. flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
  956. MSBS_SGLEBLK);
  957. flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
  958. if (cmd->resp_type & MMC_RSP_CRC)
  959. flags |= CCCE_CHECK;
  960. if (cmd->resp_type & MMC_RSP_OPCODE)
  961. flags |= CICE_CHECK;
  962. if (data) {
  963. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
  964. (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
  965. flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
  966. data->blocksize = 512;
  967. writel(data->blocksize | (data->blocks << 16),
  968. &mmc_base->blk);
  969. } else
  970. writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
  971. if (data->flags & MMC_DATA_READ)
  972. flags |= (DP_DATA | DDIR_READ);
  973. else
  974. flags |= (DP_DATA | DDIR_WRITE);
  975. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  976. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
  977. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  978. omap_hsmmc_prepare_data(mmc, data);
  979. flags |= DE_ENABLE;
  980. }
  981. #endif
  982. }
  983. mmc_enable_irq(mmc, cmd);
  984. writel(cmd->cmdarg, &mmc_base->arg);
  985. udelay(20); /* To fix "No status update" error on eMMC */
  986. writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
  987. start = get_timer(0);
  988. do {
  989. mmc_stat = readl(&mmc_base->stat);
  990. if (get_timer(start) > MAX_RETRY_MS) {
  991. printf("%s : timeout: No status update\n", __func__);
  992. return -ETIMEDOUT;
  993. }
  994. } while (!mmc_stat);
  995. if ((mmc_stat & IE_CTO) != 0) {
  996. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  997. return -ETIMEDOUT;
  998. } else if ((mmc_stat & ERRI_MASK) != 0)
  999. return -1;
  1000. if (mmc_stat & CC_MASK) {
  1001. writel(CC_MASK, &mmc_base->stat);
  1002. if (cmd->resp_type & MMC_RSP_PRESENT) {
  1003. if (cmd->resp_type & MMC_RSP_136) {
  1004. /* response type 2 */
  1005. cmd->response[3] = readl(&mmc_base->rsp10);
  1006. cmd->response[2] = readl(&mmc_base->rsp32);
  1007. cmd->response[1] = readl(&mmc_base->rsp54);
  1008. cmd->response[0] = readl(&mmc_base->rsp76);
  1009. } else
  1010. /* response types 1, 1b, 3, 4, 5, 6 */
  1011. cmd->response[0] = readl(&mmc_base->rsp10);
  1012. }
  1013. }
  1014. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  1015. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
  1016. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  1017. u32 sz_mb, timeout;
  1018. if (mmc_stat & IE_ADMAE) {
  1019. omap_hsmmc_dma_cleanup(mmc);
  1020. return -EIO;
  1021. }
  1022. sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
  1023. timeout = sz_mb * DMA_TIMEOUT_PER_MB;
  1024. if (timeout < MAX_RETRY_MS)
  1025. timeout = MAX_RETRY_MS;
  1026. start = get_timer(0);
  1027. do {
  1028. mmc_stat = readl(&mmc_base->stat);
  1029. if (mmc_stat & TC_MASK) {
  1030. writel(readl(&mmc_base->stat) | TC_MASK,
  1031. &mmc_base->stat);
  1032. break;
  1033. }
  1034. if (get_timer(start) > timeout) {
  1035. printf("%s : DMA timeout: No status update\n",
  1036. __func__);
  1037. return -ETIMEDOUT;
  1038. }
  1039. } while (1);
  1040. omap_hsmmc_dma_cleanup(mmc);
  1041. return 0;
  1042. }
  1043. #endif
  1044. if (data && (data->flags & MMC_DATA_READ)) {
  1045. mmc_read_data(mmc_base, data->dest,
  1046. data->blocksize * data->blocks);
  1047. } else if (data && (data->flags & MMC_DATA_WRITE)) {
  1048. mmc_write_data(mmc_base, data->src,
  1049. data->blocksize * data->blocks);
  1050. }
  1051. return 0;
  1052. }
  1053. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
  1054. {
  1055. unsigned int *output_buf = (unsigned int *)buf;
  1056. unsigned int mmc_stat;
  1057. unsigned int count;
  1058. /*
  1059. * Start Polled Read
  1060. */
  1061. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1062. count /= 4;
  1063. while (size) {
  1064. ulong start = get_timer(0);
  1065. do {
  1066. mmc_stat = readl(&mmc_base->stat);
  1067. if (get_timer(0) - start > MAX_RETRY_MS) {
  1068. printf("%s: timedout waiting for status!\n",
  1069. __func__);
  1070. return -ETIMEDOUT;
  1071. }
  1072. } while (mmc_stat == 0);
  1073. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1074. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1075. if ((mmc_stat & ERRI_MASK) != 0)
  1076. return 1;
  1077. if (mmc_stat & BRR_MASK) {
  1078. unsigned int k;
  1079. writel(readl(&mmc_base->stat) | BRR_MASK,
  1080. &mmc_base->stat);
  1081. for (k = 0; k < count; k++) {
  1082. *output_buf = readl(&mmc_base->data);
  1083. output_buf++;
  1084. }
  1085. size -= (count*4);
  1086. }
  1087. if (mmc_stat & BWR_MASK)
  1088. writel(readl(&mmc_base->stat) | BWR_MASK,
  1089. &mmc_base->stat);
  1090. if (mmc_stat & TC_MASK) {
  1091. writel(readl(&mmc_base->stat) | TC_MASK,
  1092. &mmc_base->stat);
  1093. break;
  1094. }
  1095. }
  1096. return 0;
  1097. }
  1098. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1099. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1100. unsigned int size)
  1101. {
  1102. unsigned int *input_buf = (unsigned int *)buf;
  1103. unsigned int mmc_stat;
  1104. unsigned int count;
  1105. /*
  1106. * Start Polled Write
  1107. */
  1108. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1109. count /= 4;
  1110. while (size) {
  1111. ulong start = get_timer(0);
  1112. do {
  1113. mmc_stat = readl(&mmc_base->stat);
  1114. if (get_timer(0) - start > MAX_RETRY_MS) {
  1115. printf("%s: timedout waiting for status!\n",
  1116. __func__);
  1117. return -ETIMEDOUT;
  1118. }
  1119. } while (mmc_stat == 0);
  1120. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1121. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1122. if ((mmc_stat & ERRI_MASK) != 0)
  1123. return 1;
  1124. if (mmc_stat & BWR_MASK) {
  1125. unsigned int k;
  1126. writel(readl(&mmc_base->stat) | BWR_MASK,
  1127. &mmc_base->stat);
  1128. for (k = 0; k < count; k++) {
  1129. writel(*input_buf, &mmc_base->data);
  1130. input_buf++;
  1131. }
  1132. size -= (count*4);
  1133. }
  1134. if (mmc_stat & BRR_MASK)
  1135. writel(readl(&mmc_base->stat) | BRR_MASK,
  1136. &mmc_base->stat);
  1137. if (mmc_stat & TC_MASK) {
  1138. writel(readl(&mmc_base->stat) | TC_MASK,
  1139. &mmc_base->stat);
  1140. break;
  1141. }
  1142. }
  1143. return 0;
  1144. }
  1145. #else
  1146. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1147. unsigned int size)
  1148. {
  1149. return -ENOTSUPP;
  1150. }
  1151. #endif
  1152. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
  1153. {
  1154. writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
  1155. }
  1156. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
  1157. {
  1158. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  1159. }
  1160. static void omap_hsmmc_set_clock(struct mmc *mmc)
  1161. {
  1162. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1163. struct hsmmc *mmc_base;
  1164. unsigned int dsor = 0;
  1165. ulong start;
  1166. mmc_base = priv->base_addr;
  1167. omap_hsmmc_stop_clock(mmc_base);
  1168. /* TODO: Is setting DTO required here? */
  1169. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
  1170. (ICE_STOP | DTO_15THDTO));
  1171. if (mmc->clock != 0) {
  1172. dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
  1173. if (dsor > CLKD_MAX)
  1174. dsor = CLKD_MAX;
  1175. } else {
  1176. dsor = CLKD_MAX;
  1177. }
  1178. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  1179. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  1180. start = get_timer(0);
  1181. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  1182. if (get_timer(0) - start > MAX_RETRY_MS) {
  1183. printf("%s: timedout waiting for ics!\n", __func__);
  1184. return;
  1185. }
  1186. }
  1187. priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
  1188. mmc->clock = priv->clock;
  1189. omap_hsmmc_start_clock(mmc_base);
  1190. }
  1191. static void omap_hsmmc_set_bus_width(struct mmc *mmc)
  1192. {
  1193. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1194. struct hsmmc *mmc_base;
  1195. mmc_base = priv->base_addr;
  1196. /* configue bus width */
  1197. switch (mmc->bus_width) {
  1198. case 8:
  1199. writel(readl(&mmc_base->con) | DTW_8_BITMODE,
  1200. &mmc_base->con);
  1201. break;
  1202. case 4:
  1203. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1204. &mmc_base->con);
  1205. writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
  1206. &mmc_base->hctl);
  1207. break;
  1208. case 1:
  1209. default:
  1210. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1211. &mmc_base->con);
  1212. writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
  1213. &mmc_base->hctl);
  1214. break;
  1215. }
  1216. priv->bus_width = mmc->bus_width;
  1217. }
  1218. #if !CONFIG_IS_ENABLED(DM_MMC)
  1219. static int omap_hsmmc_set_ios(struct mmc *mmc)
  1220. {
  1221. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1222. #else
  1223. static int omap_hsmmc_set_ios(struct udevice *dev)
  1224. {
  1225. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1226. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1227. struct mmc *mmc = upriv->mmc;
  1228. #endif
  1229. struct hsmmc *mmc_base = priv->base_addr;
  1230. int ret = 0;
  1231. if (priv->bus_width != mmc->bus_width)
  1232. omap_hsmmc_set_bus_width(mmc);
  1233. if (priv->clock != mmc->clock)
  1234. omap_hsmmc_set_clock(mmc);
  1235. if (mmc->clk_disable)
  1236. omap_hsmmc_stop_clock(mmc_base);
  1237. else
  1238. omap_hsmmc_start_clock(mmc_base);
  1239. #if CONFIG_IS_ENABLED(DM_MMC)
  1240. if (priv->mode != mmc->selected_mode)
  1241. omap_hsmmc_set_timing(mmc);
  1242. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1243. if (priv->signal_voltage != mmc->signal_voltage)
  1244. ret = omap_hsmmc_set_signal_voltage(mmc);
  1245. #endif
  1246. #endif
  1247. return ret;
  1248. }
  1249. #ifdef OMAP_HSMMC_USE_GPIO
  1250. #if CONFIG_IS_ENABLED(DM_MMC)
  1251. static int omap_hsmmc_getcd(struct udevice *dev)
  1252. {
  1253. int value = -1;
  1254. #if CONFIG_IS_ENABLED(DM_GPIO)
  1255. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1256. value = dm_gpio_get_value(&priv->cd_gpio);
  1257. #endif
  1258. /* if no CD return as 1 */
  1259. if (value < 0)
  1260. return 1;
  1261. return value;
  1262. }
  1263. static int omap_hsmmc_getwp(struct udevice *dev)
  1264. {
  1265. int value = 0;
  1266. #if CONFIG_IS_ENABLED(DM_GPIO)
  1267. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1268. value = dm_gpio_get_value(&priv->wp_gpio);
  1269. #endif
  1270. /* if no WP return as 0 */
  1271. if (value < 0)
  1272. return 0;
  1273. return value;
  1274. }
  1275. #else
  1276. static int omap_hsmmc_getcd(struct mmc *mmc)
  1277. {
  1278. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1279. int cd_gpio;
  1280. /* if no CD return as 1 */
  1281. cd_gpio = priv->cd_gpio;
  1282. if (cd_gpio < 0)
  1283. return 1;
  1284. /* NOTE: assumes card detect signal is active-low */
  1285. return !gpio_get_value(cd_gpio);
  1286. }
  1287. static int omap_hsmmc_getwp(struct mmc *mmc)
  1288. {
  1289. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1290. int wp_gpio;
  1291. /* if no WP return as 0 */
  1292. wp_gpio = priv->wp_gpio;
  1293. if (wp_gpio < 0)
  1294. return 0;
  1295. /* NOTE: assumes write protect signal is active-high */
  1296. return gpio_get_value(wp_gpio);
  1297. }
  1298. #endif
  1299. #endif
  1300. #if CONFIG_IS_ENABLED(DM_MMC)
  1301. static const struct dm_mmc_ops omap_hsmmc_ops = {
  1302. .send_cmd = omap_hsmmc_send_cmd,
  1303. .set_ios = omap_hsmmc_set_ios,
  1304. #ifdef OMAP_HSMMC_USE_GPIO
  1305. .get_cd = omap_hsmmc_getcd,
  1306. .get_wp = omap_hsmmc_getwp,
  1307. #endif
  1308. #ifdef MMC_SUPPORTS_TUNING
  1309. .execute_tuning = omap_hsmmc_execute_tuning,
  1310. #endif
  1311. .wait_dat0 = omap_hsmmc_wait_dat0,
  1312. };
  1313. #else
  1314. static const struct mmc_ops omap_hsmmc_ops = {
  1315. .send_cmd = omap_hsmmc_send_cmd,
  1316. .set_ios = omap_hsmmc_set_ios,
  1317. .init = omap_hsmmc_init_setup,
  1318. #ifdef OMAP_HSMMC_USE_GPIO
  1319. .getcd = omap_hsmmc_getcd,
  1320. .getwp = omap_hsmmc_getwp,
  1321. #endif
  1322. };
  1323. #endif
  1324. #if !CONFIG_IS_ENABLED(DM_MMC)
  1325. int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
  1326. int wp_gpio)
  1327. {
  1328. struct mmc *mmc;
  1329. struct omap_hsmmc_data *priv;
  1330. struct mmc_config *cfg;
  1331. uint host_caps_val;
  1332. priv = calloc(1, sizeof(*priv));
  1333. if (priv == NULL)
  1334. return -1;
  1335. host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1336. switch (dev_index) {
  1337. case 0:
  1338. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1339. break;
  1340. #ifdef OMAP_HSMMC2_BASE
  1341. case 1:
  1342. priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
  1343. #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  1344. defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
  1345. defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
  1346. defined(CONFIG_HSMMC2_8BIT)
  1347. /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
  1348. host_caps_val |= MMC_MODE_8BIT;
  1349. #endif
  1350. break;
  1351. #endif
  1352. #ifdef OMAP_HSMMC3_BASE
  1353. case 2:
  1354. priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
  1355. #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
  1356. /* Enable 8-bit interface for eMMC on DRA7XX */
  1357. host_caps_val |= MMC_MODE_8BIT;
  1358. #endif
  1359. break;
  1360. #endif
  1361. default:
  1362. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1363. return 1;
  1364. }
  1365. #ifdef OMAP_HSMMC_USE_GPIO
  1366. /* on error gpio values are set to -1, which is what we want */
  1367. priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
  1368. priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
  1369. #endif
  1370. cfg = &priv->cfg;
  1371. cfg->name = "OMAP SD/MMC";
  1372. cfg->ops = &omap_hsmmc_ops;
  1373. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1374. cfg->host_caps = host_caps_val & ~host_caps_mask;
  1375. cfg->f_min = 400000;
  1376. if (f_max != 0)
  1377. cfg->f_max = f_max;
  1378. else {
  1379. if (cfg->host_caps & MMC_MODE_HS) {
  1380. if (cfg->host_caps & MMC_MODE_HS_52MHz)
  1381. cfg->f_max = 52000000;
  1382. else
  1383. cfg->f_max = 26000000;
  1384. } else
  1385. cfg->f_max = 20000000;
  1386. }
  1387. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1388. #if defined(CONFIG_OMAP34XX)
  1389. /*
  1390. * Silicon revs 2.1 and older do not support multiblock transfers.
  1391. */
  1392. if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
  1393. cfg->b_max = 1;
  1394. #endif
  1395. mmc = mmc_create(cfg, priv);
  1396. if (mmc == NULL)
  1397. return -1;
  1398. return 0;
  1399. }
  1400. #else
  1401. #ifdef CONFIG_IODELAY_RECALIBRATION
  1402. static struct pad_conf_entry *
  1403. omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
  1404. {
  1405. int index = 0;
  1406. struct pad_conf_entry *padconf;
  1407. padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
  1408. if (!padconf) {
  1409. debug("failed to allocate memory\n");
  1410. return 0;
  1411. }
  1412. while (index < count) {
  1413. padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
  1414. padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
  1415. index++;
  1416. }
  1417. return padconf;
  1418. }
  1419. static struct iodelay_cfg_entry *
  1420. omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
  1421. {
  1422. int index = 0;
  1423. struct iodelay_cfg_entry *iodelay;
  1424. iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
  1425. if (!iodelay) {
  1426. debug("failed to allocate memory\n");
  1427. return 0;
  1428. }
  1429. while (index < count) {
  1430. iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
  1431. iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
  1432. iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
  1433. index++;
  1434. }
  1435. return iodelay;
  1436. }
  1437. static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
  1438. const char *name, int *len)
  1439. {
  1440. const void *fdt = gd->fdt_blob;
  1441. int offset;
  1442. const fdt32_t *pinctrl;
  1443. offset = fdt_node_offset_by_phandle(fdt, phandle);
  1444. if (offset < 0) {
  1445. debug("failed to get pinctrl node %s.\n",
  1446. fdt_strerror(offset));
  1447. return 0;
  1448. }
  1449. pinctrl = fdt_getprop(fdt, offset, name, len);
  1450. if (!pinctrl) {
  1451. debug("failed to get property %s\n", name);
  1452. return 0;
  1453. }
  1454. return pinctrl;
  1455. }
  1456. static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
  1457. char *prop_name)
  1458. {
  1459. const void *fdt = gd->fdt_blob;
  1460. const __be32 *phandle;
  1461. int node = dev_of_offset(mmc->dev);
  1462. phandle = fdt_getprop(fdt, node, prop_name, NULL);
  1463. if (!phandle) {
  1464. debug("failed to get property %s\n", prop_name);
  1465. return 0;
  1466. }
  1467. return fdt32_to_cpu(*phandle);
  1468. }
  1469. static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
  1470. char *prop_name)
  1471. {
  1472. const void *fdt = gd->fdt_blob;
  1473. const __be32 *phandle;
  1474. int len;
  1475. int count;
  1476. int node = dev_of_offset(mmc->dev);
  1477. phandle = fdt_getprop(fdt, node, prop_name, &len);
  1478. if (!phandle) {
  1479. debug("failed to get property %s\n", prop_name);
  1480. return 0;
  1481. }
  1482. /* No manual mode iodelay values if count < 2 */
  1483. count = len / sizeof(*phandle);
  1484. if (count < 2)
  1485. return 0;
  1486. return fdt32_to_cpu(*(phandle + 1));
  1487. }
  1488. static struct pad_conf_entry *
  1489. omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
  1490. {
  1491. int len;
  1492. int count;
  1493. struct pad_conf_entry *padconf;
  1494. u32 phandle;
  1495. const fdt32_t *pinctrl;
  1496. phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
  1497. if (!phandle)
  1498. return ERR_PTR(-EINVAL);
  1499. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
  1500. &len);
  1501. if (!pinctrl)
  1502. return ERR_PTR(-EINVAL);
  1503. count = (len / sizeof(*pinctrl)) / 2;
  1504. padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
  1505. if (!padconf)
  1506. return ERR_PTR(-EINVAL);
  1507. *npads = count;
  1508. return padconf;
  1509. }
  1510. static struct iodelay_cfg_entry *
  1511. omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
  1512. {
  1513. int len;
  1514. int count;
  1515. struct iodelay_cfg_entry *iodelay;
  1516. u32 phandle;
  1517. const fdt32_t *pinctrl;
  1518. phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
  1519. /* Not all modes have manual mode iodelay values. So its not fatal */
  1520. if (!phandle)
  1521. return 0;
  1522. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
  1523. &len);
  1524. if (!pinctrl)
  1525. return ERR_PTR(-EINVAL);
  1526. count = (len / sizeof(*pinctrl)) / 3;
  1527. iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
  1528. if (!iodelay)
  1529. return ERR_PTR(-EINVAL);
  1530. *niodelay = count;
  1531. return iodelay;
  1532. }
  1533. static struct omap_hsmmc_pinctrl_state *
  1534. omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
  1535. {
  1536. int index;
  1537. int npads = 0;
  1538. int niodelays = 0;
  1539. const void *fdt = gd->fdt_blob;
  1540. int node = dev_of_offset(mmc->dev);
  1541. char prop_name[11];
  1542. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  1543. pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
  1544. malloc(sizeof(*pinctrl_state));
  1545. if (!pinctrl_state) {
  1546. debug("failed to allocate memory\n");
  1547. return 0;
  1548. }
  1549. index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
  1550. if (index < 0) {
  1551. debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
  1552. goto err_pinctrl_state;
  1553. }
  1554. sprintf(prop_name, "pinctrl-%d", index);
  1555. pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
  1556. &npads);
  1557. if (IS_ERR(pinctrl_state->padconf))
  1558. goto err_pinctrl_state;
  1559. pinctrl_state->npads = npads;
  1560. pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
  1561. &niodelays);
  1562. if (IS_ERR(pinctrl_state->iodelay))
  1563. goto err_padconf;
  1564. pinctrl_state->niodelays = niodelays;
  1565. return pinctrl_state;
  1566. err_padconf:
  1567. kfree(pinctrl_state->padconf);
  1568. err_pinctrl_state:
  1569. kfree(pinctrl_state);
  1570. return 0;
  1571. }
  1572. #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
  1573. do { \
  1574. struct omap_hsmmc_pinctrl_state *s = NULL; \
  1575. char str[20]; \
  1576. if (!(cfg->host_caps & capmask)) \
  1577. break; \
  1578. \
  1579. if (priv->hw_rev) { \
  1580. sprintf(str, "%s-%s", #mode, priv->hw_rev); \
  1581. s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
  1582. } \
  1583. \
  1584. if (!s) \
  1585. s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
  1586. \
  1587. if (!s && !optional) { \
  1588. debug("%s: no pinctrl for %s\n", \
  1589. mmc->dev->name, #mode); \
  1590. cfg->host_caps &= ~(capmask); \
  1591. } else { \
  1592. priv->mode##_pinctrl_state = s; \
  1593. } \
  1594. } while (0)
  1595. static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
  1596. {
  1597. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1598. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  1599. struct omap_hsmmc_pinctrl_state *default_pinctrl;
  1600. if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
  1601. return 0;
  1602. default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
  1603. if (!default_pinctrl) {
  1604. printf("no pinctrl state for default mode\n");
  1605. return -EINVAL;
  1606. }
  1607. priv->default_pinctrl_state = default_pinctrl;
  1608. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
  1609. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
  1610. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
  1611. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
  1612. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
  1613. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
  1614. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
  1615. OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
  1616. return 0;
  1617. }
  1618. #endif
  1619. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1620. #ifdef CONFIG_OMAP54XX
  1621. __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  1622. {
  1623. return NULL;
  1624. }
  1625. #endif
  1626. static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
  1627. {
  1628. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1629. struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
  1630. struct mmc_config *cfg = &plat->cfg;
  1631. #ifdef CONFIG_OMAP54XX
  1632. const struct mmc_platform_fixups *fixups;
  1633. #endif
  1634. const void *fdt = gd->fdt_blob;
  1635. int node = dev_of_offset(dev);
  1636. int ret;
  1637. plat->base_addr = map_physmem(devfdt_get_addr(dev),
  1638. sizeof(struct hsmmc *),
  1639. MAP_NOCACHE);
  1640. ret = mmc_of_parse(dev, cfg);
  1641. if (ret < 0)
  1642. return ret;
  1643. if (!cfg->f_max)
  1644. cfg->f_max = 52000000;
  1645. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1646. cfg->f_min = 400000;
  1647. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1648. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1649. if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
  1650. plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1651. if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
  1652. plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
  1653. if (of_data)
  1654. plat->controller_flags |= of_data->controller_flags;
  1655. #ifdef CONFIG_OMAP54XX
  1656. fixups = platform_fixups_mmc(devfdt_get_addr(dev));
  1657. if (fixups) {
  1658. plat->hw_rev = fixups->hw_rev;
  1659. cfg->host_caps &= ~fixups->unsupported_caps;
  1660. cfg->f_max = fixups->max_freq;
  1661. }
  1662. #endif
  1663. return 0;
  1664. }
  1665. #endif
  1666. #ifdef CONFIG_BLK
  1667. static int omap_hsmmc_bind(struct udevice *dev)
  1668. {
  1669. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1670. plat->mmc = calloc(1, sizeof(struct mmc));
  1671. return mmc_bind(dev, plat->mmc, &plat->cfg);
  1672. }
  1673. #endif
  1674. static int omap_hsmmc_probe(struct udevice *dev)
  1675. {
  1676. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1677. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1678. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1679. struct mmc_config *cfg = &plat->cfg;
  1680. struct mmc *mmc;
  1681. #ifdef CONFIG_IODELAY_RECALIBRATION
  1682. int ret;
  1683. #endif
  1684. cfg->name = "OMAP SD/MMC";
  1685. priv->base_addr = plat->base_addr;
  1686. priv->controller_flags = plat->controller_flags;
  1687. priv->hw_rev = plat->hw_rev;
  1688. #ifdef CONFIG_BLK
  1689. mmc = plat->mmc;
  1690. #else
  1691. mmc = mmc_create(cfg, priv);
  1692. if (mmc == NULL)
  1693. return -1;
  1694. #endif
  1695. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1696. device_get_supply_regulator(dev, "pbias-supply",
  1697. &priv->pbias_supply);
  1698. #endif
  1699. #if defined(OMAP_HSMMC_USE_GPIO)
  1700. #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
  1701. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  1702. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  1703. #endif
  1704. #endif
  1705. mmc->dev = dev;
  1706. upriv->mmc = mmc;
  1707. #ifdef CONFIG_IODELAY_RECALIBRATION
  1708. ret = omap_hsmmc_get_pinctrl_state(mmc);
  1709. /*
  1710. * disable high speed modes for the platforms that require IO delay
  1711. * and for which we don't have this information
  1712. */
  1713. if ((ret < 0) &&
  1714. (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
  1715. priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
  1716. cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
  1717. UHS_CAPS);
  1718. }
  1719. #endif
  1720. return omap_hsmmc_init_setup(mmc);
  1721. }
  1722. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1723. static const struct omap_mmc_of_data dra7_mmc_of_data = {
  1724. .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
  1725. };
  1726. static const struct udevice_id omap_hsmmc_ids[] = {
  1727. { .compatible = "ti,omap3-hsmmc" },
  1728. { .compatible = "ti,omap4-hsmmc" },
  1729. { .compatible = "ti,am33xx-hsmmc" },
  1730. { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
  1731. { }
  1732. };
  1733. #endif
  1734. U_BOOT_DRIVER(omap_hsmmc) = {
  1735. .name = "omap_hsmmc",
  1736. .id = UCLASS_MMC,
  1737. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1738. .of_match = omap_hsmmc_ids,
  1739. .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
  1740. .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
  1741. #endif
  1742. #ifdef CONFIG_BLK
  1743. .bind = omap_hsmmc_bind,
  1744. #endif
  1745. .ops = &omap_hsmmc_ops,
  1746. .probe = omap_hsmmc_probe,
  1747. .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
  1748. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  1749. .flags = DM_FLAG_PRE_RELOC,
  1750. #endif
  1751. };
  1752. #endif