fsl_esdhc_imx.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <mmc.h>
  20. #include <part.h>
  21. #include <power/regulator.h>
  22. #include <malloc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <fdt_support.h>
  25. #include <asm/io.h>
  26. #include <dm.h>
  27. #include <asm-generic/gpio.h>
  28. #include <dm/pinctrl.h>
  29. #if !CONFIG_IS_ENABLED(BLK)
  30. #include "mmc_private.h"
  31. #endif
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  34. IRQSTATEN_CINT | \
  35. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  36. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  37. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  38. IRQSTATEN_DINT)
  39. #define MAX_TUNING_LOOP 40
  40. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  41. struct fsl_esdhc {
  42. uint dsaddr; /* SDMA system address register */
  43. uint blkattr; /* Block attributes register */
  44. uint cmdarg; /* Command argument register */
  45. uint xfertyp; /* Transfer type register */
  46. uint cmdrsp0; /* Command response 0 register */
  47. uint cmdrsp1; /* Command response 1 register */
  48. uint cmdrsp2; /* Command response 2 register */
  49. uint cmdrsp3; /* Command response 3 register */
  50. uint datport; /* Buffer data port register */
  51. uint prsstat; /* Present state register */
  52. uint proctl; /* Protocol control register */
  53. uint sysctl; /* System Control Register */
  54. uint irqstat; /* Interrupt status register */
  55. uint irqstaten; /* Interrupt status enable register */
  56. uint irqsigen; /* Interrupt signal enable register */
  57. uint autoc12err; /* Auto CMD error status register */
  58. uint hostcapblt; /* Host controller capabilities register */
  59. uint wml; /* Watermark level register */
  60. uint mixctrl; /* For USDHC */
  61. char reserved1[4]; /* reserved */
  62. uint fevt; /* Force event register */
  63. uint admaes; /* ADMA error status register */
  64. uint adsaddr; /* ADMA system address register */
  65. char reserved2[4];
  66. uint dllctrl;
  67. uint dllstat;
  68. uint clktunectrlstatus;
  69. char reserved3[4];
  70. uint strobe_dllctrl;
  71. uint strobe_dllstat;
  72. char reserved4[72];
  73. uint vendorspec;
  74. uint mmcboot;
  75. uint vendorspec2;
  76. uint tuning_ctrl; /* on i.MX6/7/8 */
  77. char reserved5[44];
  78. uint hostver; /* Host controller version register */
  79. char reserved6[4]; /* reserved */
  80. uint dmaerraddr; /* DMA error address register */
  81. char reserved7[4]; /* reserved */
  82. uint dmaerrattr; /* DMA error attribute register */
  83. char reserved8[4]; /* reserved */
  84. uint hostcapblt2; /* Host controller capabilities register 2 */
  85. char reserved9[8]; /* reserved */
  86. uint tcr; /* Tuning control register */
  87. char reserved10[28]; /* reserved */
  88. uint sddirctl; /* SD direction control register */
  89. char reserved11[712];/* reserved */
  90. uint scr; /* eSDHC control register */
  91. };
  92. struct fsl_esdhc_plat {
  93. struct mmc_config cfg;
  94. struct mmc mmc;
  95. };
  96. struct esdhc_soc_data {
  97. u32 flags;
  98. };
  99. /**
  100. * struct fsl_esdhc_priv
  101. *
  102. * @esdhc_regs: registers of the sdhc controller
  103. * @sdhc_clk: Current clk of the sdhc controller
  104. * @bus_width: bus width, 1bit, 4bit or 8bit
  105. * @cfg: mmc config
  106. * @mmc: mmc
  107. * Following is used when Driver Model is enabled for MMC
  108. * @dev: pointer for the device
  109. * @non_removable: 0: removable; 1: non-removable
  110. * @wp_enable: 1: enable checking wp; 0: no check
  111. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  112. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  113. * @caps: controller capabilities
  114. * @tuning_step: tuning step setting in tuning_ctrl register
  115. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  116. * @strobe_dll_delay_target: settings in strobe_dllctrl
  117. * @signal_voltage: indicating the current voltage
  118. * @cd_gpio: gpio for card detection
  119. * @wp_gpio: gpio for write protection
  120. */
  121. struct fsl_esdhc_priv {
  122. struct fsl_esdhc *esdhc_regs;
  123. unsigned int sdhc_clk;
  124. struct clk per_clk;
  125. unsigned int clock;
  126. unsigned int mode;
  127. unsigned int bus_width;
  128. #if !CONFIG_IS_ENABLED(BLK)
  129. struct mmc *mmc;
  130. #endif
  131. struct udevice *dev;
  132. int non_removable;
  133. int wp_enable;
  134. int vs18_enable;
  135. u32 flags;
  136. u32 caps;
  137. u32 tuning_step;
  138. u32 tuning_start_tap;
  139. u32 strobe_dll_delay_target;
  140. u32 signal_voltage;
  141. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  142. struct udevice *vqmmc_dev;
  143. struct udevice *vmmc_dev;
  144. #endif
  145. #if CONFIG_IS_ENABLED(DM_GPIO)
  146. struct gpio_desc cd_gpio;
  147. struct gpio_desc wp_gpio;
  148. #endif
  149. };
  150. /* Return the XFERTYP flags for a given command and data packet */
  151. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  152. {
  153. uint xfertyp = 0;
  154. if (data) {
  155. xfertyp |= XFERTYP_DPSEL;
  156. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  157. xfertyp |= XFERTYP_DMAEN;
  158. #endif
  159. if (data->blocks > 1) {
  160. xfertyp |= XFERTYP_MSBSEL;
  161. xfertyp |= XFERTYP_BCEN;
  162. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  163. xfertyp |= XFERTYP_AC12EN;
  164. #endif
  165. }
  166. if (data->flags & MMC_DATA_READ)
  167. xfertyp |= XFERTYP_DTDSEL;
  168. }
  169. if (cmd->resp_type & MMC_RSP_CRC)
  170. xfertyp |= XFERTYP_CCCEN;
  171. if (cmd->resp_type & MMC_RSP_OPCODE)
  172. xfertyp |= XFERTYP_CICEN;
  173. if (cmd->resp_type & MMC_RSP_136)
  174. xfertyp |= XFERTYP_RSPTYP_136;
  175. else if (cmd->resp_type & MMC_RSP_BUSY)
  176. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  177. else if (cmd->resp_type & MMC_RSP_PRESENT)
  178. xfertyp |= XFERTYP_RSPTYP_48;
  179. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  180. xfertyp |= XFERTYP_CMDTYP_ABORT;
  181. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  182. }
  183. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  184. /*
  185. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  186. */
  187. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  188. struct mmc_data *data)
  189. {
  190. struct fsl_esdhc *regs = priv->esdhc_regs;
  191. uint blocks;
  192. char *buffer;
  193. uint databuf;
  194. uint size;
  195. uint irqstat;
  196. ulong start;
  197. if (data->flags & MMC_DATA_READ) {
  198. blocks = data->blocks;
  199. buffer = data->dest;
  200. while (blocks) {
  201. start = get_timer(0);
  202. size = data->blocksize;
  203. irqstat = esdhc_read32(&regs->irqstat);
  204. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  205. if (get_timer(start) > PIO_TIMEOUT) {
  206. printf("\nData Read Failed in PIO Mode.");
  207. return;
  208. }
  209. }
  210. while (size && (!(irqstat & IRQSTAT_TC))) {
  211. udelay(100); /* Wait before last byte transfer complete */
  212. irqstat = esdhc_read32(&regs->irqstat);
  213. databuf = in_le32(&regs->datport);
  214. *((uint *)buffer) = databuf;
  215. buffer += 4;
  216. size -= 4;
  217. }
  218. blocks--;
  219. }
  220. } else {
  221. blocks = data->blocks;
  222. buffer = (char *)data->src;
  223. while (blocks) {
  224. start = get_timer(0);
  225. size = data->blocksize;
  226. irqstat = esdhc_read32(&regs->irqstat);
  227. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  228. if (get_timer(start) > PIO_TIMEOUT) {
  229. printf("\nData Write Failed in PIO Mode.");
  230. return;
  231. }
  232. }
  233. while (size && (!(irqstat & IRQSTAT_TC))) {
  234. udelay(100); /* Wait before last byte transfer complete */
  235. databuf = *((uint *)buffer);
  236. buffer += 4;
  237. size -= 4;
  238. irqstat = esdhc_read32(&regs->irqstat);
  239. out_le32(&regs->datport, databuf);
  240. }
  241. blocks--;
  242. }
  243. }
  244. }
  245. #endif
  246. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  247. struct mmc_data *data)
  248. {
  249. int timeout;
  250. struct fsl_esdhc *regs = priv->esdhc_regs;
  251. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  252. dma_addr_t addr;
  253. #endif
  254. uint wml_value;
  255. wml_value = data->blocksize/4;
  256. if (data->flags & MMC_DATA_READ) {
  257. if (wml_value > WML_RD_WML_MAX)
  258. wml_value = WML_RD_WML_MAX_VAL;
  259. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  260. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  261. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  262. addr = virt_to_phys((void *)(data->dest));
  263. if (upper_32_bits(addr))
  264. printf("Error found for upper 32 bits\n");
  265. else
  266. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  267. #else
  268. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  269. #endif
  270. #endif
  271. } else {
  272. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  273. flush_dcache_range((ulong)data->src,
  274. (ulong)data->src+data->blocks
  275. *data->blocksize);
  276. #endif
  277. if (wml_value > WML_WR_WML_MAX)
  278. wml_value = WML_WR_WML_MAX_VAL;
  279. if (priv->wp_enable) {
  280. if ((esdhc_read32(&regs->prsstat) &
  281. PRSSTAT_WPSPL) == 0) {
  282. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  283. return -ETIMEDOUT;
  284. }
  285. } else {
  286. #if CONFIG_IS_ENABLED(DM_GPIO)
  287. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  288. dm_gpio_get_value(&priv->wp_gpio)) {
  289. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  290. return -ETIMEDOUT;
  291. }
  292. #endif
  293. }
  294. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  295. wml_value << 16);
  296. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  297. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  298. addr = virt_to_phys((void *)(data->src));
  299. if (upper_32_bits(addr))
  300. printf("Error found for upper 32 bits\n");
  301. else
  302. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  303. #else
  304. esdhc_write32(&regs->dsaddr, (u32)data->src);
  305. #endif
  306. #endif
  307. }
  308. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  309. /* Calculate the timeout period for data transactions */
  310. /*
  311. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  312. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  313. * So, Number of SD Clock cycles for 0.25sec should be minimum
  314. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  315. * = (mmc->clock * 1/4) SD Clock cycles
  316. * As 1) >= 2)
  317. * => (2^(timeout+13)) >= mmc->clock * 1/4
  318. * Taking log2 both the sides
  319. * => timeout + 13 >= log2(mmc->clock/4)
  320. * Rounding up to next power of 2
  321. * => timeout + 13 = log2(mmc->clock/4) + 1
  322. * => timeout + 13 = fls(mmc->clock/4)
  323. *
  324. * However, the MMC spec "It is strongly recommended for hosts to
  325. * implement more than 500ms timeout value even if the card
  326. * indicates the 250ms maximum busy length." Even the previous
  327. * value of 300ms is known to be insufficient for some cards.
  328. * So, we use
  329. * => timeout + 13 = fls(mmc->clock/2)
  330. */
  331. timeout = fls(mmc->clock/2);
  332. timeout -= 13;
  333. if (timeout > 14)
  334. timeout = 14;
  335. if (timeout < 0)
  336. timeout = 0;
  337. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  338. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  339. timeout++;
  340. #endif
  341. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  342. timeout = 0xE;
  343. #endif
  344. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  345. return 0;
  346. }
  347. static void check_and_invalidate_dcache_range
  348. (struct mmc_cmd *cmd,
  349. struct mmc_data *data) {
  350. unsigned start = 0;
  351. unsigned end = 0;
  352. unsigned size = roundup(ARCH_DMA_MINALIGN,
  353. data->blocks*data->blocksize);
  354. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  355. dma_addr_t addr;
  356. addr = virt_to_phys((void *)(data->dest));
  357. if (upper_32_bits(addr))
  358. printf("Error found for upper 32 bits\n");
  359. else
  360. start = lower_32_bits(addr);
  361. #else
  362. start = (unsigned)data->dest;
  363. #endif
  364. end = start + size;
  365. invalidate_dcache_range(start, end);
  366. }
  367. #ifdef CONFIG_MCF5441x
  368. /*
  369. * Swaps 32-bit words to little-endian byte order.
  370. */
  371. static inline void sd_swap_dma_buff(struct mmc_data *data)
  372. {
  373. int i, size = data->blocksize >> 2;
  374. u32 *buffer = (u32 *)data->dest;
  375. u32 sw;
  376. while (data->blocks--) {
  377. for (i = 0; i < size; i++) {
  378. sw = __sw32(*buffer);
  379. *buffer++ = sw;
  380. }
  381. }
  382. }
  383. #endif
  384. /*
  385. * Sends a command out on the bus. Takes the mmc pointer,
  386. * a command pointer, and an optional data pointer.
  387. */
  388. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  389. struct mmc_cmd *cmd, struct mmc_data *data)
  390. {
  391. int err = 0;
  392. uint xfertyp;
  393. uint irqstat;
  394. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  395. struct fsl_esdhc *regs = priv->esdhc_regs;
  396. unsigned long start;
  397. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  398. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  399. return 0;
  400. #endif
  401. esdhc_write32(&regs->irqstat, -1);
  402. sync();
  403. /* Wait for the bus to be idle */
  404. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  405. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  406. ;
  407. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  408. ;
  409. /* Wait at least 8 SD clock cycles before the next command */
  410. /*
  411. * Note: This is way more than 8 cycles, but 1ms seems to
  412. * resolve timing issues with some cards
  413. */
  414. udelay(1000);
  415. /* Set up for a data transfer if we have one */
  416. if (data) {
  417. err = esdhc_setup_data(priv, mmc, data);
  418. if(err)
  419. return err;
  420. if (data->flags & MMC_DATA_READ)
  421. check_and_invalidate_dcache_range(cmd, data);
  422. }
  423. /* Figure out the transfer arguments */
  424. xfertyp = esdhc_xfertyp(cmd, data);
  425. /* Mask all irqs */
  426. esdhc_write32(&regs->irqsigen, 0);
  427. /* Send the command */
  428. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  429. #if defined(CONFIG_FSL_USDHC)
  430. esdhc_write32(&regs->mixctrl,
  431. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  432. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  433. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  434. #else
  435. esdhc_write32(&regs->xfertyp, xfertyp);
  436. #endif
  437. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  438. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  439. flags = IRQSTAT_BRR;
  440. /* Wait for the command to complete */
  441. start = get_timer(0);
  442. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  443. if (get_timer(start) > 1000) {
  444. err = -ETIMEDOUT;
  445. goto out;
  446. }
  447. }
  448. irqstat = esdhc_read32(&regs->irqstat);
  449. if (irqstat & CMD_ERR) {
  450. err = -ECOMM;
  451. goto out;
  452. }
  453. if (irqstat & IRQSTAT_CTOE) {
  454. err = -ETIMEDOUT;
  455. goto out;
  456. }
  457. /* Switch voltage to 1.8V if CMD11 succeeded */
  458. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
  459. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  460. printf("Run CMD11 1.8V switch\n");
  461. /* Sleep for 5 ms - max time for card to switch to 1.8V */
  462. udelay(5000);
  463. }
  464. /* Workaround for ESDHC errata ENGcm03648 */
  465. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  466. int timeout = 50000;
  467. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  468. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  469. PRSSTAT_DAT0)) {
  470. udelay(100);
  471. timeout--;
  472. }
  473. if (timeout <= 0) {
  474. printf("Timeout waiting for DAT0 to go high!\n");
  475. err = -ETIMEDOUT;
  476. goto out;
  477. }
  478. }
  479. /* Copy the response to the response buffer */
  480. if (cmd->resp_type & MMC_RSP_136) {
  481. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  482. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  483. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  484. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  485. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  486. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  487. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  488. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  489. cmd->response[3] = (cmdrsp0 << 8);
  490. } else
  491. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  492. /* Wait until all of the blocks are transferred */
  493. if (data) {
  494. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  495. esdhc_pio_read_write(priv, data);
  496. #else
  497. flags = DATA_COMPLETE;
  498. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  499. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  500. flags = IRQSTAT_BRR;
  501. }
  502. do {
  503. irqstat = esdhc_read32(&regs->irqstat);
  504. if (irqstat & IRQSTAT_DTOE) {
  505. err = -ETIMEDOUT;
  506. goto out;
  507. }
  508. if (irqstat & DATA_ERR) {
  509. err = -ECOMM;
  510. goto out;
  511. }
  512. } while ((irqstat & flags) != flags);
  513. /*
  514. * Need invalidate the dcache here again to avoid any
  515. * cache-fill during the DMA operations such as the
  516. * speculative pre-fetching etc.
  517. */
  518. if (data->flags & MMC_DATA_READ) {
  519. check_and_invalidate_dcache_range(cmd, data);
  520. #ifdef CONFIG_MCF5441x
  521. sd_swap_dma_buff(data);
  522. #endif
  523. }
  524. #endif
  525. }
  526. out:
  527. /* Reset CMD and DATA portions on error */
  528. if (err) {
  529. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  530. SYSCTL_RSTC);
  531. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  532. ;
  533. if (data) {
  534. esdhc_write32(&regs->sysctl,
  535. esdhc_read32(&regs->sysctl) |
  536. SYSCTL_RSTD);
  537. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  538. ;
  539. }
  540. /* If this was CMD11, then notify that power cycle is needed */
  541. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  542. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  543. }
  544. esdhc_write32(&regs->irqstat, -1);
  545. return err;
  546. }
  547. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  548. {
  549. struct fsl_esdhc *regs = priv->esdhc_regs;
  550. int div = 1;
  551. #ifdef ARCH_MXC
  552. #ifdef CONFIG_MX53
  553. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  554. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  555. #else
  556. int pre_div = 1;
  557. #endif
  558. #else
  559. int pre_div = 2;
  560. #endif
  561. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  562. int sdhc_clk = priv->sdhc_clk;
  563. uint clk;
  564. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  565. pre_div *= 2;
  566. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  567. div++;
  568. pre_div >>= 1;
  569. div -= 1;
  570. clk = (pre_div << 8) | (div << 4);
  571. #ifdef CONFIG_FSL_USDHC
  572. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  573. #else
  574. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  575. #endif
  576. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  577. udelay(10000);
  578. #ifdef CONFIG_FSL_USDHC
  579. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  580. #else
  581. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  582. #endif
  583. priv->clock = clock;
  584. }
  585. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  586. static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
  587. {
  588. struct fsl_esdhc *regs = priv->esdhc_regs;
  589. u32 value;
  590. u32 time_out;
  591. value = esdhc_read32(&regs->sysctl);
  592. if (enable)
  593. value |= SYSCTL_CKEN;
  594. else
  595. value &= ~SYSCTL_CKEN;
  596. esdhc_write32(&regs->sysctl, value);
  597. time_out = 20;
  598. value = PRSSTAT_SDSTB;
  599. while (!(esdhc_read32(&regs->prsstat) & value)) {
  600. if (time_out == 0) {
  601. printf("fsl_esdhc: Internal clock never stabilised.\n");
  602. break;
  603. }
  604. time_out--;
  605. mdelay(1);
  606. }
  607. }
  608. #endif
  609. #ifdef MMC_SUPPORTS_TUNING
  610. static int esdhc_change_pinstate(struct udevice *dev)
  611. {
  612. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  613. int ret;
  614. switch (priv->mode) {
  615. case UHS_SDR50:
  616. case UHS_DDR50:
  617. ret = pinctrl_select_state(dev, "state_100mhz");
  618. break;
  619. case UHS_SDR104:
  620. case MMC_HS_200:
  621. case MMC_HS_400:
  622. case MMC_HS_400_ES:
  623. ret = pinctrl_select_state(dev, "state_200mhz");
  624. break;
  625. default:
  626. ret = pinctrl_select_state(dev, "default");
  627. break;
  628. }
  629. if (ret)
  630. printf("%s %d error\n", __func__, priv->mode);
  631. return ret;
  632. }
  633. static void esdhc_reset_tuning(struct mmc *mmc)
  634. {
  635. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  636. struct fsl_esdhc *regs = priv->esdhc_regs;
  637. if (priv->flags & ESDHC_FLAG_USDHC) {
  638. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  639. esdhc_clrbits32(&regs->autoc12err,
  640. MIX_CTRL_SMPCLK_SEL |
  641. MIX_CTRL_EXE_TUNE);
  642. }
  643. }
  644. }
  645. static void esdhc_set_strobe_dll(struct mmc *mmc)
  646. {
  647. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  648. struct fsl_esdhc *regs = priv->esdhc_regs;
  649. u32 val;
  650. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  651. writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
  652. /*
  653. * enable strobe dll ctrl and adjust the delay target
  654. * for the uSDHC loopback read clock
  655. */
  656. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  657. (priv->strobe_dll_delay_target <<
  658. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  659. writel(val, &regs->strobe_dllctrl);
  660. /* wait 1us to make sure strobe dll status register stable */
  661. mdelay(1);
  662. val = readl(&regs->strobe_dllstat);
  663. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  664. pr_warn("HS400 strobe DLL status REF not lock!\n");
  665. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  666. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  667. }
  668. }
  669. static int esdhc_set_timing(struct mmc *mmc)
  670. {
  671. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  672. struct fsl_esdhc *regs = priv->esdhc_regs;
  673. u32 mixctrl;
  674. mixctrl = readl(&regs->mixctrl);
  675. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  676. switch (mmc->selected_mode) {
  677. case MMC_LEGACY:
  678. case SD_LEGACY:
  679. esdhc_reset_tuning(mmc);
  680. writel(mixctrl, &regs->mixctrl);
  681. break;
  682. case MMC_HS_400:
  683. case MMC_HS_400_ES:
  684. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  685. writel(mixctrl, &regs->mixctrl);
  686. esdhc_set_strobe_dll(mmc);
  687. break;
  688. case MMC_HS:
  689. case MMC_HS_52:
  690. case MMC_HS_200:
  691. case SD_HS:
  692. case UHS_SDR12:
  693. case UHS_SDR25:
  694. case UHS_SDR50:
  695. case UHS_SDR104:
  696. writel(mixctrl, &regs->mixctrl);
  697. break;
  698. case UHS_DDR50:
  699. case MMC_DDR_52:
  700. mixctrl |= MIX_CTRL_DDREN;
  701. writel(mixctrl, &regs->mixctrl);
  702. break;
  703. default:
  704. printf("Not supported %d\n", mmc->selected_mode);
  705. return -EINVAL;
  706. }
  707. priv->mode = mmc->selected_mode;
  708. return esdhc_change_pinstate(mmc->dev);
  709. }
  710. static int esdhc_set_voltage(struct mmc *mmc)
  711. {
  712. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  713. struct fsl_esdhc *regs = priv->esdhc_regs;
  714. int ret;
  715. priv->signal_voltage = mmc->signal_voltage;
  716. switch (mmc->signal_voltage) {
  717. case MMC_SIGNAL_VOLTAGE_330:
  718. if (priv->vs18_enable)
  719. return -EIO;
  720. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  721. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  722. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  723. if (ret) {
  724. printf("Setting to 3.3V error");
  725. return -EIO;
  726. }
  727. /* Wait for 5ms */
  728. mdelay(5);
  729. }
  730. #endif
  731. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  732. if (!(esdhc_read32(&regs->vendorspec) &
  733. ESDHC_VENDORSPEC_VSELECT))
  734. return 0;
  735. return -EAGAIN;
  736. case MMC_SIGNAL_VOLTAGE_180:
  737. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  738. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  739. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  740. if (ret) {
  741. printf("Setting to 1.8V error");
  742. return -EIO;
  743. }
  744. }
  745. #endif
  746. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  747. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  748. return 0;
  749. return -EAGAIN;
  750. case MMC_SIGNAL_VOLTAGE_120:
  751. return -ENOTSUPP;
  752. default:
  753. return 0;
  754. }
  755. }
  756. static void esdhc_stop_tuning(struct mmc *mmc)
  757. {
  758. struct mmc_cmd cmd;
  759. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  760. cmd.cmdarg = 0;
  761. cmd.resp_type = MMC_RSP_R1b;
  762. dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
  763. }
  764. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  765. {
  766. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  767. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  768. struct fsl_esdhc *regs = priv->esdhc_regs;
  769. struct mmc *mmc = &plat->mmc;
  770. u32 irqstaten = readl(&regs->irqstaten);
  771. u32 irqsigen = readl(&regs->irqsigen);
  772. int i, ret = -ETIMEDOUT;
  773. u32 val, mixctrl;
  774. /* clock tuning is not needed for upto 52MHz */
  775. if (mmc->clock <= 52000000)
  776. return 0;
  777. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  778. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  779. val = readl(&regs->autoc12err);
  780. mixctrl = readl(&regs->mixctrl);
  781. val &= ~MIX_CTRL_SMPCLK_SEL;
  782. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  783. val |= MIX_CTRL_EXE_TUNE;
  784. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  785. writel(val, &regs->autoc12err);
  786. writel(mixctrl, &regs->mixctrl);
  787. }
  788. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  789. mixctrl = readl(&regs->mixctrl);
  790. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  791. writel(mixctrl, &regs->mixctrl);
  792. writel(IRQSTATEN_BRR, &regs->irqstaten);
  793. writel(IRQSTATEN_BRR, &regs->irqsigen);
  794. /*
  795. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  796. * of loops reaches 40 times.
  797. */
  798. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  799. u32 ctrl;
  800. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  801. if (mmc->bus_width == 8)
  802. writel(0x7080, &regs->blkattr);
  803. else if (mmc->bus_width == 4)
  804. writel(0x7040, &regs->blkattr);
  805. } else {
  806. writel(0x7040, &regs->blkattr);
  807. }
  808. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  809. val = readl(&regs->mixctrl);
  810. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  811. writel(val, &regs->mixctrl);
  812. /* We are using STD tuning, no need to check return value */
  813. mmc_send_tuning(mmc, opcode, NULL);
  814. ctrl = readl(&regs->autoc12err);
  815. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  816. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  817. /*
  818. * need to wait some time, make sure sd/mmc fininsh
  819. * send out tuning data, otherwise, the sd/mmc can't
  820. * response to any command when the card still out
  821. * put the tuning data.
  822. */
  823. mdelay(1);
  824. ret = 0;
  825. break;
  826. }
  827. /* Add 1ms delay for SD and eMMC */
  828. mdelay(1);
  829. }
  830. writel(irqstaten, &regs->irqstaten);
  831. writel(irqsigen, &regs->irqsigen);
  832. esdhc_stop_tuning(mmc);
  833. return ret;
  834. }
  835. #endif
  836. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  837. {
  838. struct fsl_esdhc *regs = priv->esdhc_regs;
  839. int ret __maybe_unused;
  840. u32 clock;
  841. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  842. /* Select to use peripheral clock */
  843. esdhc_clock_control(priv, false);
  844. esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
  845. esdhc_clock_control(priv, true);
  846. #endif
  847. /* Set the clock speed */
  848. clock = mmc->clock;
  849. if (clock < mmc->cfg->f_min)
  850. clock = mmc->cfg->f_min;
  851. if (priv->clock != clock)
  852. set_sysctl(priv, mmc, clock);
  853. #ifdef MMC_SUPPORTS_TUNING
  854. if (mmc->clk_disable) {
  855. #ifdef CONFIG_FSL_USDHC
  856. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  857. #else
  858. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  859. #endif
  860. } else {
  861. #ifdef CONFIG_FSL_USDHC
  862. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  863. VENDORSPEC_CKEN);
  864. #else
  865. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  866. #endif
  867. }
  868. if (priv->mode != mmc->selected_mode) {
  869. ret = esdhc_set_timing(mmc);
  870. if (ret) {
  871. printf("esdhc_set_timing error %d\n", ret);
  872. return ret;
  873. }
  874. }
  875. if (priv->signal_voltage != mmc->signal_voltage) {
  876. ret = esdhc_set_voltage(mmc);
  877. if (ret) {
  878. printf("esdhc_set_voltage error %d\n", ret);
  879. return ret;
  880. }
  881. }
  882. #endif
  883. /* Set the bus width */
  884. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  885. if (mmc->bus_width == 4)
  886. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  887. else if (mmc->bus_width == 8)
  888. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  889. return 0;
  890. }
  891. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  892. {
  893. struct fsl_esdhc *regs = priv->esdhc_regs;
  894. ulong start;
  895. /* Reset the entire host controller */
  896. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  897. /* Wait until the controller is available */
  898. start = get_timer(0);
  899. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  900. if (get_timer(start) > 1000)
  901. return -ETIMEDOUT;
  902. }
  903. #if defined(CONFIG_FSL_USDHC)
  904. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  905. esdhc_write32(&regs->mmcboot, 0x0);
  906. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  907. esdhc_write32(&regs->mixctrl, 0x0);
  908. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  909. /* Put VEND_SPEC to default value */
  910. if (priv->vs18_enable)
  911. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  912. ESDHC_VENDORSPEC_VSELECT));
  913. else
  914. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  915. /* Disable DLL_CTRL delay line */
  916. esdhc_write32(&regs->dllctrl, 0x0);
  917. #endif
  918. #ifndef ARCH_MXC
  919. /* Enable cache snooping */
  920. esdhc_write32(&regs->scr, 0x00000040);
  921. #endif
  922. #ifndef CONFIG_FSL_USDHC
  923. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  924. #else
  925. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  926. #endif
  927. /* Set the initial clock speed */
  928. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  929. /* Disable the BRR and BWR bits in IRQSTAT */
  930. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  931. #ifdef CONFIG_MCF5441x
  932. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  933. #else
  934. /* Put the PROCTL reg back to the default */
  935. esdhc_write32(&regs->proctl, PROCTL_INIT);
  936. #endif
  937. /* Set timout to the maximum value */
  938. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  939. return 0;
  940. }
  941. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  942. {
  943. struct fsl_esdhc *regs = priv->esdhc_regs;
  944. int timeout = 1000;
  945. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  946. if (CONFIG_ESDHC_DETECT_QUIRK)
  947. return 1;
  948. #endif
  949. #if CONFIG_IS_ENABLED(DM_MMC)
  950. if (priv->non_removable)
  951. return 1;
  952. #if CONFIG_IS_ENABLED(DM_GPIO)
  953. if (dm_gpio_is_valid(&priv->cd_gpio))
  954. return dm_gpio_get_value(&priv->cd_gpio);
  955. #endif
  956. #endif
  957. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  958. udelay(1000);
  959. return timeout > 0;
  960. }
  961. static int esdhc_reset(struct fsl_esdhc *regs)
  962. {
  963. ulong start;
  964. /* reset the controller */
  965. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  966. /* hardware clears the bit when it is done */
  967. start = get_timer(0);
  968. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  969. if (get_timer(start) > 100) {
  970. printf("MMC/SD: Reset never completed.\n");
  971. return -ETIMEDOUT;
  972. }
  973. }
  974. return 0;
  975. }
  976. #if !CONFIG_IS_ENABLED(DM_MMC)
  977. static int esdhc_getcd(struct mmc *mmc)
  978. {
  979. struct fsl_esdhc_priv *priv = mmc->priv;
  980. return esdhc_getcd_common(priv);
  981. }
  982. static int esdhc_init(struct mmc *mmc)
  983. {
  984. struct fsl_esdhc_priv *priv = mmc->priv;
  985. return esdhc_init_common(priv, mmc);
  986. }
  987. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  988. struct mmc_data *data)
  989. {
  990. struct fsl_esdhc_priv *priv = mmc->priv;
  991. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  992. }
  993. static int esdhc_set_ios(struct mmc *mmc)
  994. {
  995. struct fsl_esdhc_priv *priv = mmc->priv;
  996. return esdhc_set_ios_common(priv, mmc);
  997. }
  998. static const struct mmc_ops esdhc_ops = {
  999. .getcd = esdhc_getcd,
  1000. .init = esdhc_init,
  1001. .send_cmd = esdhc_send_cmd,
  1002. .set_ios = esdhc_set_ios,
  1003. };
  1004. #endif
  1005. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  1006. struct fsl_esdhc_plat *plat)
  1007. {
  1008. struct mmc_config *cfg;
  1009. struct fsl_esdhc *regs;
  1010. u32 caps, voltage_caps;
  1011. int ret;
  1012. if (!priv)
  1013. return -EINVAL;
  1014. regs = priv->esdhc_regs;
  1015. /* First reset the eSDHC controller */
  1016. ret = esdhc_reset(regs);
  1017. if (ret)
  1018. return ret;
  1019. #ifdef CONFIG_MCF5441x
  1020. /* ColdFire, using SDHC_DATA[3] for card detection */
  1021. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  1022. #endif
  1023. #ifndef CONFIG_FSL_USDHC
  1024. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  1025. | SYSCTL_IPGEN | SYSCTL_CKEN);
  1026. /* Clearing tuning bits in case ROM has set it already */
  1027. esdhc_write32(&regs->mixctrl, 0);
  1028. esdhc_write32(&regs->autoc12err, 0);
  1029. esdhc_write32(&regs->clktunectrlstatus, 0);
  1030. #else
  1031. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1032. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1033. #endif
  1034. if (priv->vs18_enable)
  1035. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1036. writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
  1037. cfg = &plat->cfg;
  1038. #ifndef CONFIG_DM_MMC
  1039. memset(cfg, '\0', sizeof(*cfg));
  1040. #endif
  1041. voltage_caps = 0;
  1042. caps = esdhc_read32(&regs->hostcapblt);
  1043. #ifdef CONFIG_MCF5441x
  1044. /*
  1045. * MCF5441x RM declares in more points that sdhc clock speed must
  1046. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1047. * from host capabilities.
  1048. */
  1049. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1050. #endif
  1051. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1052. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1053. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1054. #endif
  1055. /* T4240 host controller capabilities register should have VS33 bit */
  1056. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  1057. caps = caps | ESDHC_HOSTCAPBLT_VS33;
  1058. #endif
  1059. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1060. voltage_caps |= MMC_VDD_165_195;
  1061. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1062. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1063. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1064. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1065. cfg->name = "FSL_SDHC";
  1066. #if !CONFIG_IS_ENABLED(DM_MMC)
  1067. cfg->ops = &esdhc_ops;
  1068. #endif
  1069. #ifdef CONFIG_SYS_SD_VOLTAGE
  1070. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1071. #else
  1072. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1073. #endif
  1074. if ((cfg->voltages & voltage_caps) == 0) {
  1075. printf("voltage not supported by controller\n");
  1076. return -1;
  1077. }
  1078. if (priv->bus_width == 8)
  1079. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1080. else if (priv->bus_width == 4)
  1081. cfg->host_caps = MMC_MODE_4BIT;
  1082. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1083. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1084. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1085. #endif
  1086. if (priv->bus_width > 0) {
  1087. if (priv->bus_width < 8)
  1088. cfg->host_caps &= ~MMC_MODE_8BIT;
  1089. if (priv->bus_width < 4)
  1090. cfg->host_caps &= ~MMC_MODE_4BIT;
  1091. }
  1092. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1093. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1094. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1095. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1096. cfg->host_caps &= ~MMC_MODE_8BIT;
  1097. #endif
  1098. cfg->host_caps |= priv->caps;
  1099. cfg->f_min = 400000;
  1100. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1101. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1102. writel(0, &regs->dllctrl);
  1103. if (priv->flags & ESDHC_FLAG_USDHC) {
  1104. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1105. u32 val = readl(&regs->tuning_ctrl);
  1106. val |= ESDHC_STD_TUNING_EN;
  1107. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1108. val |= priv->tuning_start_tap;
  1109. val &= ~ESDHC_TUNING_STEP_MASK;
  1110. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1111. writel(val, &regs->tuning_ctrl);
  1112. }
  1113. }
  1114. return 0;
  1115. }
  1116. #if !CONFIG_IS_ENABLED(DM_MMC)
  1117. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1118. struct fsl_esdhc_priv *priv)
  1119. {
  1120. if (!cfg || !priv)
  1121. return -EINVAL;
  1122. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1123. priv->bus_width = cfg->max_bus_width;
  1124. priv->sdhc_clk = cfg->sdhc_clk;
  1125. priv->wp_enable = cfg->wp_enable;
  1126. priv->vs18_enable = cfg->vs18_enable;
  1127. return 0;
  1128. };
  1129. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
  1130. {
  1131. struct fsl_esdhc_plat *plat;
  1132. struct fsl_esdhc_priv *priv;
  1133. struct mmc *mmc;
  1134. int ret;
  1135. if (!cfg)
  1136. return -EINVAL;
  1137. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1138. if (!priv)
  1139. return -ENOMEM;
  1140. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1141. if (!plat) {
  1142. free(priv);
  1143. return -ENOMEM;
  1144. }
  1145. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1146. if (ret) {
  1147. debug("%s xlate failure\n", __func__);
  1148. free(plat);
  1149. free(priv);
  1150. return ret;
  1151. }
  1152. ret = fsl_esdhc_init(priv, plat);
  1153. if (ret) {
  1154. debug("%s init failure\n", __func__);
  1155. free(plat);
  1156. free(priv);
  1157. return ret;
  1158. }
  1159. mmc = mmc_create(&plat->cfg, priv);
  1160. if (!mmc)
  1161. return -EIO;
  1162. priv->mmc = mmc;
  1163. return 0;
  1164. }
  1165. int fsl_esdhc_mmc_init(bd_t *bis)
  1166. {
  1167. struct fsl_esdhc_cfg *cfg;
  1168. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1169. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1170. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1171. return fsl_esdhc_initialize(bis, cfg);
  1172. }
  1173. #endif
  1174. #ifdef CONFIG_OF_LIBFDT
  1175. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1176. {
  1177. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1178. if (!hwconfig("esdhc")) {
  1179. do_fixup_by_compat(blob, compat, "status", "disabled",
  1180. sizeof("disabled"), 1);
  1181. return 1;
  1182. }
  1183. #endif
  1184. return 0;
  1185. }
  1186. void fdt_fixup_esdhc(void *blob, bd_t *bd)
  1187. {
  1188. const char *compat = "fsl,esdhc";
  1189. if (esdhc_status_fixup(blob, compat))
  1190. return;
  1191. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  1192. do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
  1193. gd->arch.sdhc_clk, 1);
  1194. #else
  1195. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1196. gd->arch.sdhc_clk, 1);
  1197. #endif
  1198. }
  1199. #endif
  1200. #if CONFIG_IS_ENABLED(DM_MMC)
  1201. #include <asm/arch/clock.h>
  1202. __weak void init_clk_usdhc(u32 index)
  1203. {
  1204. }
  1205. static int fsl_esdhc_probe(struct udevice *dev)
  1206. {
  1207. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1208. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1209. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1210. const void *fdt = gd->fdt_blob;
  1211. int node = dev_of_offset(dev);
  1212. struct esdhc_soc_data *data =
  1213. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1214. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1215. struct udevice *vqmmc_dev;
  1216. #endif
  1217. fdt_addr_t addr;
  1218. unsigned int val;
  1219. struct mmc *mmc;
  1220. #if !CONFIG_IS_ENABLED(BLK)
  1221. struct blk_desc *bdesc;
  1222. #endif
  1223. int ret;
  1224. addr = dev_read_addr(dev);
  1225. if (addr == FDT_ADDR_T_NONE)
  1226. return -EINVAL;
  1227. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1228. priv->dev = dev;
  1229. priv->mode = -1;
  1230. if (data)
  1231. priv->flags = data->flags;
  1232. val = dev_read_u32_default(dev, "bus-width", -1);
  1233. if (val == 8)
  1234. priv->bus_width = 8;
  1235. else if (val == 4)
  1236. priv->bus_width = 4;
  1237. else
  1238. priv->bus_width = 1;
  1239. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1240. priv->tuning_step = val;
  1241. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1242. ESDHC_TUNING_START_TAP_DEFAULT);
  1243. priv->tuning_start_tap = val;
  1244. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1245. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1246. priv->strobe_dll_delay_target = val;
  1247. if (dev_read_bool(dev, "non-removable")) {
  1248. priv->non_removable = 1;
  1249. } else {
  1250. priv->non_removable = 0;
  1251. #if CONFIG_IS_ENABLED(DM_GPIO)
  1252. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1253. GPIOD_IS_IN);
  1254. #endif
  1255. }
  1256. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1257. priv->wp_enable = 1;
  1258. } else {
  1259. priv->wp_enable = 0;
  1260. #if CONFIG_IS_ENABLED(DM_GPIO)
  1261. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1262. GPIOD_IS_IN);
  1263. #endif
  1264. }
  1265. priv->vs18_enable = 0;
  1266. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1267. /*
  1268. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1269. * otherwise, emmc will work abnormally.
  1270. */
  1271. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1272. if (ret) {
  1273. dev_dbg(dev, "no vqmmc-supply\n");
  1274. } else {
  1275. ret = regulator_set_enable(vqmmc_dev, true);
  1276. if (ret) {
  1277. dev_err(dev, "fail to enable vqmmc-supply\n");
  1278. return ret;
  1279. }
  1280. if (regulator_get_value(vqmmc_dev) == 1800000)
  1281. priv->vs18_enable = 1;
  1282. }
  1283. #endif
  1284. /*
  1285. * TODO:
  1286. * Because lack of clk driver, if SDHC clk is not enabled,
  1287. * need to enable it first before this driver is invoked.
  1288. *
  1289. * we use MXC_ESDHC_CLK to get clk freq.
  1290. * If one would like to make this function work,
  1291. * the aliases should be provided in dts as this:
  1292. *
  1293. * aliases {
  1294. * mmc0 = &usdhc1;
  1295. * mmc1 = &usdhc2;
  1296. * mmc2 = &usdhc3;
  1297. * mmc3 = &usdhc4;
  1298. * };
  1299. * Then if your board only supports mmc2 and mmc3, but we can
  1300. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1301. * work as expected.
  1302. */
  1303. init_clk_usdhc(dev->seq);
  1304. if (CONFIG_IS_ENABLED(CLK)) {
  1305. /* Assigned clock already set clock */
  1306. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1307. if (ret) {
  1308. printf("Failed to get per_clk\n");
  1309. return ret;
  1310. }
  1311. ret = clk_enable(&priv->per_clk);
  1312. if (ret) {
  1313. printf("Failed to enable per_clk\n");
  1314. return ret;
  1315. }
  1316. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1317. } else {
  1318. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  1319. if (priv->sdhc_clk <= 0) {
  1320. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1321. return -EINVAL;
  1322. }
  1323. }
  1324. ret = fsl_esdhc_init(priv, plat);
  1325. if (ret) {
  1326. dev_err(dev, "fsl_esdhc_init failure\n");
  1327. return ret;
  1328. }
  1329. ret = mmc_of_parse(dev, &plat->cfg);
  1330. if (ret)
  1331. return ret;
  1332. mmc = &plat->mmc;
  1333. mmc->cfg = &plat->cfg;
  1334. mmc->dev = dev;
  1335. #if !CONFIG_IS_ENABLED(BLK)
  1336. mmc->priv = priv;
  1337. /* Setup dsr related values */
  1338. mmc->dsr_imp = 0;
  1339. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1340. /* Setup the universal parts of the block interface just once */
  1341. bdesc = mmc_get_blk_desc(mmc);
  1342. bdesc->if_type = IF_TYPE_MMC;
  1343. bdesc->removable = 1;
  1344. bdesc->devnum = mmc_get_next_devnum();
  1345. bdesc->block_read = mmc_bread;
  1346. bdesc->block_write = mmc_bwrite;
  1347. bdesc->block_erase = mmc_berase;
  1348. /* setup initial part type */
  1349. bdesc->part_type = mmc->cfg->part_type;
  1350. mmc_list_add(mmc);
  1351. #endif
  1352. upriv->mmc = mmc;
  1353. return esdhc_init_common(priv, mmc);
  1354. }
  1355. #if CONFIG_IS_ENABLED(DM_MMC)
  1356. static int fsl_esdhc_get_cd(struct udevice *dev)
  1357. {
  1358. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1359. return esdhc_getcd_common(priv);
  1360. }
  1361. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1362. struct mmc_data *data)
  1363. {
  1364. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1365. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1366. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1367. }
  1368. static int fsl_esdhc_set_ios(struct udevice *dev)
  1369. {
  1370. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1371. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1372. return esdhc_set_ios_common(priv, &plat->mmc);
  1373. }
  1374. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1375. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1376. {
  1377. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1378. struct fsl_esdhc *regs = priv->esdhc_regs;
  1379. u32 m;
  1380. m = readl(&regs->mixctrl);
  1381. m |= MIX_CTRL_HS400_ES;
  1382. writel(m, &regs->mixctrl);
  1383. return 0;
  1384. }
  1385. #endif
  1386. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1387. .get_cd = fsl_esdhc_get_cd,
  1388. .send_cmd = fsl_esdhc_send_cmd,
  1389. .set_ios = fsl_esdhc_set_ios,
  1390. #ifdef MMC_SUPPORTS_TUNING
  1391. .execute_tuning = fsl_esdhc_execute_tuning,
  1392. #endif
  1393. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1394. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1395. #endif
  1396. };
  1397. #endif
  1398. static struct esdhc_soc_data usdhc_imx7d_data = {
  1399. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1400. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1401. | ESDHC_FLAG_HS400,
  1402. };
  1403. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1404. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1405. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1406. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1407. };
  1408. static const struct udevice_id fsl_esdhc_ids[] = {
  1409. { .compatible = "fsl,imx53-esdhc", },
  1410. { .compatible = "fsl,imx6ul-usdhc", },
  1411. { .compatible = "fsl,imx6sx-usdhc", },
  1412. { .compatible = "fsl,imx6sl-usdhc", },
  1413. { .compatible = "fsl,imx6q-usdhc", },
  1414. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1415. { .compatible = "fsl,imx7ulp-usdhc", },
  1416. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1417. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1418. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1419. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1420. { .compatible = "fsl,esdhc", },
  1421. { /* sentinel */ }
  1422. };
  1423. #if CONFIG_IS_ENABLED(BLK)
  1424. static int fsl_esdhc_bind(struct udevice *dev)
  1425. {
  1426. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1427. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1428. }
  1429. #endif
  1430. U_BOOT_DRIVER(fsl_esdhc) = {
  1431. .name = "fsl-esdhc-mmc",
  1432. .id = UCLASS_MMC,
  1433. .of_match = fsl_esdhc_ids,
  1434. .ops = &fsl_esdhc_ops,
  1435. #if CONFIG_IS_ENABLED(BLK)
  1436. .bind = fsl_esdhc_bind,
  1437. #endif
  1438. .probe = fsl_esdhc_probe,
  1439. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  1440. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  1441. };
  1442. #endif