atmel_pio4.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 device driver
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/gpio.h>
  14. #include <mach/gpio.h>
  15. #include <mach/atmel_pio4.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
  18. {
  19. struct atmel_pio4_port *base = NULL;
  20. switch (port) {
  21. case AT91_PIO_PORTA:
  22. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
  23. break;
  24. case AT91_PIO_PORTB:
  25. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
  26. break;
  27. case AT91_PIO_PORTC:
  28. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
  29. break;
  30. case AT91_PIO_PORTD:
  31. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
  32. break;
  33. default:
  34. printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
  35. port);
  36. break;
  37. }
  38. return base;
  39. }
  40. static int atmel_pio4_config_io_func(u32 port, u32 pin,
  41. u32 func, u32 config)
  42. {
  43. struct atmel_pio4_port *port_base;
  44. u32 reg, mask;
  45. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  46. return -EINVAL;
  47. port_base = atmel_pio4_port_base(port);
  48. if (!port_base)
  49. return -EINVAL;
  50. mask = 1 << pin;
  51. reg = func;
  52. reg |= config;
  53. writel(mask, &port_base->mskr);
  54. writel(reg, &port_base->cfgr);
  55. return 0;
  56. }
  57. int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
  58. {
  59. return atmel_pio4_config_io_func(port, pin,
  60. ATMEL_PIO_CFGR_FUNC_GPIO,
  61. config);
  62. }
  63. int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
  64. {
  65. return atmel_pio4_config_io_func(port, pin,
  66. ATMEL_PIO_CFGR_FUNC_PERIPH_A,
  67. config);
  68. }
  69. int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
  70. {
  71. return atmel_pio4_config_io_func(port, pin,
  72. ATMEL_PIO_CFGR_FUNC_PERIPH_B,
  73. config);
  74. }
  75. int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
  76. {
  77. return atmel_pio4_config_io_func(port, pin,
  78. ATMEL_PIO_CFGR_FUNC_PERIPH_C,
  79. config);
  80. }
  81. int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
  82. {
  83. return atmel_pio4_config_io_func(port, pin,
  84. ATMEL_PIO_CFGR_FUNC_PERIPH_D,
  85. config);
  86. }
  87. int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
  88. {
  89. return atmel_pio4_config_io_func(port, pin,
  90. ATMEL_PIO_CFGR_FUNC_PERIPH_E,
  91. config);
  92. }
  93. int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
  94. {
  95. return atmel_pio4_config_io_func(port, pin,
  96. ATMEL_PIO_CFGR_FUNC_PERIPH_F,
  97. config);
  98. }
  99. int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
  100. {
  101. return atmel_pio4_config_io_func(port, pin,
  102. ATMEL_PIO_CFGR_FUNC_PERIPH_G,
  103. config);
  104. }
  105. int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
  106. {
  107. struct atmel_pio4_port *port_base;
  108. u32 reg, mask;
  109. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  110. return -EINVAL;
  111. port_base = atmel_pio4_port_base(port);
  112. if (!port_base)
  113. return -EINVAL;
  114. mask = 0x01 << pin;
  115. reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
  116. writel(mask, &port_base->mskr);
  117. writel(reg, &port_base->cfgr);
  118. if (value)
  119. writel(mask, &port_base->sodr);
  120. else
  121. writel(mask, &port_base->codr);
  122. return 0;
  123. }
  124. int atmel_pio4_get_pio_input(u32 port, u32 pin)
  125. {
  126. struct atmel_pio4_port *port_base;
  127. u32 reg, mask;
  128. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  129. return -EINVAL;
  130. port_base = atmel_pio4_port_base(port);
  131. if (!port_base)
  132. return -EINVAL;
  133. mask = 0x01 << pin;
  134. reg = ATMEL_PIO_CFGR_FUNC_GPIO;
  135. writel(mask, &port_base->mskr);
  136. writel(reg, &port_base->cfgr);
  137. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  138. }
  139. #if CONFIG_IS_ENABLED(DM_GPIO)
  140. struct atmel_pioctrl_data {
  141. u32 nbanks;
  142. };
  143. struct atmel_pio4_platdata {
  144. struct atmel_pio4_port *reg_base;
  145. };
  146. static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  147. u32 bank)
  148. {
  149. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  150. struct atmel_pio4_port *port_base =
  151. (struct atmel_pio4_port *)((u32)plat->reg_base +
  152. ATMEL_PIO_BANK_OFFSET * bank);
  153. return port_base;
  154. }
  155. static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
  156. {
  157. u32 bank = ATMEL_PIO_BANK(offset);
  158. u32 line = ATMEL_PIO_LINE(offset);
  159. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  160. u32 mask = BIT(line);
  161. writel(mask, &port_base->mskr);
  162. clrbits_le32(&port_base->cfgr,
  163. ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
  164. return 0;
  165. }
  166. static int atmel_pio4_direction_output(struct udevice *dev,
  167. unsigned offset, int value)
  168. {
  169. u32 bank = ATMEL_PIO_BANK(offset);
  170. u32 line = ATMEL_PIO_LINE(offset);
  171. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  172. u32 mask = BIT(line);
  173. writel(mask, &port_base->mskr);
  174. clrsetbits_le32(&port_base->cfgr,
  175. ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
  176. if (value)
  177. writel(mask, &port_base->sodr);
  178. else
  179. writel(mask, &port_base->codr);
  180. return 0;
  181. }
  182. static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
  183. {
  184. u32 bank = ATMEL_PIO_BANK(offset);
  185. u32 line = ATMEL_PIO_LINE(offset);
  186. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  187. u32 mask = BIT(line);
  188. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  189. }
  190. static int atmel_pio4_set_value(struct udevice *dev,
  191. unsigned offset, int value)
  192. {
  193. u32 bank = ATMEL_PIO_BANK(offset);
  194. u32 line = ATMEL_PIO_LINE(offset);
  195. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  196. u32 mask = BIT(line);
  197. if (value)
  198. writel(mask, &port_base->sodr);
  199. else
  200. writel(mask, &port_base->codr);
  201. return 0;
  202. }
  203. static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
  204. {
  205. u32 bank = ATMEL_PIO_BANK(offset);
  206. u32 line = ATMEL_PIO_LINE(offset);
  207. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  208. u32 mask = BIT(line);
  209. writel(mask, &port_base->mskr);
  210. return (readl(&port_base->cfgr) &
  211. ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
  212. }
  213. static const struct dm_gpio_ops atmel_pio4_ops = {
  214. .direction_input = atmel_pio4_direction_input,
  215. .direction_output = atmel_pio4_direction_output,
  216. .get_value = atmel_pio4_get_value,
  217. .set_value = atmel_pio4_set_value,
  218. .get_function = atmel_pio4_get_function,
  219. };
  220. static int atmel_pio4_bind(struct udevice *dev)
  221. {
  222. return dm_scan_fdt_dev(dev);
  223. }
  224. static int atmel_pio4_probe(struct udevice *dev)
  225. {
  226. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  227. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  228. struct atmel_pioctrl_data *pioctrl_data;
  229. struct clk clk;
  230. fdt_addr_t addr_base;
  231. u32 nbanks;
  232. int ret;
  233. ret = clk_get_by_index(dev, 0, &clk);
  234. if (ret)
  235. return ret;
  236. ret = clk_enable(&clk);
  237. if (ret)
  238. return ret;
  239. clk_free(&clk);
  240. addr_base = devfdt_get_addr(dev);
  241. if (addr_base == FDT_ADDR_T_NONE)
  242. return -EINVAL;
  243. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  244. pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
  245. nbanks = pioctrl_data->nbanks;
  246. uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
  247. NULL);
  248. uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
  249. return 0;
  250. }
  251. /*
  252. * The number of banks can be different from a SoC to another one.
  253. * We can have up to 16 banks.
  254. */
  255. static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  256. .nbanks = 4,
  257. };
  258. static const struct udevice_id atmel_pio4_ids[] = {
  259. {
  260. .compatible = "atmel,sama5d2-gpio",
  261. .data = (ulong)&atmel_sama5d2_pioctrl_data,
  262. },
  263. {}
  264. };
  265. U_BOOT_DRIVER(gpio_atmel_pio4) = {
  266. .name = "gpio_atmel_pio4",
  267. .id = UCLASS_GPIO,
  268. .ops = &atmel_pio4_ops,
  269. .probe = atmel_pio4_probe,
  270. .bind = atmel_pio4_bind,
  271. .of_match = atmel_pio4_ids,
  272. .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
  273. };
  274. #endif