fec_mxc.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  4. * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  5. * (C) Copyright 2008 Armadeus Systems nc
  6. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <memalign.h>
  16. #include <miiphy.h>
  17. #include <net.h>
  18. #include <netdev.h>
  19. #include <asm/cache.h>
  20. #include <linux/delay.h>
  21. #include <power/regulator.h>
  22. #include <asm/io.h>
  23. #include <linux/errno.h>
  24. #include <linux/compiler.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/imx-regs.h>
  27. #include <asm/mach-imx/sys_proto.h>
  28. #include <asm-generic/gpio.h>
  29. #include "fec_mxc.h"
  30. #include <eth_phy.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /*
  33. * Timeout the transfer after 5 mS. This is usually a bit more, since
  34. * the code in the tightloops this timeout is used in adds some overhead.
  35. */
  36. #define FEC_XFER_TIMEOUT 5000
  37. /*
  38. * The standard 32-byte DMA alignment does not work on mx6solox, which requires
  39. * 64-byte alignment in the DMA RX FEC buffer.
  40. * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
  41. * satisfies the alignment on other SoCs (32-bytes)
  42. */
  43. #define FEC_DMA_RX_MINALIGN 64
  44. #ifndef CONFIG_MII
  45. #error "CONFIG_MII has to be defined!"
  46. #endif
  47. #ifndef CONFIG_FEC_XCV_TYPE
  48. #define CONFIG_FEC_XCV_TYPE MII100
  49. #endif
  50. /*
  51. * The i.MX28 operates with packets in big endian. We need to swap them before
  52. * sending and after receiving.
  53. */
  54. #ifdef CONFIG_MX28
  55. #define CONFIG_FEC_MXC_SWAP_PACKET
  56. #endif
  57. #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
  58. /* Check various alignment issues at compile time */
  59. #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
  60. #error "ARCH_DMA_MINALIGN must be multiple of 16!"
  61. #endif
  62. #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
  63. (PKTALIGN % ARCH_DMA_MINALIGN != 0))
  64. #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
  65. #endif
  66. #undef DEBUG
  67. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  68. static void swap_packet(uint32_t *packet, int length)
  69. {
  70. int i;
  71. for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
  72. packet[i] = __swab32(packet[i]);
  73. }
  74. #endif
  75. /* MII-interface related functions */
  76. static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
  77. uint8_t regaddr)
  78. {
  79. uint32_t reg; /* convenient holder for the PHY register */
  80. uint32_t phy; /* convenient holder for the PHY */
  81. uint32_t start;
  82. int val;
  83. /*
  84. * reading from any PHY's register is done by properly
  85. * programming the FEC's MII data register.
  86. */
  87. writel(FEC_IEVENT_MII, &eth->ievent);
  88. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  89. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  90. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
  91. phy | reg, &eth->mii_data);
  92. /* wait for the related interrupt */
  93. start = get_timer(0);
  94. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  95. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  96. printf("Read MDIO failed...\n");
  97. return -1;
  98. }
  99. }
  100. /* clear mii interrupt bit */
  101. writel(FEC_IEVENT_MII, &eth->ievent);
  102. /* it's now safe to read the PHY's register */
  103. val = (unsigned short)readl(&eth->mii_data);
  104. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  105. regaddr, val);
  106. return val;
  107. }
  108. #ifndef imx_get_fecclk
  109. u32 __weak imx_get_fecclk(void)
  110. {
  111. return 0;
  112. }
  113. #endif
  114. static int fec_get_clk_rate(void *udev, int idx)
  115. {
  116. struct fec_priv *fec;
  117. struct udevice *dev;
  118. int ret;
  119. if (IS_ENABLED(CONFIG_IMX8) ||
  120. CONFIG_IS_ENABLED(CLK_CCF)) {
  121. dev = udev;
  122. if (!dev) {
  123. ret = uclass_get_device(UCLASS_ETH, idx, &dev);
  124. if (ret < 0) {
  125. debug("Can't get FEC udev: %d\n", ret);
  126. return ret;
  127. }
  128. }
  129. fec = dev_get_priv(dev);
  130. if (fec)
  131. return fec->clk_rate;
  132. return -EINVAL;
  133. } else {
  134. return imx_get_fecclk();
  135. }
  136. }
  137. static void fec_mii_setspeed(struct ethernet_regs *eth)
  138. {
  139. /*
  140. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  141. * and do not drop the Preamble.
  142. *
  143. * The i.MX28 and i.MX6 types have another field in the MSCR (aka
  144. * MII_SPEED) register that defines the MDIO output hold time. Earlier
  145. * versions are RAZ there, so just ignore the difference and write the
  146. * register always.
  147. * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
  148. * HOLDTIME + 1 is the number of clk cycles the fec is holding the
  149. * output.
  150. * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
  151. * Given that ceil(clkrate / 5000000) <= 64, the calculation for
  152. * holdtime cannot result in a value greater than 3.
  153. */
  154. u32 pclk;
  155. u32 speed;
  156. u32 hold;
  157. int ret;
  158. ret = fec_get_clk_rate(NULL, 0);
  159. if (ret < 0) {
  160. printf("Can't find FEC0 clk rate: %d\n", ret);
  161. return;
  162. }
  163. pclk = ret;
  164. speed = DIV_ROUND_UP(pclk, 5000000);
  165. hold = DIV_ROUND_UP(pclk, 100000000) - 1;
  166. #ifdef FEC_QUIRK_ENET_MAC
  167. speed--;
  168. #endif
  169. writel(speed << 1 | hold << 8, &eth->mii_speed);
  170. debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
  171. }
  172. static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
  173. uint8_t regaddr, uint16_t data)
  174. {
  175. uint32_t reg; /* convenient holder for the PHY register */
  176. uint32_t phy; /* convenient holder for the PHY */
  177. uint32_t start;
  178. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  179. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  180. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  181. FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
  182. /* wait for the MII interrupt */
  183. start = get_timer(0);
  184. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  185. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  186. printf("Write MDIO failed...\n");
  187. return -1;
  188. }
  189. }
  190. /* clear MII interrupt bit */
  191. writel(FEC_IEVENT_MII, &eth->ievent);
  192. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  193. regaddr, data);
  194. return 0;
  195. }
  196. static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
  197. int regaddr)
  198. {
  199. return fec_mdio_read(bus->priv, phyaddr, regaddr);
  200. }
  201. static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
  202. int regaddr, u16 data)
  203. {
  204. return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
  205. }
  206. #ifndef CONFIG_PHYLIB
  207. static int miiphy_restart_aneg(struct eth_device *dev)
  208. {
  209. int ret = 0;
  210. #if !defined(CONFIG_FEC_MXC_NO_ANEG)
  211. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  212. struct ethernet_regs *eth = fec->bus->priv;
  213. /*
  214. * Wake up from sleep if necessary
  215. * Reset PHY, then delay 300ns
  216. */
  217. #ifdef CONFIG_MX27
  218. fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
  219. #endif
  220. fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
  221. udelay(1000);
  222. /* Set the auto-negotiation advertisement register bits */
  223. fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
  224. LPA_100FULL | LPA_100HALF | LPA_10FULL |
  225. LPA_10HALF | PHY_ANLPAR_PSB_802_3);
  226. fec_mdio_write(eth, fec->phy_id, MII_BMCR,
  227. BMCR_ANENABLE | BMCR_ANRESTART);
  228. if (fec->mii_postcall)
  229. ret = fec->mii_postcall(fec->phy_id);
  230. #endif
  231. return ret;
  232. }
  233. #ifndef CONFIG_FEC_FIXED_SPEED
  234. static int miiphy_wait_aneg(struct eth_device *dev)
  235. {
  236. uint32_t start;
  237. int status;
  238. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  239. struct ethernet_regs *eth = fec->bus->priv;
  240. /* Wait for AN completion */
  241. start = get_timer(0);
  242. do {
  243. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  244. printf("%s: Autonegotiation timeout\n", dev->name);
  245. return -1;
  246. }
  247. status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
  248. if (status < 0) {
  249. printf("%s: Autonegotiation failed. status: %d\n",
  250. dev->name, status);
  251. return -1;
  252. }
  253. } while (!(status & BMSR_LSTATUS));
  254. return 0;
  255. }
  256. #endif /* CONFIG_FEC_FIXED_SPEED */
  257. #endif
  258. static int fec_rx_task_enable(struct fec_priv *fec)
  259. {
  260. writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
  261. return 0;
  262. }
  263. static int fec_rx_task_disable(struct fec_priv *fec)
  264. {
  265. return 0;
  266. }
  267. static int fec_tx_task_enable(struct fec_priv *fec)
  268. {
  269. writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
  270. return 0;
  271. }
  272. static int fec_tx_task_disable(struct fec_priv *fec)
  273. {
  274. return 0;
  275. }
  276. /**
  277. * Initialize receive task's buffer descriptors
  278. * @param[in] fec all we know about the device yet
  279. * @param[in] count receive buffer count to be allocated
  280. * @param[in] dsize desired size of each receive buffer
  281. * @return 0 on success
  282. *
  283. * Init all RX descriptors to default values.
  284. */
  285. static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  286. {
  287. uint32_t size;
  288. ulong data;
  289. int i;
  290. /*
  291. * Reload the RX descriptors with default values and wipe
  292. * the RX buffers.
  293. */
  294. size = roundup(dsize, ARCH_DMA_MINALIGN);
  295. for (i = 0; i < count; i++) {
  296. data = fec->rbd_base[i].data_pointer;
  297. memset((void *)data, 0, dsize);
  298. flush_dcache_range(data, data + size);
  299. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  300. fec->rbd_base[i].data_length = 0;
  301. }
  302. /* Mark the last RBD to close the ring. */
  303. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  304. fec->rbd_index = 0;
  305. flush_dcache_range((ulong)fec->rbd_base,
  306. (ulong)fec->rbd_base + size);
  307. }
  308. /**
  309. * Initialize transmit task's buffer descriptors
  310. * @param[in] fec all we know about the device yet
  311. *
  312. * Transmit buffers are created externally. We only have to init the BDs here.\n
  313. * Note: There is a race condition in the hardware. When only one BD is in
  314. * use it must be marked with the WRAP bit to use it for every transmitt.
  315. * This bit in combination with the READY bit results into double transmit
  316. * of each data buffer. It seems the state machine checks READY earlier then
  317. * resetting it after the first transfer.
  318. * Using two BDs solves this issue.
  319. */
  320. static void fec_tbd_init(struct fec_priv *fec)
  321. {
  322. ulong addr = (ulong)fec->tbd_base;
  323. unsigned size = roundup(2 * sizeof(struct fec_bd),
  324. ARCH_DMA_MINALIGN);
  325. memset(fec->tbd_base, 0, size);
  326. fec->tbd_base[0].status = 0;
  327. fec->tbd_base[1].status = FEC_TBD_WRAP;
  328. fec->tbd_index = 0;
  329. flush_dcache_range(addr, addr + size);
  330. }
  331. /**
  332. * Mark the given read buffer descriptor as free
  333. * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  334. * @param[in] prbd buffer descriptor to mark free again
  335. */
  336. static void fec_rbd_clean(int last, struct fec_bd *prbd)
  337. {
  338. unsigned short flags = FEC_RBD_EMPTY;
  339. if (last)
  340. flags |= FEC_RBD_WRAP;
  341. writew(flags, &prbd->status);
  342. writew(0, &prbd->data_length);
  343. }
  344. static int fec_get_hwaddr(int dev_id, unsigned char *mac)
  345. {
  346. imx_get_mac_from_fuse(dev_id, mac);
  347. return !is_valid_ethaddr(mac);
  348. }
  349. #ifdef CONFIG_DM_ETH
  350. static int fecmxc_set_hwaddr(struct udevice *dev)
  351. #else
  352. static int fec_set_hwaddr(struct eth_device *dev)
  353. #endif
  354. {
  355. #ifdef CONFIG_DM_ETH
  356. struct fec_priv *fec = dev_get_priv(dev);
  357. struct eth_pdata *pdata = dev_get_platdata(dev);
  358. uchar *mac = pdata->enetaddr;
  359. #else
  360. uchar *mac = dev->enetaddr;
  361. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  362. #endif
  363. writel(0, &fec->eth->iaddr1);
  364. writel(0, &fec->eth->iaddr2);
  365. writel(0, &fec->eth->gaddr1);
  366. writel(0, &fec->eth->gaddr2);
  367. /* Set physical address */
  368. writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
  369. &fec->eth->paddr1);
  370. writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
  371. return 0;
  372. }
  373. /* Do initial configuration of the FEC registers */
  374. static void fec_reg_setup(struct fec_priv *fec)
  375. {
  376. uint32_t rcntrl;
  377. /* Set interrupt mask register */
  378. writel(0x00000000, &fec->eth->imask);
  379. /* Clear FEC-Lite interrupt event register(IEVENT) */
  380. writel(0xffffffff, &fec->eth->ievent);
  381. /* Set FEC-Lite receive control register(R_CNTRL): */
  382. /* Start with frame length = 1518, common for all modes. */
  383. rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
  384. if (fec->xcv_type != SEVENWIRE) /* xMII modes */
  385. rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
  386. if (fec->xcv_type == RGMII)
  387. rcntrl |= FEC_RCNTRL_RGMII;
  388. else if (fec->xcv_type == RMII)
  389. rcntrl |= FEC_RCNTRL_RMII;
  390. writel(rcntrl, &fec->eth->r_cntrl);
  391. }
  392. /**
  393. * Start the FEC engine
  394. * @param[in] dev Our device to handle
  395. */
  396. #ifdef CONFIG_DM_ETH
  397. static int fec_open(struct udevice *dev)
  398. #else
  399. static int fec_open(struct eth_device *edev)
  400. #endif
  401. {
  402. #ifdef CONFIG_DM_ETH
  403. struct fec_priv *fec = dev_get_priv(dev);
  404. #else
  405. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  406. #endif
  407. int speed;
  408. ulong addr, size;
  409. int i;
  410. debug("fec_open: fec_open(dev)\n");
  411. /* full-duplex, heartbeat disabled */
  412. writel(1 << 2, &fec->eth->x_cntrl);
  413. fec->rbd_index = 0;
  414. /* Invalidate all descriptors */
  415. for (i = 0; i < FEC_RBD_NUM - 1; i++)
  416. fec_rbd_clean(0, &fec->rbd_base[i]);
  417. fec_rbd_clean(1, &fec->rbd_base[i]);
  418. /* Flush the descriptors into RAM */
  419. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
  420. ARCH_DMA_MINALIGN);
  421. addr = (ulong)fec->rbd_base;
  422. flush_dcache_range(addr, addr + size);
  423. #ifdef FEC_QUIRK_ENET_MAC
  424. /* Enable ENET HW endian SWAP */
  425. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
  426. &fec->eth->ecntrl);
  427. /* Enable ENET store and forward mode */
  428. writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
  429. &fec->eth->x_wmrk);
  430. #endif
  431. /* Enable FEC-Lite controller */
  432. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
  433. &fec->eth->ecntrl);
  434. #ifdef FEC_ENET_ENABLE_TXC_DELAY
  435. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
  436. &fec->eth->ecntrl);
  437. #endif
  438. #ifdef FEC_ENET_ENABLE_RXC_DELAY
  439. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
  440. &fec->eth->ecntrl);
  441. #endif
  442. #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
  443. udelay(100);
  444. /* setup the MII gasket for RMII mode */
  445. /* disable the gasket */
  446. writew(0, &fec->eth->miigsk_enr);
  447. /* wait for the gasket to be disabled */
  448. while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
  449. udelay(2);
  450. /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
  451. writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
  452. /* re-enable the gasket */
  453. writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
  454. /* wait until MII gasket is ready */
  455. int max_loops = 10;
  456. while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
  457. if (--max_loops <= 0) {
  458. printf("WAIT for MII Gasket ready timed out\n");
  459. break;
  460. }
  461. }
  462. #endif
  463. #ifdef CONFIG_PHYLIB
  464. {
  465. /* Start up the PHY */
  466. int ret = phy_startup(fec->phydev);
  467. if (ret) {
  468. printf("Could not initialize PHY %s\n",
  469. fec->phydev->dev->name);
  470. return ret;
  471. }
  472. speed = fec->phydev->speed;
  473. }
  474. #elif CONFIG_FEC_FIXED_SPEED
  475. speed = CONFIG_FEC_FIXED_SPEED;
  476. #else
  477. miiphy_wait_aneg(edev);
  478. speed = miiphy_speed(edev->name, fec->phy_id);
  479. miiphy_duplex(edev->name, fec->phy_id);
  480. #endif
  481. #ifdef FEC_QUIRK_ENET_MAC
  482. {
  483. u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
  484. u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
  485. if (speed == _1000BASET)
  486. ecr |= FEC_ECNTRL_SPEED;
  487. else if (speed != _100BASET)
  488. rcr |= FEC_RCNTRL_RMII_10T;
  489. writel(ecr, &fec->eth->ecntrl);
  490. writel(rcr, &fec->eth->r_cntrl);
  491. }
  492. #endif
  493. debug("%s:Speed=%i\n", __func__, speed);
  494. /* Enable SmartDMA receive task */
  495. fec_rx_task_enable(fec);
  496. udelay(100000);
  497. return 0;
  498. }
  499. #ifdef CONFIG_DM_ETH
  500. static int fecmxc_init(struct udevice *dev)
  501. #else
  502. static int fec_init(struct eth_device *dev, struct bd_info *bd)
  503. #endif
  504. {
  505. #ifdef CONFIG_DM_ETH
  506. struct fec_priv *fec = dev_get_priv(dev);
  507. #else
  508. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  509. #endif
  510. u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
  511. u8 *i;
  512. ulong addr;
  513. /* Initialize MAC address */
  514. #ifdef CONFIG_DM_ETH
  515. fecmxc_set_hwaddr(dev);
  516. #else
  517. fec_set_hwaddr(dev);
  518. #endif
  519. /* Setup transmit descriptors, there are two in total. */
  520. fec_tbd_init(fec);
  521. /* Setup receive descriptors. */
  522. fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
  523. fec_reg_setup(fec);
  524. if (fec->xcv_type != SEVENWIRE)
  525. fec_mii_setspeed(fec->bus->priv);
  526. /* Set Opcode/Pause Duration Register */
  527. writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
  528. writel(0x2, &fec->eth->x_wmrk);
  529. /* Set multicast address filter */
  530. writel(0x00000000, &fec->eth->gaddr1);
  531. writel(0x00000000, &fec->eth->gaddr2);
  532. /* Do not access reserved register */
  533. if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
  534. /* clear MIB RAM */
  535. for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
  536. writel(0, i);
  537. /* FIFO receive start register */
  538. writel(0x520, &fec->eth->r_fstart);
  539. }
  540. /* size and address of each buffer */
  541. writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
  542. addr = (ulong)fec->tbd_base;
  543. writel((uint32_t)addr, &fec->eth->etdsr);
  544. addr = (ulong)fec->rbd_base;
  545. writel((uint32_t)addr, &fec->eth->erdsr);
  546. #ifndef CONFIG_PHYLIB
  547. if (fec->xcv_type != SEVENWIRE)
  548. miiphy_restart_aneg(dev);
  549. #endif
  550. fec_open(dev);
  551. return 0;
  552. }
  553. /**
  554. * Halt the FEC engine
  555. * @param[in] dev Our device to handle
  556. */
  557. #ifdef CONFIG_DM_ETH
  558. static void fecmxc_halt(struct udevice *dev)
  559. #else
  560. static void fec_halt(struct eth_device *dev)
  561. #endif
  562. {
  563. #ifdef CONFIG_DM_ETH
  564. struct fec_priv *fec = dev_get_priv(dev);
  565. #else
  566. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  567. #endif
  568. int counter = 0xffff;
  569. /* issue graceful stop command to the FEC transmitter if necessary */
  570. writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
  571. &fec->eth->x_cntrl);
  572. debug("eth_halt: wait for stop regs\n");
  573. /* wait for graceful stop to register */
  574. while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
  575. udelay(1);
  576. /* Disable SmartDMA tasks */
  577. fec_tx_task_disable(fec);
  578. fec_rx_task_disable(fec);
  579. /*
  580. * Disable the Ethernet Controller
  581. * Note: this will also reset the BD index counter!
  582. */
  583. writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
  584. &fec->eth->ecntrl);
  585. fec->rbd_index = 0;
  586. fec->tbd_index = 0;
  587. debug("eth_halt: done\n");
  588. }
  589. /**
  590. * Transmit one frame
  591. * @param[in] dev Our ethernet device to handle
  592. * @param[in] packet Pointer to the data to be transmitted
  593. * @param[in] length Data count in bytes
  594. * @return 0 on success
  595. */
  596. #ifdef CONFIG_DM_ETH
  597. static int fecmxc_send(struct udevice *dev, void *packet, int length)
  598. #else
  599. static int fec_send(struct eth_device *dev, void *packet, int length)
  600. #endif
  601. {
  602. unsigned int status;
  603. u32 size;
  604. ulong addr, end;
  605. int timeout = FEC_XFER_TIMEOUT;
  606. int ret = 0;
  607. /*
  608. * This routine transmits one frame. This routine only accepts
  609. * 6-byte Ethernet addresses.
  610. */
  611. #ifdef CONFIG_DM_ETH
  612. struct fec_priv *fec = dev_get_priv(dev);
  613. #else
  614. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  615. #endif
  616. /*
  617. * Check for valid length of data.
  618. */
  619. if ((length > 1500) || (length <= 0)) {
  620. printf("Payload (%d) too large\n", length);
  621. return -1;
  622. }
  623. /*
  624. * Setup the transmit buffer. We are always using the first buffer for
  625. * transmission, the second will be empty and only used to stop the DMA
  626. * engine. We also flush the packet to RAM here to avoid cache trouble.
  627. */
  628. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  629. swap_packet((uint32_t *)packet, length);
  630. #endif
  631. addr = (ulong)packet;
  632. end = roundup(addr + length, ARCH_DMA_MINALIGN);
  633. addr &= ~(ARCH_DMA_MINALIGN - 1);
  634. flush_dcache_range(addr, end);
  635. writew(length, &fec->tbd_base[fec->tbd_index].data_length);
  636. writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
  637. /*
  638. * update BD's status now
  639. * This block:
  640. * - is always the last in a chain (means no chain)
  641. * - should transmitt the CRC
  642. * - might be the last BD in the list, so the address counter should
  643. * wrap (-> keep the WRAP flag)
  644. */
  645. status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
  646. status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  647. writew(status, &fec->tbd_base[fec->tbd_index].status);
  648. /*
  649. * Flush data cache. This code flushes both TX descriptors to RAM.
  650. * After this code, the descriptors will be safely in RAM and we
  651. * can start DMA.
  652. */
  653. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  654. addr = (ulong)fec->tbd_base;
  655. flush_dcache_range(addr, addr + size);
  656. /*
  657. * Below we read the DMA descriptor's last four bytes back from the
  658. * DRAM. This is important in order to make sure that all WRITE
  659. * operations on the bus that were triggered by previous cache FLUSH
  660. * have completed.
  661. *
  662. * Otherwise, on MX28, it is possible to observe a corruption of the
  663. * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
  664. * for the bus structure of MX28. The scenario is as follows:
  665. *
  666. * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
  667. * to DRAM due to flush_dcache_range()
  668. * 2) ARM core writes the FEC registers via AHB_ARB2
  669. * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
  670. *
  671. * Note that 2) does sometimes finish before 1) due to reordering of
  672. * WRITE accesses on the AHB bus, therefore triggering 3) before the
  673. * DMA descriptor is fully written into DRAM. This results in occasional
  674. * corruption of the DMA descriptor.
  675. */
  676. readl(addr + size - 4);
  677. /* Enable SmartDMA transmit task */
  678. fec_tx_task_enable(fec);
  679. /*
  680. * Wait until frame is sent. On each turn of the wait cycle, we must
  681. * invalidate data cache to see what's really in RAM. Also, we need
  682. * barrier here.
  683. */
  684. while (--timeout) {
  685. if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
  686. break;
  687. }
  688. if (!timeout) {
  689. ret = -EINVAL;
  690. goto out;
  691. }
  692. /*
  693. * The TDAR bit is cleared when the descriptors are all out from TX
  694. * but on mx6solox we noticed that the READY bit is still not cleared
  695. * right after TDAR.
  696. * These are two distinct signals, and in IC simulation, we found that
  697. * TDAR always gets cleared prior than the READY bit of last BD becomes
  698. * cleared.
  699. * In mx6solox, we use a later version of FEC IP. It looks like that
  700. * this intrinsic behaviour of TDAR bit has changed in this newer FEC
  701. * version.
  702. *
  703. * Fix this by polling the READY bit of BD after the TDAR polling,
  704. * which covers the mx6solox case and does not harm the other SoCs.
  705. */
  706. timeout = FEC_XFER_TIMEOUT;
  707. while (--timeout) {
  708. invalidate_dcache_range(addr, addr + size);
  709. if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
  710. FEC_TBD_READY))
  711. break;
  712. }
  713. if (!timeout)
  714. ret = -EINVAL;
  715. out:
  716. debug("fec_send: status 0x%x index %d ret %i\n",
  717. readw(&fec->tbd_base[fec->tbd_index].status),
  718. fec->tbd_index, ret);
  719. /* for next transmission use the other buffer */
  720. if (fec->tbd_index)
  721. fec->tbd_index = 0;
  722. else
  723. fec->tbd_index = 1;
  724. return ret;
  725. }
  726. /**
  727. * Pull one frame from the card
  728. * @param[in] dev Our ethernet device to handle
  729. * @return Length of packet read
  730. */
  731. #ifdef CONFIG_DM_ETH
  732. static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
  733. #else
  734. static int fec_recv(struct eth_device *dev)
  735. #endif
  736. {
  737. #ifdef CONFIG_DM_ETH
  738. struct fec_priv *fec = dev_get_priv(dev);
  739. #else
  740. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  741. #endif
  742. struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
  743. unsigned long ievent;
  744. int frame_length, len = 0;
  745. uint16_t bd_status;
  746. ulong addr, size, end;
  747. int i;
  748. #ifdef CONFIG_DM_ETH
  749. *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
  750. if (*packetp == 0) {
  751. printf("%s: error allocating packetp\n", __func__);
  752. return -ENOMEM;
  753. }
  754. #else
  755. ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
  756. #endif
  757. /* Check if any critical events have happened */
  758. ievent = readl(&fec->eth->ievent);
  759. writel(ievent, &fec->eth->ievent);
  760. debug("fec_recv: ievent 0x%lx\n", ievent);
  761. if (ievent & FEC_IEVENT_BABR) {
  762. #ifdef CONFIG_DM_ETH
  763. fecmxc_halt(dev);
  764. fecmxc_init(dev);
  765. #else
  766. fec_halt(dev);
  767. fec_init(dev, fec->bd);
  768. #endif
  769. printf("some error: 0x%08lx\n", ievent);
  770. return 0;
  771. }
  772. if (ievent & FEC_IEVENT_HBERR) {
  773. /* Heartbeat error */
  774. writel(0x00000001 | readl(&fec->eth->x_cntrl),
  775. &fec->eth->x_cntrl);
  776. }
  777. if (ievent & FEC_IEVENT_GRA) {
  778. /* Graceful stop complete */
  779. if (readl(&fec->eth->x_cntrl) & 0x00000001) {
  780. #ifdef CONFIG_DM_ETH
  781. fecmxc_halt(dev);
  782. #else
  783. fec_halt(dev);
  784. #endif
  785. writel(~0x00000001 & readl(&fec->eth->x_cntrl),
  786. &fec->eth->x_cntrl);
  787. #ifdef CONFIG_DM_ETH
  788. fecmxc_init(dev);
  789. #else
  790. fec_init(dev, fec->bd);
  791. #endif
  792. }
  793. }
  794. /*
  795. * Read the buffer status. Before the status can be read, the data cache
  796. * must be invalidated, because the data in RAM might have been changed
  797. * by DMA. The descriptors are properly aligned to cachelines so there's
  798. * no need to worry they'd overlap.
  799. *
  800. * WARNING: By invalidating the descriptor here, we also invalidate
  801. * the descriptors surrounding this one. Therefore we can NOT change the
  802. * contents of this descriptor nor the surrounding ones. The problem is
  803. * that in order to mark the descriptor as processed, we need to change
  804. * the descriptor. The solution is to mark the whole cache line when all
  805. * descriptors in the cache line are processed.
  806. */
  807. addr = (ulong)rbd;
  808. addr &= ~(ARCH_DMA_MINALIGN - 1);
  809. size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  810. invalidate_dcache_range(addr, addr + size);
  811. bd_status = readw(&rbd->status);
  812. debug("fec_recv: status 0x%x\n", bd_status);
  813. if (!(bd_status & FEC_RBD_EMPTY)) {
  814. if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
  815. ((readw(&rbd->data_length) - 4) > 14)) {
  816. /* Get buffer address and size */
  817. addr = readl(&rbd->data_pointer);
  818. frame_length = readw(&rbd->data_length) - 4;
  819. /* Invalidate data cache over the buffer */
  820. end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
  821. addr &= ~(ARCH_DMA_MINALIGN - 1);
  822. invalidate_dcache_range(addr, end);
  823. /* Fill the buffer and pass it to upper layers */
  824. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  825. swap_packet((uint32_t *)addr, frame_length);
  826. #endif
  827. #ifdef CONFIG_DM_ETH
  828. memcpy(*packetp, (char *)addr, frame_length);
  829. #else
  830. memcpy(buff, (char *)addr, frame_length);
  831. net_process_received_packet(buff, frame_length);
  832. #endif
  833. len = frame_length;
  834. } else {
  835. if (bd_status & FEC_RBD_ERR)
  836. debug("error frame: 0x%08lx 0x%08x\n",
  837. addr, bd_status);
  838. }
  839. /*
  840. * Free the current buffer, restart the engine and move forward
  841. * to the next buffer. Here we check if the whole cacheline of
  842. * descriptors was already processed and if so, we mark it free
  843. * as whole.
  844. */
  845. size = RXDESC_PER_CACHELINE - 1;
  846. if ((fec->rbd_index & size) == size) {
  847. i = fec->rbd_index - size;
  848. addr = (ulong)&fec->rbd_base[i];
  849. for (; i <= fec->rbd_index ; i++) {
  850. fec_rbd_clean(i == (FEC_RBD_NUM - 1),
  851. &fec->rbd_base[i]);
  852. }
  853. flush_dcache_range(addr,
  854. addr + ARCH_DMA_MINALIGN);
  855. }
  856. fec_rx_task_enable(fec);
  857. fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
  858. }
  859. debug("fec_recv: stop\n");
  860. return len;
  861. }
  862. static void fec_set_dev_name(char *dest, int dev_id)
  863. {
  864. sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
  865. }
  866. static int fec_alloc_descs(struct fec_priv *fec)
  867. {
  868. unsigned int size;
  869. int i;
  870. uint8_t *data;
  871. ulong addr;
  872. /* Allocate TX descriptors. */
  873. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  874. fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
  875. if (!fec->tbd_base)
  876. goto err_tx;
  877. /* Allocate RX descriptors. */
  878. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  879. fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
  880. if (!fec->rbd_base)
  881. goto err_rx;
  882. memset(fec->rbd_base, 0, size);
  883. /* Allocate RX buffers. */
  884. /* Maximum RX buffer size. */
  885. size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
  886. for (i = 0; i < FEC_RBD_NUM; i++) {
  887. data = memalign(FEC_DMA_RX_MINALIGN, size);
  888. if (!data) {
  889. printf("%s: error allocating rxbuf %d\n", __func__, i);
  890. goto err_ring;
  891. }
  892. memset(data, 0, size);
  893. addr = (ulong)data;
  894. fec->rbd_base[i].data_pointer = (uint32_t)addr;
  895. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  896. fec->rbd_base[i].data_length = 0;
  897. /* Flush the buffer to memory. */
  898. flush_dcache_range(addr, addr + size);
  899. }
  900. /* Mark the last RBD to close the ring. */
  901. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  902. fec->rbd_index = 0;
  903. fec->tbd_index = 0;
  904. return 0;
  905. err_ring:
  906. for (; i >= 0; i--) {
  907. addr = fec->rbd_base[i].data_pointer;
  908. free((void *)addr);
  909. }
  910. free(fec->rbd_base);
  911. err_rx:
  912. free(fec->tbd_base);
  913. err_tx:
  914. return -ENOMEM;
  915. }
  916. static void fec_free_descs(struct fec_priv *fec)
  917. {
  918. int i;
  919. ulong addr;
  920. for (i = 0; i < FEC_RBD_NUM; i++) {
  921. addr = fec->rbd_base[i].data_pointer;
  922. free((void *)addr);
  923. }
  924. free(fec->rbd_base);
  925. free(fec->tbd_base);
  926. }
  927. struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
  928. {
  929. struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
  930. struct mii_dev *bus;
  931. int ret;
  932. bus = mdio_alloc();
  933. if (!bus) {
  934. printf("mdio_alloc failed\n");
  935. return NULL;
  936. }
  937. bus->read = fec_phy_read;
  938. bus->write = fec_phy_write;
  939. bus->priv = eth;
  940. fec_set_dev_name(bus->name, dev_id);
  941. ret = mdio_register(bus);
  942. if (ret) {
  943. printf("mdio_register failed\n");
  944. free(bus);
  945. return NULL;
  946. }
  947. fec_mii_setspeed(eth);
  948. return bus;
  949. }
  950. #ifndef CONFIG_DM_ETH
  951. #ifdef CONFIG_PHYLIB
  952. int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
  953. struct mii_dev *bus, struct phy_device *phydev)
  954. #else
  955. static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
  956. struct mii_dev *bus, int phy_id)
  957. #endif
  958. {
  959. struct eth_device *edev;
  960. struct fec_priv *fec;
  961. unsigned char ethaddr[6];
  962. char mac[16];
  963. uint32_t start;
  964. int ret = 0;
  965. /* create and fill edev struct */
  966. edev = (struct eth_device *)malloc(sizeof(struct eth_device));
  967. if (!edev) {
  968. puts("fec_mxc: not enough malloc memory for eth_device\n");
  969. ret = -ENOMEM;
  970. goto err1;
  971. }
  972. fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
  973. if (!fec) {
  974. puts("fec_mxc: not enough malloc memory for fec_priv\n");
  975. ret = -ENOMEM;
  976. goto err2;
  977. }
  978. memset(edev, 0, sizeof(*edev));
  979. memset(fec, 0, sizeof(*fec));
  980. ret = fec_alloc_descs(fec);
  981. if (ret)
  982. goto err3;
  983. edev->priv = fec;
  984. edev->init = fec_init;
  985. edev->send = fec_send;
  986. edev->recv = fec_recv;
  987. edev->halt = fec_halt;
  988. edev->write_hwaddr = fec_set_hwaddr;
  989. fec->eth = (struct ethernet_regs *)(ulong)base_addr;
  990. fec->bd = bd;
  991. fec->xcv_type = CONFIG_FEC_XCV_TYPE;
  992. /* Reset chip. */
  993. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
  994. start = get_timer(0);
  995. while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
  996. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  997. printf("FEC MXC: Timeout resetting chip\n");
  998. goto err4;
  999. }
  1000. udelay(10);
  1001. }
  1002. fec_reg_setup(fec);
  1003. fec_set_dev_name(edev->name, dev_id);
  1004. fec->dev_id = (dev_id == -1) ? 0 : dev_id;
  1005. fec->bus = bus;
  1006. fec_mii_setspeed(bus->priv);
  1007. #ifdef CONFIG_PHYLIB
  1008. fec->phydev = phydev;
  1009. phy_connect_dev(phydev, edev);
  1010. /* Configure phy */
  1011. phy_config(phydev);
  1012. #else
  1013. fec->phy_id = phy_id;
  1014. #endif
  1015. eth_register(edev);
  1016. /* only support one eth device, the index number pointed by dev_id */
  1017. edev->index = fec->dev_id;
  1018. if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
  1019. debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
  1020. memcpy(edev->enetaddr, ethaddr, 6);
  1021. if (fec->dev_id)
  1022. sprintf(mac, "eth%daddr", fec->dev_id);
  1023. else
  1024. strcpy(mac, "ethaddr");
  1025. if (!env_get(mac))
  1026. eth_env_set_enetaddr(mac, ethaddr);
  1027. }
  1028. return ret;
  1029. err4:
  1030. fec_free_descs(fec);
  1031. err3:
  1032. free(fec);
  1033. err2:
  1034. free(edev);
  1035. err1:
  1036. return ret;
  1037. }
  1038. int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
  1039. uint32_t addr)
  1040. {
  1041. uint32_t base_mii;
  1042. struct mii_dev *bus = NULL;
  1043. #ifdef CONFIG_PHYLIB
  1044. struct phy_device *phydev = NULL;
  1045. #endif
  1046. int ret;
  1047. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  1048. if (enet_fused((ulong)addr)) {
  1049. printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
  1050. return -ENODEV;
  1051. }
  1052. }
  1053. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1054. /*
  1055. * The i.MX28 has two ethernet interfaces, but they are not equal.
  1056. * Only the first one can access the MDIO bus.
  1057. */
  1058. base_mii = CONFIG_FEC_MXC_MDIO_BASE;
  1059. #else
  1060. base_mii = addr;
  1061. #endif
  1062. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  1063. bus = fec_get_miibus(base_mii, dev_id);
  1064. if (!bus)
  1065. return -ENOMEM;
  1066. #ifdef CONFIG_PHYLIB
  1067. phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
  1068. if (!phydev) {
  1069. mdio_unregister(bus);
  1070. free(bus);
  1071. return -ENOMEM;
  1072. }
  1073. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  1074. #else
  1075. ret = fec_probe(bd, dev_id, addr, bus, phy_id);
  1076. #endif
  1077. if (ret) {
  1078. #ifdef CONFIG_PHYLIB
  1079. free(phydev);
  1080. #endif
  1081. mdio_unregister(bus);
  1082. free(bus);
  1083. }
  1084. return ret;
  1085. }
  1086. #ifdef CONFIG_FEC_MXC_PHYADDR
  1087. int fecmxc_initialize(struct bd_info *bd)
  1088. {
  1089. return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
  1090. IMX_FEC_BASE);
  1091. }
  1092. #endif
  1093. #ifndef CONFIG_PHYLIB
  1094. int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
  1095. {
  1096. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  1097. fec->mii_postcall = cb;
  1098. return 0;
  1099. }
  1100. #endif
  1101. #else
  1102. static int fecmxc_read_rom_hwaddr(struct udevice *dev)
  1103. {
  1104. struct fec_priv *priv = dev_get_priv(dev);
  1105. struct eth_pdata *pdata = dev_get_platdata(dev);
  1106. return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
  1107. }
  1108. static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
  1109. {
  1110. if (packet)
  1111. free(packet);
  1112. return 0;
  1113. }
  1114. static const struct eth_ops fecmxc_ops = {
  1115. .start = fecmxc_init,
  1116. .send = fecmxc_send,
  1117. .recv = fecmxc_recv,
  1118. .free_pkt = fecmxc_free_pkt,
  1119. .stop = fecmxc_halt,
  1120. .write_hwaddr = fecmxc_set_hwaddr,
  1121. .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
  1122. };
  1123. static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
  1124. {
  1125. struct ofnode_phandle_args phandle_args;
  1126. int reg;
  1127. if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  1128. &phandle_args)) {
  1129. debug("Failed to find phy-handle");
  1130. return -ENODEV;
  1131. }
  1132. priv->phy_of_node = phandle_args.node;
  1133. reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
  1134. return reg;
  1135. }
  1136. static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
  1137. {
  1138. struct phy_device *phydev;
  1139. int addr;
  1140. addr = device_get_phy_addr(priv, dev);
  1141. #ifdef CONFIG_FEC_MXC_PHYADDR
  1142. addr = CONFIG_FEC_MXC_PHYADDR;
  1143. #endif
  1144. phydev = phy_connect(priv->bus, addr, dev, priv->interface);
  1145. if (!phydev)
  1146. return -ENODEV;
  1147. priv->phydev = phydev;
  1148. priv->phydev->node = priv->phy_of_node;
  1149. phy_config(phydev);
  1150. return 0;
  1151. }
  1152. #if CONFIG_IS_ENABLED(DM_GPIO)
  1153. /* FEC GPIO reset */
  1154. static void fec_gpio_reset(struct fec_priv *priv)
  1155. {
  1156. debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
  1157. if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
  1158. dm_gpio_set_value(&priv->phy_reset_gpio, 1);
  1159. mdelay(priv->reset_delay);
  1160. dm_gpio_set_value(&priv->phy_reset_gpio, 0);
  1161. if (priv->reset_post_delay)
  1162. mdelay(priv->reset_post_delay);
  1163. }
  1164. }
  1165. #endif
  1166. static int fecmxc_probe(struct udevice *dev)
  1167. {
  1168. struct eth_pdata *pdata = dev_get_platdata(dev);
  1169. struct fec_priv *priv = dev_get_priv(dev);
  1170. struct mii_dev *bus = NULL;
  1171. uint32_t start;
  1172. int ret;
  1173. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  1174. if (enet_fused((ulong)priv->eth)) {
  1175. printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
  1176. return -ENODEV;
  1177. }
  1178. }
  1179. if (IS_ENABLED(CONFIG_IMX8)) {
  1180. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1181. if (ret < 0) {
  1182. debug("Can't get FEC ipg clk: %d\n", ret);
  1183. return ret;
  1184. }
  1185. ret = clk_enable(&priv->ipg_clk);
  1186. if (ret < 0) {
  1187. debug("Can't enable FEC ipg clk: %d\n", ret);
  1188. return ret;
  1189. }
  1190. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1191. } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
  1192. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1193. if (ret < 0) {
  1194. debug("Can't get FEC ipg clk: %d\n", ret);
  1195. return ret;
  1196. }
  1197. ret = clk_enable(&priv->ipg_clk);
  1198. if(ret)
  1199. return ret;
  1200. ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
  1201. if (ret < 0) {
  1202. debug("Can't get FEC ahb clk: %d\n", ret);
  1203. return ret;
  1204. }
  1205. ret = clk_enable(&priv->ahb_clk);
  1206. if (ret)
  1207. return ret;
  1208. ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
  1209. if (!ret) {
  1210. ret = clk_enable(&priv->clk_enet_out);
  1211. if (ret)
  1212. return ret;
  1213. }
  1214. ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
  1215. if (!ret) {
  1216. ret = clk_enable(&priv->clk_ref);
  1217. if (ret)
  1218. return ret;
  1219. }
  1220. ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
  1221. if (!ret) {
  1222. ret = clk_enable(&priv->clk_ptp);
  1223. if (ret)
  1224. return ret;
  1225. }
  1226. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1227. }
  1228. ret = fec_alloc_descs(priv);
  1229. if (ret)
  1230. return ret;
  1231. #ifdef CONFIG_DM_REGULATOR
  1232. if (priv->phy_supply) {
  1233. ret = regulator_set_enable(priv->phy_supply, true);
  1234. if (ret) {
  1235. printf("%s: Error enabling phy supply\n", dev->name);
  1236. return ret;
  1237. }
  1238. }
  1239. #endif
  1240. #if CONFIG_IS_ENABLED(DM_GPIO)
  1241. fec_gpio_reset(priv);
  1242. #endif
  1243. /* Reset chip. */
  1244. writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
  1245. &priv->eth->ecntrl);
  1246. start = get_timer(0);
  1247. while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
  1248. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  1249. printf("FEC MXC: Timeout reseting chip\n");
  1250. goto err_timeout;
  1251. }
  1252. udelay(10);
  1253. }
  1254. fec_reg_setup(priv);
  1255. priv->dev_id = dev->seq;
  1256. #ifdef CONFIG_DM_ETH_PHY
  1257. bus = eth_phy_get_mdio_bus(dev);
  1258. #endif
  1259. if (!bus) {
  1260. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1261. bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
  1262. #else
  1263. bus = fec_get_miibus((ulong)priv->eth, dev->seq);
  1264. #endif
  1265. }
  1266. if (!bus) {
  1267. ret = -ENOMEM;
  1268. goto err_mii;
  1269. }
  1270. #ifdef CONFIG_DM_ETH_PHY
  1271. eth_phy_set_mdio_bus(dev, bus);
  1272. #endif
  1273. priv->bus = bus;
  1274. priv->interface = pdata->phy_interface;
  1275. switch (priv->interface) {
  1276. case PHY_INTERFACE_MODE_MII:
  1277. priv->xcv_type = MII100;
  1278. break;
  1279. case PHY_INTERFACE_MODE_RMII:
  1280. priv->xcv_type = RMII;
  1281. break;
  1282. case PHY_INTERFACE_MODE_RGMII:
  1283. case PHY_INTERFACE_MODE_RGMII_ID:
  1284. case PHY_INTERFACE_MODE_RGMII_RXID:
  1285. case PHY_INTERFACE_MODE_RGMII_TXID:
  1286. priv->xcv_type = RGMII;
  1287. break;
  1288. default:
  1289. priv->xcv_type = CONFIG_FEC_XCV_TYPE;
  1290. printf("Unsupported interface type %d defaulting to %d\n",
  1291. priv->interface, priv->xcv_type);
  1292. break;
  1293. }
  1294. ret = fec_phy_init(priv, dev);
  1295. if (ret)
  1296. goto err_phy;
  1297. return 0;
  1298. err_phy:
  1299. mdio_unregister(bus);
  1300. free(bus);
  1301. err_mii:
  1302. err_timeout:
  1303. fec_free_descs(priv);
  1304. return ret;
  1305. }
  1306. static int fecmxc_remove(struct udevice *dev)
  1307. {
  1308. struct fec_priv *priv = dev_get_priv(dev);
  1309. free(priv->phydev);
  1310. fec_free_descs(priv);
  1311. mdio_unregister(priv->bus);
  1312. mdio_free(priv->bus);
  1313. #ifdef CONFIG_DM_REGULATOR
  1314. if (priv->phy_supply)
  1315. regulator_set_enable(priv->phy_supply, false);
  1316. #endif
  1317. return 0;
  1318. }
  1319. static int fecmxc_ofdata_to_platdata(struct udevice *dev)
  1320. {
  1321. int ret = 0;
  1322. struct eth_pdata *pdata = dev_get_platdata(dev);
  1323. struct fec_priv *priv = dev_get_priv(dev);
  1324. const char *phy_mode;
  1325. pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
  1326. priv->eth = (struct ethernet_regs *)pdata->iobase;
  1327. pdata->phy_interface = -1;
  1328. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1329. NULL);
  1330. if (phy_mode)
  1331. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1332. if (pdata->phy_interface == -1) {
  1333. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1334. return -EINVAL;
  1335. }
  1336. #ifdef CONFIG_DM_REGULATOR
  1337. device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  1338. #endif
  1339. #if CONFIG_IS_ENABLED(DM_GPIO)
  1340. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1341. &priv->phy_reset_gpio, GPIOD_IS_OUT);
  1342. if (ret < 0)
  1343. return 0; /* property is optional, don't return error! */
  1344. priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
  1345. if (priv->reset_delay > 1000) {
  1346. printf("FEC MXC: phy reset duration should be <= 1000ms\n");
  1347. /* property value wrong, use default value */
  1348. priv->reset_delay = 1;
  1349. }
  1350. priv->reset_post_delay = dev_read_u32_default(dev,
  1351. "phy-reset-post-delay",
  1352. 0);
  1353. if (priv->reset_post_delay > 1000) {
  1354. printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
  1355. /* property value wrong, use default value */
  1356. priv->reset_post_delay = 0;
  1357. }
  1358. #endif
  1359. return 0;
  1360. }
  1361. static const struct udevice_id fecmxc_ids[] = {
  1362. { .compatible = "fsl,imx28-fec" },
  1363. { .compatible = "fsl,imx6q-fec" },
  1364. { .compatible = "fsl,imx6sl-fec" },
  1365. { .compatible = "fsl,imx6sx-fec" },
  1366. { .compatible = "fsl,imx6ul-fec" },
  1367. { .compatible = "fsl,imx53-fec" },
  1368. { .compatible = "fsl,imx7d-fec" },
  1369. { .compatible = "fsl,mvf600-fec" },
  1370. { }
  1371. };
  1372. U_BOOT_DRIVER(fecmxc_gem) = {
  1373. .name = "fecmxc",
  1374. .id = UCLASS_ETH,
  1375. .of_match = fecmxc_ids,
  1376. .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
  1377. .probe = fecmxc_probe,
  1378. .remove = fecmxc_remove,
  1379. .ops = &fecmxc_ops,
  1380. .priv_auto_alloc_size = sizeof(struct fec_priv),
  1381. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1382. };
  1383. #endif