ehci-marvell.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <usb.h>
  10. #include "ehci.h"
  11. #include <linux/mbus.h>
  12. #include <asm/arch/cpu.h>
  13. #include <dm.h>
  14. #if defined(CONFIG_ARCH_KIRKWOOD)
  15. #include <asm/arch/soc.h>
  16. #elif defined(CONFIG_ARCH_ORION5X)
  17. #include <asm/arch/orion5x.h>
  18. #endif
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
  21. #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
  22. #define USB_TARGET_DRAM 0x0
  23. #define USB2_SBUSCFG_OFF 0x90
  24. #define USB_SBUSCFG_BAWR_OFF 0x6
  25. #define USB_SBUSCFG_BARD_OFF 0x3
  26. #define USB_SBUSCFG_AHBBRST_OFF 0x0
  27. #define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
  28. #define USB_SBUSCFG_BARD_ALIGN_64B 0x4
  29. #define USB_SBUSCFG_AHBBRST_INCR16 0x7
  30. /*
  31. * USB 2.0 Bridge Address Decoding registers setup
  32. */
  33. #if CONFIG_IS_ENABLED(DM_USB)
  34. struct ehci_mvebu_priv {
  35. struct ehci_ctrl ehci;
  36. fdt_addr_t hcd_base;
  37. };
  38. /*
  39. * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  40. * to the common mvebu archticture including the mbus setup, this
  41. * will be the only function needed to configure the access windows
  42. */
  43. static void usb_brg_adrdec_setup(void *base)
  44. {
  45. const struct mbus_dram_target_info *dram;
  46. int i;
  47. dram = mvebu_mbus_dram_info();
  48. for (i = 0; i < 4; i++) {
  49. writel(0, base + USB_WINDOW_CTRL(i));
  50. writel(0, base + USB_WINDOW_BASE(i));
  51. }
  52. for (i = 0; i < dram->num_cs; i++) {
  53. const struct mbus_dram_window *cs = dram->cs + i;
  54. /* Write size, attributes and target id to control register */
  55. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  56. (dram->mbus_dram_target_id << 4) | 1,
  57. base + USB_WINDOW_CTRL(i));
  58. /* Write base address to base register */
  59. writel(cs->base, base + USB_WINDOW_BASE(i));
  60. }
  61. }
  62. static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
  63. uint32_t *status_reg, uint32_t *reg)
  64. {
  65. struct ehci_mvebu_priv *priv = ctrl->priv;
  66. /*
  67. * Set default value for reg SBUSCFG, which is Control for the AMBA
  68. * system bus interface:
  69. * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
  70. * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
  71. */
  72. writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
  73. (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
  74. (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
  75. priv->hcd_base + USB2_SBUSCFG_OFF);
  76. mdelay(50);
  77. }
  78. static struct ehci_ops marvell_ehci_ops = {
  79. .powerup_fixup = NULL,
  80. };
  81. static int ehci_mvebu_probe(struct udevice *dev)
  82. {
  83. struct ehci_mvebu_priv *priv = dev_get_priv(dev);
  84. struct ehci_hccr *hccr;
  85. struct ehci_hcor *hcor;
  86. /*
  87. * Get the base address for EHCI controller from the device node
  88. */
  89. priv->hcd_base = devfdt_get_addr(dev);
  90. if (priv->hcd_base == FDT_ADDR_T_NONE) {
  91. debug("Can't get the EHCI register base address\n");
  92. return -ENXIO;
  93. }
  94. /*
  95. * For SoCs without hlock like Armada3700 we need to program the sbuscfg
  96. * reg to guarantee AHB master's burst will not overrun or underrun
  97. * the FIFO. Otherwise all USB2 write option will fail.
  98. * Also, the address decoder doesn't need to get setup with this
  99. * SoC, so don't call usb_brg_adrdec_setup().
  100. */
  101. if (device_is_compatible(dev, "marvell,armada3700-ehci"))
  102. marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
  103. else
  104. usb_brg_adrdec_setup((void *)priv->hcd_base);
  105. hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
  106. hcor = (struct ehci_hcor *)
  107. ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  108. debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
  109. (uintptr_t)hccr, (uintptr_t)hcor,
  110. (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  111. return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
  112. USB_INIT_HOST);
  113. }
  114. static const struct udevice_id ehci_usb_ids[] = {
  115. { .compatible = "marvell,orion-ehci", },
  116. { .compatible = "marvell,armada3700-ehci", },
  117. { }
  118. };
  119. U_BOOT_DRIVER(ehci_mvebu) = {
  120. .name = "ehci_mvebu",
  121. .id = UCLASS_USB,
  122. .of_match = ehci_usb_ids,
  123. .probe = ehci_mvebu_probe,
  124. .remove = ehci_deregister,
  125. .ops = &ehci_usb_ops,
  126. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  127. .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
  128. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  129. };
  130. #else
  131. #define MVUSB_BASE(port) MVUSB0_BASE
  132. static void usb_brg_adrdec_setup(int index)
  133. {
  134. int i;
  135. u32 size, base, attrib;
  136. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  137. /* Enable DRAM bank */
  138. switch (i) {
  139. case 0:
  140. attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
  141. break;
  142. case 1:
  143. attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
  144. break;
  145. case 2:
  146. attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
  147. break;
  148. case 3:
  149. attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
  150. break;
  151. default:
  152. /* invalide bank, disable access */
  153. attrib = 0;
  154. break;
  155. }
  156. size = gd->bd->bi_dram[i].size;
  157. base = gd->bd->bi_dram[i].start;
  158. if ((size) && (attrib))
  159. writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
  160. attrib, MVCPU_WIN_ENABLE),
  161. MVUSB0_BASE + USB_WINDOW_CTRL(i));
  162. else
  163. writel(MVCPU_WIN_DISABLE,
  164. MVUSB0_BASE + USB_WINDOW_CTRL(i));
  165. writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
  166. }
  167. }
  168. /*
  169. * Create the appropriate control structures to manage
  170. * a new EHCI host controller.
  171. */
  172. int ehci_hcd_init(int index, enum usb_init_type init,
  173. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  174. {
  175. usb_brg_adrdec_setup(index);
  176. *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
  177. *hcor = (struct ehci_hcor *)((uint32_t) *hccr
  178. + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  179. debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
  180. (uint32_t)*hccr, (uint32_t)*hcor,
  181. (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  182. return 0;
  183. }
  184. /*
  185. * Destroy the appropriate control structures corresponding
  186. * the the EHCI host controller.
  187. */
  188. int ehci_hcd_stop(int index)
  189. {
  190. return 0;
  191. }
  192. #endif /* CONFIG_IS_ENABLED(DM_USB) */