sata_mv.c 27 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, 2010.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
  7. */
  8. /*
  9. * This driver supports the SATA controller of some Mavell SoC's.
  10. * Here a (most likely incomplete) list of the supported SoC's:
  11. * - Kirkwood
  12. * - Armada 370
  13. * - Armada XP
  14. *
  15. * This driver implementation is an alternative to the already available
  16. * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
  17. * But this driver only supports PIO mode and as this new driver also
  18. * supports transfer via DMA, its much faster.
  19. *
  20. * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
  21. * by this driver. As they have an AHCI compatible SATA controller
  22. * integrated.
  23. */
  24. /*
  25. * TODO:
  26. * Better error recovery
  27. * No support for using PRDs (Thus max 64KB transfers)
  28. * No NCQ support
  29. * No port multiplier support
  30. */
  31. #include <common.h>
  32. #include <ahci.h>
  33. #include <cpu_func.h>
  34. #include <dm.h>
  35. #include <dm/device-internal.h>
  36. #include <dm/lists.h>
  37. #include <fis.h>
  38. #include <libata.h>
  39. #include <malloc.h>
  40. #include <sata.h>
  41. #include <linux/errno.h>
  42. #include <asm/io.h>
  43. #include <linux/mbus.h>
  44. #include <asm/arch/soc.h>
  45. #if defined(CONFIG_ARCH_KIRKWOOD)
  46. #define SATAHC_BASE KW_SATA_BASE
  47. #else
  48. #define SATAHC_BASE MVEBU_AXP_SATA_BASE
  49. #endif
  50. #define SATA0_BASE (SATAHC_BASE + 0x2000)
  51. #define SATA1_BASE (SATAHC_BASE + 0x4000)
  52. /* EDMA registers */
  53. #define EDMA_CFG 0x000
  54. #define EDMA_CFG_NCQ (1 << 5)
  55. #define EDMA_CFG_EQUE (1 << 9)
  56. #define EDMA_TIMER 0x004
  57. #define EDMA_IECR 0x008
  58. #define EDMA_IEMR 0x00c
  59. #define EDMA_RQBA_HI 0x010
  60. #define EDMA_RQIPR 0x014
  61. #define EDMA_RQIPR_IPMASK (0x1f << 5)
  62. #define EDMA_RQIPR_IPSHIFT 5
  63. #define EDMA_RQOPR 0x018
  64. #define EDMA_RQOPR_OPMASK (0x1f << 5)
  65. #define EDMA_RQOPR_OPSHIFT 5
  66. #define EDMA_RSBA_HI 0x01c
  67. #define EDMA_RSIPR 0x020
  68. #define EDMA_RSIPR_IPMASK (0x1f << 3)
  69. #define EDMA_RSIPR_IPSHIFT 3
  70. #define EDMA_RSOPR 0x024
  71. #define EDMA_RSOPR_OPMASK (0x1f << 3)
  72. #define EDMA_RSOPR_OPSHIFT 3
  73. #define EDMA_CMD 0x028
  74. #define EDMA_CMD_ENEDMA (0x01 << 0)
  75. #define EDMA_CMD_DISEDMA (0x01 << 1)
  76. #define EDMA_CMD_ATARST (0x01 << 2)
  77. #define EDMA_CMD_FREEZE (0x01 << 4)
  78. #define EDMA_TEST_CTL 0x02c
  79. #define EDMA_STATUS 0x030
  80. #define EDMA_IORTO 0x034
  81. #define EDMA_CDTR 0x040
  82. #define EDMA_HLTCND 0x060
  83. #define EDMA_NTSR 0x094
  84. /* Basic DMA registers */
  85. #define BDMA_CMD 0x224
  86. #define BDMA_STATUS 0x228
  87. #define BDMA_DTLB 0x22c
  88. #define BDMA_DTHB 0x230
  89. #define BDMA_DRL 0x234
  90. #define BDMA_DRH 0x238
  91. /* SATA Interface registers */
  92. #define SIR_ICFG 0x050
  93. #define SIR_CFG_GEN2EN (0x1 << 7)
  94. #define SIR_PLL_CFG 0x054
  95. #define SIR_SSTATUS 0x300
  96. #define SSTATUS_DET_MASK (0x0f << 0)
  97. #define SIR_SERROR 0x304
  98. #define SIR_SCONTROL 0x308
  99. #define SIR_SCONTROL_DETEN (0x01 << 0)
  100. #define SIR_LTMODE 0x30c
  101. #define SIR_LTMODE_NELBE (0x01 << 7)
  102. #define SIR_PHYMODE3 0x310
  103. #define SIR_PHYMODE4 0x314
  104. #define SIR_PHYMODE1 0x32c
  105. #define SIR_PHYMODE2 0x330
  106. #define SIR_BIST_CTRL 0x334
  107. #define SIR_BIST_DW1 0x338
  108. #define SIR_BIST_DW2 0x33c
  109. #define SIR_SERR_IRQ_MASK 0x340
  110. #define SIR_SATA_IFCTRL 0x344
  111. #define SIR_SATA_TESTCTRL 0x348
  112. #define SIR_SATA_IFSTATUS 0x34c
  113. #define SIR_VEND_UNIQ 0x35c
  114. #define SIR_FIS_CFG 0x360
  115. #define SIR_FIS_IRQ_CAUSE 0x364
  116. #define SIR_FIS_IRQ_MASK 0x368
  117. #define SIR_FIS_DWORD0 0x370
  118. #define SIR_FIS_DWORD1 0x374
  119. #define SIR_FIS_DWORD2 0x378
  120. #define SIR_FIS_DWORD3 0x37c
  121. #define SIR_FIS_DWORD4 0x380
  122. #define SIR_FIS_DWORD5 0x384
  123. #define SIR_FIS_DWORD6 0x388
  124. #define SIR_PHYM9_GEN2 0x398
  125. #define SIR_PHYM9_GEN1 0x39c
  126. #define SIR_PHY_CFG 0x3a0
  127. #define SIR_PHYCTL 0x3a4
  128. #define SIR_PHYM10 0x3a8
  129. #define SIR_PHYM12 0x3b0
  130. /* Shadow registers */
  131. #define PIO_DATA 0x100
  132. #define PIO_ERR_FEATURES 0x104
  133. #define PIO_SECTOR_COUNT 0x108
  134. #define PIO_LBA_LOW 0x10c
  135. #define PIO_LBA_MID 0x110
  136. #define PIO_LBA_HI 0x114
  137. #define PIO_DEVICE 0x118
  138. #define PIO_CMD_STATUS 0x11c
  139. #define PIO_STATUS_ERR (0x01 << 0)
  140. #define PIO_STATUS_DRQ (0x01 << 3)
  141. #define PIO_STATUS_DF (0x01 << 5)
  142. #define PIO_STATUS_DRDY (0x01 << 6)
  143. #define PIO_STATUS_BSY (0x01 << 7)
  144. #define PIO_CTRL_ALTSTAT 0x120
  145. /* SATAHC arbiter registers */
  146. #define SATAHC_CFG 0x000
  147. #define SATAHC_RQOP 0x004
  148. #define SATAHC_RQIP 0x008
  149. #define SATAHC_ICT 0x00c
  150. #define SATAHC_ITT 0x010
  151. #define SATAHC_ICR 0x014
  152. #define SATAHC_ICR_PORT0 (0x01 << 0)
  153. #define SATAHC_ICR_PORT1 (0x01 << 1)
  154. #define SATAHC_MIC 0x020
  155. #define SATAHC_MIM 0x024
  156. #define SATAHC_LED_CFG 0x02c
  157. #define REQUEST_QUEUE_SIZE 32
  158. #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
  159. struct crqb {
  160. u32 dtb_low; /* DW0 */
  161. u32 dtb_high; /* DW1 */
  162. u32 control_flags; /* DW2 */
  163. u32 drb_count; /* DW3 */
  164. u32 ata_cmd_feat; /* DW4 */
  165. u32 ata_addr; /* DW5 */
  166. u32 ata_addr_exp; /* DW6 */
  167. u32 ata_sect_count; /* DW7 */
  168. };
  169. #define CRQB_ALIGN 0x400
  170. #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
  171. #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
  172. #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
  173. #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
  174. #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
  175. #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
  176. #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
  177. #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
  178. #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
  179. #define CRQB_CMDFEAT_CMDSHIFT 16
  180. #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
  181. #define CRQB_CMDFEAT_FEATSHIFT 24
  182. #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
  183. #define CRQB_ADDR_LBA_LOWSHIFT 0
  184. #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
  185. #define CRQB_ADDR_LBA_MIDSHIFT 8
  186. #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
  187. #define CRQB_ADDR_LBA_HIGHSHIFT 16
  188. #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
  189. #define CRQB_ADDR_DEVICE_SHIFT 24
  190. #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
  191. #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
  192. #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
  193. #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
  194. #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
  195. #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
  196. #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
  197. #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
  198. #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
  199. #define CRQB_SECTCOUNT_COUNT_SHIFT 0
  200. #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
  201. #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
  202. #define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
  203. #define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
  204. struct eprd {
  205. u32 phyaddr_low;
  206. u32 bytecount_eot;
  207. u32 phyaddr_hi;
  208. u32 reserved;
  209. };
  210. #define EPRD_PHYADDR_MASK 0xfffffffe
  211. #define EPRD_BYTECOUNT_MASK 0x0000ffff
  212. #define EPRD_EOT (0x01 << 31)
  213. struct crpb {
  214. u32 id;
  215. u32 flags;
  216. u32 timestamp;
  217. };
  218. #define CRPB_ALIGN 0x100
  219. #define READ_CMD 0
  220. #define WRITE_CMD 1
  221. /*
  222. * Since we don't use PRDs yet max transfer size
  223. * is 64KB
  224. */
  225. #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
  226. /* Keep track if hw is initialized or not */
  227. static u32 hw_init;
  228. struct mv_priv {
  229. char name[12];
  230. u32 link;
  231. u32 regbase;
  232. u32 queue_depth;
  233. u16 pio;
  234. u16 mwdma;
  235. u16 udma;
  236. int dev_nr;
  237. void *crqb_alloc;
  238. struct crqb *request;
  239. void *crpb_alloc;
  240. struct crpb *response;
  241. };
  242. static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
  243. {
  244. ulong start;
  245. start = get_timer(0);
  246. do {
  247. if ((in_le32(addr) & mask) == val)
  248. return 0;
  249. } while (get_timer(start) < timeout_msec);
  250. return -ETIMEDOUT;
  251. }
  252. /* Cut from sata_mv in linux kernel */
  253. static int mv_stop_edma_engine(struct udevice *dev, int port)
  254. {
  255. struct mv_priv *priv = dev_get_platdata(dev);
  256. int i;
  257. /* Disable eDMA. The disable bit auto clears. */
  258. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
  259. /* Wait for the chip to confirm eDMA is off. */
  260. for (i = 10000; i > 0; i--) {
  261. u32 reg = in_le32(priv->regbase + EDMA_CMD);
  262. if (!(reg & EDMA_CMD_ENEDMA)) {
  263. debug("EDMA stop on port %d succesful\n", port);
  264. return 0;
  265. }
  266. udelay(10);
  267. }
  268. debug("EDMA stop on port %d failed\n", port);
  269. return -1;
  270. }
  271. static int mv_start_edma_engine(struct udevice *dev, int port)
  272. {
  273. struct mv_priv *priv = dev_get_platdata(dev);
  274. u32 tmp;
  275. /* Check preconditions */
  276. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  277. if ((tmp & SSTATUS_DET_MASK) != 0x03) {
  278. printf("Device error on port: %d\n", port);
  279. return -1;
  280. }
  281. tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
  282. if (tmp & (ATA_BUSY | ATA_DRQ)) {
  283. printf("Device not ready on port: %d\n", port);
  284. return -1;
  285. }
  286. /* Clear interrupt cause */
  287. out_le32(priv->regbase + EDMA_IECR, 0x0);
  288. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  289. tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
  290. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  291. /* Configure edma operation */
  292. tmp = in_le32(priv->regbase + EDMA_CFG);
  293. tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
  294. tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
  295. out_le32(priv->regbase + EDMA_CFG, tmp);
  296. out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
  297. /* Configure fis, set all to no-wait for now */
  298. out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
  299. /* Setup request queue */
  300. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  301. out_le32(priv->regbase + EDMA_RQIPR, priv->request);
  302. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  303. /* Setup response queue */
  304. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  305. out_le32(priv->regbase + EDMA_RSOPR, priv->response);
  306. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  307. /* Start edma */
  308. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
  309. return 0;
  310. }
  311. static int mv_reset_channel(struct udevice *dev, int port)
  312. {
  313. struct mv_priv *priv = dev_get_platdata(dev);
  314. /* Make sure edma is stopped */
  315. mv_stop_edma_engine(dev, port);
  316. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
  317. udelay(25); /* allow reset propagation */
  318. out_le32(priv->regbase + EDMA_CMD, 0);
  319. mdelay(10);
  320. return 0;
  321. }
  322. static void mv_reset_port(struct udevice *dev, int port)
  323. {
  324. struct mv_priv *priv = dev_get_platdata(dev);
  325. mv_reset_channel(dev, port);
  326. out_le32(priv->regbase + EDMA_CMD, 0x0);
  327. out_le32(priv->regbase + EDMA_CFG, 0x101f);
  328. out_le32(priv->regbase + EDMA_IECR, 0x0);
  329. out_le32(priv->regbase + EDMA_IEMR, 0x0);
  330. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  331. out_le32(priv->regbase + EDMA_RQIPR, 0x0);
  332. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  333. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  334. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  335. out_le32(priv->regbase + EDMA_RSOPR, 0x0);
  336. out_le32(priv->regbase + EDMA_IORTO, 0xfa);
  337. }
  338. static void mv_reset_one_hc(void)
  339. {
  340. out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
  341. out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
  342. out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
  343. }
  344. static int probe_port(struct udevice *dev, int port)
  345. {
  346. struct mv_priv *priv = dev_get_platdata(dev);
  347. int tries, tries2, set15 = 0;
  348. u32 tmp;
  349. debug("Probe port: %d\n", port);
  350. for (tries = 0; tries < 2; tries++) {
  351. /* Clear SError */
  352. out_le32(priv->regbase + SIR_SERROR, 0x0);
  353. /* trigger com-init */
  354. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  355. tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
  356. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  357. mdelay(1);
  358. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  359. tries2 = 5;
  360. do {
  361. tmp = (tmp & 0x0f0) | 0x300;
  362. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  363. mdelay(10);
  364. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  365. } while ((tmp & 0xf0f) != 0x300 && tries2--);
  366. mdelay(10);
  367. for (tries2 = 0; tries2 < 200; tries2++) {
  368. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  369. if ((tmp & SSTATUS_DET_MASK) == 0x03) {
  370. debug("Found device on port\n");
  371. return 0;
  372. }
  373. mdelay(1);
  374. }
  375. if ((tmp & SSTATUS_DET_MASK) == 0) {
  376. debug("No device attached on port %d\n", port);
  377. return -ENODEV;
  378. }
  379. if (!set15) {
  380. /* Try on 1.5Gb/S */
  381. debug("Try 1.5Gb link\n");
  382. set15 = 1;
  383. out_le32(priv->regbase + SIR_SCONTROL, 0x304);
  384. tmp = in_le32(priv->regbase + SIR_ICFG);
  385. tmp &= ~SIR_CFG_GEN2EN;
  386. out_le32(priv->regbase + SIR_ICFG, tmp);
  387. mv_reset_channel(dev, port);
  388. }
  389. }
  390. debug("Failed to probe port\n");
  391. return -1;
  392. }
  393. /* Get request queue in pointer */
  394. static int get_reqip(struct udevice *dev, int port)
  395. {
  396. struct mv_priv *priv = dev_get_platdata(dev);
  397. u32 tmp;
  398. tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
  399. tmp = tmp >> EDMA_RQIPR_IPSHIFT;
  400. return tmp;
  401. }
  402. static void set_reqip(struct udevice *dev, int port, int reqin)
  403. {
  404. struct mv_priv *priv = dev_get_platdata(dev);
  405. u32 tmp;
  406. tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
  407. tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
  408. out_le32(priv->regbase + EDMA_RQIPR, tmp);
  409. }
  410. /* Get next available slot, ignoring possible overwrite */
  411. static int get_next_reqip(struct udevice *dev, int port)
  412. {
  413. int slot = get_reqip(dev, port);
  414. slot = (slot + 1) % REQUEST_QUEUE_SIZE;
  415. return slot;
  416. }
  417. /* Get response queue in pointer */
  418. static int get_rspip(struct udevice *dev, int port)
  419. {
  420. struct mv_priv *priv = dev_get_platdata(dev);
  421. u32 tmp;
  422. tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
  423. tmp = tmp >> EDMA_RSIPR_IPSHIFT;
  424. return tmp;
  425. }
  426. /* Get response queue out pointer */
  427. static int get_rspop(struct udevice *dev, int port)
  428. {
  429. struct mv_priv *priv = dev_get_platdata(dev);
  430. u32 tmp;
  431. tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
  432. tmp = tmp >> EDMA_RSOPR_OPSHIFT;
  433. return tmp;
  434. }
  435. /* Get next response queue pointer */
  436. static int get_next_rspop(struct udevice *dev, int port)
  437. {
  438. return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
  439. }
  440. /* Set response queue pointer */
  441. static void set_rspop(struct udevice *dev, int port, int reqin)
  442. {
  443. struct mv_priv *priv = dev_get_platdata(dev);
  444. u32 tmp;
  445. tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
  446. tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
  447. out_le32(priv->regbase + EDMA_RSOPR, tmp);
  448. }
  449. static int wait_dma_completion(struct udevice *dev, int port, int index,
  450. u32 timeout_msec)
  451. {
  452. u32 tmp, res;
  453. tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
  454. res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
  455. tmp, timeout_msec);
  456. if (res)
  457. printf("Failed to wait for completion on port %d\n", port);
  458. return res;
  459. }
  460. static void process_responses(struct udevice *dev, int port)
  461. {
  462. #ifdef DEBUG
  463. struct mv_priv *priv = dev_get_platdata(dev);
  464. #endif
  465. u32 tmp;
  466. u32 outind = get_rspop(dev, port);
  467. /* Ack interrupts */
  468. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  469. if (port == 0)
  470. tmp &= ~(BIT(0) | BIT(8));
  471. else
  472. tmp &= ~(BIT(1) | BIT(9));
  473. tmp &= ~(BIT(4));
  474. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  475. while (get_rspip(dev, port) != outind) {
  476. #ifdef DEBUG
  477. debug("Response index %d flags %08x on port %d\n", outind,
  478. priv->response[outind].flags, port);
  479. #endif
  480. outind = get_next_rspop(dev, port);
  481. set_rspop(dev, port, outind);
  482. }
  483. }
  484. static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
  485. struct sata_fis_h2d *cfis,
  486. u8 *buffer, u32 len, u32 iswrite)
  487. {
  488. struct mv_priv *priv = dev_get_platdata(dev);
  489. struct crqb *req;
  490. int slot;
  491. u32 start;
  492. if (len >= 64 * 1024) {
  493. printf("We only support <64K transfers for now\n");
  494. return -1;
  495. }
  496. /* Initialize request */
  497. slot = get_reqip(dev, port);
  498. memset(&priv->request[slot], 0, sizeof(struct crqb));
  499. req = &priv->request[slot];
  500. req->dtb_low = (u32)buffer;
  501. /* Dont use PRDs */
  502. req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
  503. req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
  504. req->control_flags |=
  505. ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
  506. & CRQB_CNTRLFLAGS_PMPORTMASK);
  507. req->drb_count = len;
  508. req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
  509. CRQB_CMDFEAT_CMDMASK;
  510. req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
  511. CRQB_CMDFEAT_FEATMASK;
  512. req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
  513. CRQB_ADDR_LBA_LOWMASK;
  514. req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
  515. CRQB_ADDR_LBA_MIDMASK;
  516. req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
  517. CRQB_ADDR_LBA_HIGHMASK;
  518. req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
  519. CRQB_ADDR_DEVICE_MASK;
  520. req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
  521. CRQB_ADDR_LBA_LOW_EXP_MASK;
  522. req->ata_addr_exp |=
  523. (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
  524. CRQB_ADDR_LBA_MID_EXP_MASK;
  525. req->ata_addr_exp |=
  526. (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
  527. CRQB_ADDR_LBA_HIGH_EXP_MASK;
  528. req->ata_addr_exp |=
  529. (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
  530. CRQB_ADDR_FEATURE_EXP_MASK;
  531. req->ata_sect_count =
  532. (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
  533. CRQB_SECTCOUNT_COUNT_MASK;
  534. req->ata_sect_count |=
  535. (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
  536. CRQB_SECTCOUNT_COUNT_EXP_MASK;
  537. /* Flush data */
  538. start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
  539. flush_dcache_range(start,
  540. start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
  541. /* Trigger operation */
  542. slot = get_next_reqip(dev, port);
  543. set_reqip(dev, port, slot);
  544. /* Wait for completion */
  545. if (wait_dma_completion(dev, port, slot, 10000)) {
  546. printf("ATA operation timed out\n");
  547. return -1;
  548. }
  549. process_responses(dev, port);
  550. /* Invalidate data on read */
  551. if (buffer && len) {
  552. start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
  553. invalidate_dcache_range(start,
  554. start + ALIGN(len, ARCH_DMA_MINALIGN));
  555. }
  556. return len;
  557. }
  558. static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
  559. u32 blkcnt,
  560. u8 *buffer, int is_write)
  561. {
  562. struct sata_fis_h2d cfis;
  563. u32 res;
  564. u64 block;
  565. block = (u64)start;
  566. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  567. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  568. cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  569. cfis.lba_high_exp = (block >> 40) & 0xff;
  570. cfis.lba_mid_exp = (block >> 32) & 0xff;
  571. cfis.lba_low_exp = (block >> 24) & 0xff;
  572. cfis.lba_high = (block >> 16) & 0xff;
  573. cfis.lba_mid = (block >> 8) & 0xff;
  574. cfis.lba_low = block & 0xff;
  575. cfis.device = ATA_LBA;
  576. cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
  577. cfis.sector_count = blkcnt & 0xff;
  578. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  579. ATA_SECT_SIZE * blkcnt, is_write);
  580. return res >= 0 ? blkcnt : res;
  581. }
  582. static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
  583. u32 blkcnt, u8 *buffer, int is_write)
  584. {
  585. struct sata_fis_h2d cfis;
  586. lbaint_t block;
  587. u32 res;
  588. block = start;
  589. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  590. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  591. cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  592. cfis.device = ATA_LBA;
  593. cfis.device |= (block >> 24) & 0xf;
  594. cfis.lba_high = (block >> 16) & 0xff;
  595. cfis.lba_mid = (block >> 8) & 0xff;
  596. cfis.lba_low = block & 0xff;
  597. cfis.sector_count = (u8)(blkcnt & 0xff);
  598. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  599. ATA_SECT_SIZE * blkcnt, is_write);
  600. return res >= 0 ? blkcnt : res;
  601. }
  602. static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
  603. lbaint_t blkcnt, void *buffer, int is_write)
  604. {
  605. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  606. lbaint_t start, blks;
  607. u8 *addr;
  608. int max_blks;
  609. debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
  610. start = blknr;
  611. blks = blkcnt;
  612. addr = (u8 *)buffer;
  613. max_blks = MV_ATA_MAX_SECTORS;
  614. do {
  615. if (blks > max_blks) {
  616. if (desc->lba48) {
  617. mv_sata_rw_cmd_ext(dev, port, start, max_blks,
  618. addr, is_write);
  619. } else {
  620. mv_sata_rw_cmd(dev, port, start, max_blks,
  621. addr, is_write);
  622. }
  623. start += max_blks;
  624. blks -= max_blks;
  625. addr += ATA_SECT_SIZE * max_blks;
  626. } else {
  627. if (desc->lba48) {
  628. mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
  629. is_write);
  630. } else {
  631. mv_sata_rw_cmd(dev, port, start, blks, addr,
  632. is_write);
  633. }
  634. start += blks;
  635. blks = 0;
  636. addr += ATA_SECT_SIZE * blks;
  637. }
  638. } while (blks != 0);
  639. return blkcnt;
  640. }
  641. static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
  642. struct sata_fis_h2d *cfis, u8 *buffer,
  643. u32 len, u32 iswrite)
  644. {
  645. struct mv_priv *priv = dev_get_platdata(dev);
  646. int i;
  647. u16 *tp;
  648. debug("%s\n", __func__);
  649. out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
  650. out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
  651. out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
  652. out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
  653. out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
  654. out_le32(priv->regbase + PIO_DEVICE, cfis->device);
  655. out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
  656. if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
  657. ATA_BUSY, 0x0, 10000)) {
  658. debug("Failed to wait for completion\n");
  659. return -1;
  660. }
  661. if (len > 0) {
  662. tp = (u16 *)buffer;
  663. for (i = 0; i < len / 2; i++) {
  664. if (iswrite)
  665. out_le16(priv->regbase + PIO_DATA, *tp++);
  666. else
  667. *tp++ = in_le16(priv->regbase + PIO_DATA);
  668. }
  669. }
  670. return len;
  671. }
  672. static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
  673. {
  674. struct sata_fis_h2d h2d;
  675. memset(&h2d, 0, sizeof(struct sata_fis_h2d));
  676. h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  677. h2d.command = ATA_CMD_ID_ATA;
  678. /* Give device time to get operational */
  679. mdelay(10);
  680. return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
  681. ATA_ID_WORDS * 2, READ_CMD);
  682. }
  683. static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
  684. {
  685. struct mv_priv *priv = dev_get_platdata(dev);
  686. priv->pio = id[ATA_ID_PIO_MODES];
  687. priv->mwdma = id[ATA_ID_MWDMA_MODES];
  688. priv->udma = id[ATA_ID_UDMA_MODES];
  689. debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
  690. priv->udma);
  691. }
  692. static void mv_sata_set_features(struct udevice *dev, int port)
  693. {
  694. struct mv_priv *priv = dev_get_platdata(dev);
  695. struct sata_fis_h2d cfis;
  696. u8 udma_cap;
  697. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  698. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  699. cfis.command = ATA_CMD_SET_FEATURES;
  700. cfis.features = SETFEATURES_XFER;
  701. /* First check the device capablity */
  702. udma_cap = (u8) (priv->udma & 0xff);
  703. if (udma_cap == ATA_UDMA6)
  704. cfis.sector_count = XFER_UDMA_6;
  705. if (udma_cap == ATA_UDMA5)
  706. cfis.sector_count = XFER_UDMA_5;
  707. if (udma_cap == ATA_UDMA4)
  708. cfis.sector_count = XFER_UDMA_4;
  709. if (udma_cap == ATA_UDMA3)
  710. cfis.sector_count = XFER_UDMA_3;
  711. mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
  712. }
  713. /*
  714. * Initialize SATA memory windows
  715. */
  716. static void mvsata_ide_conf_mbus_windows(void)
  717. {
  718. const struct mbus_dram_target_info *dram;
  719. int i;
  720. dram = mvebu_mbus_dram_info();
  721. /* Disable windows, Set Size/Base to 0 */
  722. for (i = 0; i < 4; i++) {
  723. writel(0, MVSATA_WIN_CONTROL(i));
  724. writel(0, MVSATA_WIN_BASE(i));
  725. }
  726. for (i = 0; i < dram->num_cs; i++) {
  727. const struct mbus_dram_window *cs = dram->cs + i;
  728. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  729. (dram->mbus_dram_target_id << 4) | 1,
  730. MVSATA_WIN_CONTROL(i));
  731. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  732. }
  733. }
  734. static int sata_mv_init_sata(struct udevice *dev, int port)
  735. {
  736. struct mv_priv *priv = dev_get_platdata(dev);
  737. debug("Initialize sata dev: %d\n", port);
  738. if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
  739. printf("Invalid sata device %d\n", port);
  740. return -1;
  741. }
  742. /* Allocate and align request buffer */
  743. priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
  744. CRQB_ALIGN);
  745. if (!priv->crqb_alloc) {
  746. printf("Unable to allocate memory for request queue\n");
  747. return -ENOMEM;
  748. }
  749. memset(priv->crqb_alloc, 0,
  750. sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
  751. priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
  752. ~(CRQB_ALIGN - 1));
  753. /* Allocate and align response buffer */
  754. priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
  755. CRPB_ALIGN);
  756. if (!priv->crpb_alloc) {
  757. printf("Unable to allocate memory for response queue\n");
  758. return -ENOMEM;
  759. }
  760. memset(priv->crpb_alloc, 0,
  761. sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
  762. priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
  763. ~(CRPB_ALIGN - 1));
  764. sprintf(priv->name, "SATA%d", port);
  765. priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
  766. if (!hw_init) {
  767. debug("Initialize sata hw\n");
  768. hw_init = 1;
  769. mv_reset_one_hc();
  770. mvsata_ide_conf_mbus_windows();
  771. }
  772. mv_reset_port(dev, port);
  773. if (probe_port(dev, port)) {
  774. priv->link = 0;
  775. return -ENODEV;
  776. }
  777. priv->link = 1;
  778. return 0;
  779. }
  780. static int sata_mv_scan_sata(struct udevice *dev, int port)
  781. {
  782. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  783. struct mv_priv *priv = dev_get_platdata(dev);
  784. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  785. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  786. unsigned char product[ATA_ID_PROD_LEN + 1];
  787. u64 n_sectors;
  788. u16 *id;
  789. if (!priv->link)
  790. return -ENODEV;
  791. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  792. if (!id) {
  793. printf("Failed to malloc id data\n");
  794. return -ENOMEM;
  795. }
  796. mv_sata_identify(dev, port, id);
  797. ata_swap_buf_le16(id, ATA_ID_WORDS);
  798. #ifdef DEBUG
  799. ata_dump_id(id);
  800. #endif
  801. /* Serial number */
  802. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  803. memcpy(desc->product, serial, sizeof(serial));
  804. /* Firmware version */
  805. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  806. memcpy(desc->revision, firmware, sizeof(firmware));
  807. /* Product model */
  808. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  809. memcpy(desc->vendor, product, sizeof(product));
  810. /* Total sectors */
  811. n_sectors = ata_id_n_sectors(id);
  812. desc->lba = n_sectors;
  813. /* Check if support LBA48 */
  814. if (ata_id_has_lba48(id)) {
  815. desc->lba48 = 1;
  816. debug("Device support LBA48\n");
  817. }
  818. /* Get the NCQ queue depth from device */
  819. priv->queue_depth = ata_id_queue_depth(id);
  820. /* Get the xfer mode from device */
  821. mv_sata_xfer_mode(dev, port, id);
  822. /* Set the xfer mode to highest speed */
  823. mv_sata_set_features(dev, port);
  824. /* Start up */
  825. mv_start_edma_engine(dev, port);
  826. return 0;
  827. }
  828. static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
  829. lbaint_t blkcnt, void *buffer)
  830. {
  831. struct mv_priv *priv = dev_get_platdata(blk);
  832. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  833. buffer, READ_CMD);
  834. }
  835. static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
  836. lbaint_t blkcnt, const void *buffer)
  837. {
  838. struct mv_priv *priv = dev_get_platdata(blk);
  839. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  840. (void *)buffer, WRITE_CMD);
  841. }
  842. static const struct blk_ops sata_mv_blk_ops = {
  843. .read = sata_mv_read,
  844. .write = sata_mv_write,
  845. };
  846. U_BOOT_DRIVER(sata_mv_driver) = {
  847. .name = "sata_mv_blk",
  848. .id = UCLASS_BLK,
  849. .ops = &sata_mv_blk_ops,
  850. .platdata_auto_alloc_size = sizeof(struct mv_priv),
  851. };
  852. static int sata_mv_probe(struct udevice *dev)
  853. {
  854. const void *blob = gd->fdt_blob;
  855. int node = dev_of_offset(dev);
  856. struct mv_priv *priv;
  857. struct udevice *blk;
  858. int nr_ports;
  859. int ret;
  860. int i;
  861. /* Get number of ports of this SATA controller */
  862. nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
  863. CONFIG_SYS_SATA_MAX_DEVICE);
  864. for (i = 0; i < nr_ports; i++) {
  865. ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
  866. IF_TYPE_SATA, -1, 512, 0, &blk);
  867. if (ret) {
  868. debug("Can't create device\n");
  869. return ret;
  870. }
  871. priv = dev_get_platdata(blk);
  872. priv->dev_nr = i;
  873. /* Init SATA port */
  874. ret = sata_mv_init_sata(blk, i);
  875. if (ret) {
  876. debug("%s: Failed to init bus\n", __func__);
  877. return ret;
  878. }
  879. /* Scan SATA port */
  880. ret = sata_mv_scan_sata(blk, i);
  881. if (ret) {
  882. debug("%s: Failed to scan bus\n", __func__);
  883. return ret;
  884. }
  885. }
  886. return 0;
  887. }
  888. static int sata_mv_scan(struct udevice *dev)
  889. {
  890. /* Nothing to do here */
  891. return 0;
  892. }
  893. static const struct udevice_id sata_mv_ids[] = {
  894. { .compatible = "marvell,armada-370-sata" },
  895. { .compatible = "marvell,orion-sata" },
  896. { }
  897. };
  898. struct ahci_ops sata_mv_ahci_ops = {
  899. .scan = sata_mv_scan,
  900. };
  901. U_BOOT_DRIVER(sata_mv_ahci) = {
  902. .name = "sata_mv_ahci",
  903. .id = UCLASS_AHCI,
  904. .of_match = sata_mv_ids,
  905. .ops = &sata_mv_ahci_ops,
  906. .probe = sata_mv_probe,
  907. };