mvsata_ide.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #if defined(CONFIG_ARCH_ORION5X)
  10. #include <asm/arch/orion5x.h>
  11. #elif defined(CONFIG_ARCH_KIRKWOOD)
  12. #include <asm/arch/soc.h>
  13. #elif defined(CONFIG_ARCH_MVEBU)
  14. #include <linux/mbus.h>
  15. #endif
  16. /* SATA port registers */
  17. struct mvsata_port_registers {
  18. u32 reserved0[10];
  19. u32 edma_cmd;
  20. u32 reserved1[181];
  21. /* offset 0x300 : ATA Interface registers */
  22. u32 sstatus;
  23. u32 serror;
  24. u32 scontrol;
  25. u32 ltmode;
  26. u32 phymode3;
  27. u32 phymode4;
  28. u32 reserved2[5];
  29. u32 phymode1;
  30. u32 phymode2;
  31. u32 bist_cr;
  32. u32 bist_dw1;
  33. u32 bist_dw2;
  34. u32 serrorintrmask;
  35. };
  36. /*
  37. * Sanity checks:
  38. * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
  39. * - for ide_preinit to make sense, we need at least one of
  40. * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
  41. * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
  42. * Fail with an explanation message if these conditions are not met.
  43. * This is particularly important for CONFIG_IDE_PREINIT, because
  44. * its lack would not cause a build error.
  45. */
  46. #if !defined(CONFIG_SYS_ATA_BASE_ADDR)
  47. #error CONFIG_SYS_ATA_BASE_ADDR must be defined
  48. #elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
  49. && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
  50. #error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
  51. must be defined
  52. #elif !defined(CONFIG_IDE_PREINIT)
  53. #error CONFIG_IDE_PREINIT must be defined
  54. #endif
  55. /*
  56. * Masks and values for SControl DETection and Interface Power Management,
  57. * and for SStatus DETection.
  58. */
  59. #define MVSATA_EDMA_CMD_ATA_RST 0x00000004
  60. #define MVSATA_SCONTROL_DET_MASK 0x0000000F
  61. #define MVSATA_SCONTROL_DET_NONE 0x00000000
  62. #define MVSATA_SCONTROL_DET_INIT 0x00000001
  63. #define MVSATA_SCONTROL_IPM_MASK 0x00000F00
  64. #define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
  65. #define MVSATA_SCONTROL_MASK \
  66. (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
  67. #define MVSATA_PORT_INIT \
  68. (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  69. #define MVSATA_PORT_USE \
  70. (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  71. #define MVSATA_SSTATUS_DET_MASK 0x0000000F
  72. #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
  73. /*
  74. * Status codes to return to client callers. Currently, callers ignore
  75. * exact value and only care for zero or nonzero, so no need to make this
  76. * public, it is only #define'd for clarity.
  77. * If/when standard negative codes are implemented in U-Boot, then these
  78. * #defines should be moved to, or replaced by ones from, the common list
  79. * of status codes.
  80. */
  81. #define MVSATA_STATUS_OK 0
  82. #define MVSATA_STATUS_TIMEOUT -1
  83. /*
  84. * Registers for SATA MBUS memory windows
  85. */
  86. #define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
  87. #define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
  88. /*
  89. * Initialize SATA memory windows for Armada XP
  90. */
  91. #ifdef CONFIG_ARCH_MVEBU
  92. static void mvsata_ide_conf_mbus_windows(void)
  93. {
  94. const struct mbus_dram_target_info *dram;
  95. int i;
  96. dram = mvebu_mbus_dram_info();
  97. /* Disable windows, Set Size/Base to 0 */
  98. for (i = 0; i < 4; i++) {
  99. writel(0, MVSATA_WIN_CONTROL(i));
  100. writel(0, MVSATA_WIN_BASE(i));
  101. }
  102. for (i = 0; i < dram->num_cs; i++) {
  103. const struct mbus_dram_window *cs = dram->cs + i;
  104. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  105. (dram->mbus_dram_target_id << 4) | 1,
  106. MVSATA_WIN_CONTROL(i));
  107. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  108. }
  109. }
  110. #endif
  111. /*
  112. * Initialize one MVSATAHC port: set SControl's IPM to "always active"
  113. * and DET to "reset", then wait for SStatus's DET to become "device and
  114. * comm ok" (or time out after 50 us if no device), then set SControl's
  115. * DET back to "no action".
  116. */
  117. static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
  118. {
  119. u32 control;
  120. u32 status;
  121. u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
  122. /* Hard reset */
  123. writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
  124. udelay(25); /* taken from original marvell port */
  125. writel(0, &port->edma_cmd);
  126. /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
  127. control = readl(&port->scontrol);
  128. control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
  129. writel(control, &port->scontrol);
  130. /* Toggle control DET back to 0 (normal operation) */
  131. control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
  132. writel(control, &port->scontrol);
  133. /* wait for status DET to become 3 (device and communication OK) */
  134. while (--timeleft) {
  135. status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
  136. if (status == MVSATA_SSTATUS_DET_DEVCOMM)
  137. break;
  138. udelay(1);
  139. }
  140. /* return success or time-out error depending on time left */
  141. if (!timeleft)
  142. return MVSATA_STATUS_TIMEOUT;
  143. return MVSATA_STATUS_OK;
  144. }
  145. /*
  146. * ide_preinit() will be called by ide_init in cmd_ide.c and will
  147. * reset the MVSTATHC ports needed by the board.
  148. */
  149. int ide_preinit(void)
  150. {
  151. int ret = MVSATA_STATUS_TIMEOUT;
  152. int status;
  153. #ifdef CONFIG_ARCH_MVEBU
  154. mvsata_ide_conf_mbus_windows();
  155. #endif
  156. /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
  157. #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
  158. status = mvsata_ide_initialize_port(
  159. (struct mvsata_port_registers *)
  160. (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
  161. if (status == MVSATA_STATUS_OK)
  162. ret = MVSATA_STATUS_OK;
  163. #endif
  164. /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
  165. #if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
  166. status = mvsata_ide_initialize_port(
  167. (struct mvsata_port_registers *)
  168. (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
  169. if (status == MVSATA_STATUS_OK)
  170. ret = MVSATA_STATUS_OK;
  171. #endif
  172. /* Return success if at least one port initialization succeeded */
  173. return ret;
  174. }