mbus.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
  4. * 370/XP, Dove, Orion5x and MV78xx0)
  5. *
  6. * Ported from the Barebox version to U-Boot by:
  7. * Stefan Roese <sr@denx.de>
  8. *
  9. * The Barebox version is:
  10. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  11. *
  12. * based on mbus driver from Linux
  13. * (C) Copyright 2008 Marvell Semiconductor
  14. *
  15. * The Marvell EBU SoCs have a configurable physical address space:
  16. * the physical address at which certain devices (PCIe, NOR, NAND,
  17. * etc.) sit can be configured. The configuration takes place through
  18. * two sets of registers:
  19. *
  20. * - One to configure the access of the CPU to the devices. Depending
  21. * on the families, there are between 8 and 20 configurable windows,
  22. * each can be use to create a physical memory window that maps to a
  23. * specific device. Devices are identified by a tuple (target,
  24. * attribute).
  25. *
  26. * - One to configure the access to the CPU to the SDRAM. There are
  27. * either 2 (for Dove) or 4 (for other families) windows to map the
  28. * SDRAM into the physical address space.
  29. *
  30. * This driver:
  31. *
  32. * - Reads out the SDRAM address decoding windows at initialization
  33. * time, and fills the mbus_dram_info structure with these
  34. * informations. The exported function mv_mbus_dram_info() allow
  35. * device drivers to get those informations related to the SDRAM
  36. * address decoding windows. This is because devices also have their
  37. * own windows (configured through registers that are part of each
  38. * device register space), and therefore the drivers for Marvell
  39. * devices have to configure those device -> SDRAM windows to ensure
  40. * that DMA works properly.
  41. *
  42. * - Provides an API for platform code or device drivers to
  43. * dynamically add or remove address decoding windows for the CPU ->
  44. * device accesses. This API is mvebu_mbus_add_window_by_id(),
  45. * mvebu_mbus_add_window_remap_by_id() and
  46. * mvebu_mbus_del_window().
  47. */
  48. #include <common.h>
  49. #include <malloc.h>
  50. #include <linux/errno.h>
  51. #include <asm/io.h>
  52. #include <asm/arch/cpu.h>
  53. #include <asm/arch/soc.h>
  54. #include <linux/log2.h>
  55. #include <linux/mbus.h>
  56. /* DDR target is the same on all platforms */
  57. #define TARGET_DDR 0
  58. /* CPU Address Decode Windows registers */
  59. #define WIN_CTRL_OFF 0x0000
  60. #define WIN_CTRL_ENABLE BIT(0)
  61. #define WIN_CTRL_TGT_MASK 0xf0
  62. #define WIN_CTRL_TGT_SHIFT 4
  63. #define WIN_CTRL_ATTR_MASK 0xff00
  64. #define WIN_CTRL_ATTR_SHIFT 8
  65. #define WIN_CTRL_SIZE_MASK 0xffff0000
  66. #define WIN_CTRL_SIZE_SHIFT 16
  67. #define WIN_BASE_OFF 0x0004
  68. #define WIN_BASE_LOW 0xffff0000
  69. #define WIN_BASE_HIGH 0xf
  70. #define WIN_REMAP_LO_OFF 0x0008
  71. #define WIN_REMAP_LOW 0xffff0000
  72. #define WIN_REMAP_HI_OFF 0x000c
  73. #define ATTR_HW_COHERENCY (0x1 << 4)
  74. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  75. #define DDR_BASE_CS_HIGH_MASK 0xf
  76. #define DDR_BASE_CS_LOW_MASK 0xff000000
  77. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  78. #define DDR_SIZE_ENABLED BIT(0)
  79. #define DDR_SIZE_CS_MASK 0x1c
  80. #define DDR_SIZE_CS_SHIFT 2
  81. #define DDR_SIZE_MASK 0xff000000
  82. #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
  83. struct mvebu_mbus_state;
  84. struct mvebu_mbus_soc_data {
  85. unsigned int num_wins;
  86. unsigned int num_remappable_wins;
  87. unsigned int (*win_cfg_offset)(const int win);
  88. void (*setup_cpu_target)(struct mvebu_mbus_state *s);
  89. };
  90. struct mvebu_mbus_state mbus_state
  91. __attribute__ ((section(".data")));
  92. static struct mbus_dram_target_info mbus_dram_info
  93. __attribute__ ((section(".data")));
  94. /*
  95. * Functions to manipulate the address decoding windows
  96. */
  97. static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
  98. int win, int *enabled, u64 *base,
  99. u32 *size, u8 *target, u8 *attr,
  100. u64 *remap)
  101. {
  102. void __iomem *addr = mbus->mbuswins_base +
  103. mbus->soc->win_cfg_offset(win);
  104. u32 basereg = readl(addr + WIN_BASE_OFF);
  105. u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
  106. if (!(ctrlreg & WIN_CTRL_ENABLE)) {
  107. *enabled = 0;
  108. return;
  109. }
  110. *enabled = 1;
  111. *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
  112. *base |= (basereg & WIN_BASE_LOW);
  113. *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
  114. if (target)
  115. *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
  116. if (attr)
  117. *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
  118. if (remap) {
  119. if (win < mbus->soc->num_remappable_wins) {
  120. u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
  121. u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
  122. *remap = ((u64)remap_hi << 32) | remap_low;
  123. } else {
  124. *remap = 0;
  125. }
  126. }
  127. }
  128. static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
  129. int win)
  130. {
  131. void __iomem *addr;
  132. addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
  133. writel(0, addr + WIN_BASE_OFF);
  134. writel(0, addr + WIN_CTRL_OFF);
  135. if (win < mbus->soc->num_remappable_wins) {
  136. writel(0, addr + WIN_REMAP_LO_OFF);
  137. writel(0, addr + WIN_REMAP_HI_OFF);
  138. }
  139. }
  140. /* Checks whether the given window number is available */
  141. static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
  142. const int win)
  143. {
  144. void __iomem *addr = mbus->mbuswins_base +
  145. mbus->soc->win_cfg_offset(win);
  146. u32 ctrl = readl(addr + WIN_CTRL_OFF);
  147. return !(ctrl & WIN_CTRL_ENABLE);
  148. }
  149. /*
  150. * Checks whether the given (base, base+size) area doesn't overlap an
  151. * existing region
  152. */
  153. static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
  154. phys_addr_t base, size_t size,
  155. u8 target, u8 attr)
  156. {
  157. u64 end = (u64)base + size;
  158. int win;
  159. for (win = 0; win < mbus->soc->num_wins; win++) {
  160. u64 wbase, wend;
  161. u32 wsize;
  162. u8 wtarget, wattr;
  163. int enabled;
  164. mvebu_mbus_read_window(mbus, win,
  165. &enabled, &wbase, &wsize,
  166. &wtarget, &wattr, NULL);
  167. if (!enabled)
  168. continue;
  169. wend = wbase + wsize;
  170. /*
  171. * Check if the current window overlaps with the
  172. * proposed physical range
  173. */
  174. if ((u64)base < wend && end > wbase)
  175. return 0;
  176. /*
  177. * Check if target/attribute conflicts
  178. */
  179. if (target == wtarget && attr == wattr)
  180. return 0;
  181. }
  182. return 1;
  183. }
  184. static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
  185. phys_addr_t base, size_t size)
  186. {
  187. int win;
  188. for (win = 0; win < mbus->soc->num_wins; win++) {
  189. u64 wbase;
  190. u32 wsize;
  191. int enabled;
  192. mvebu_mbus_read_window(mbus, win,
  193. &enabled, &wbase, &wsize,
  194. NULL, NULL, NULL);
  195. if (!enabled)
  196. continue;
  197. if (base == wbase && size == wsize)
  198. return win;
  199. }
  200. return -ENODEV;
  201. }
  202. static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
  203. int win, phys_addr_t base, size_t size,
  204. phys_addr_t remap, u8 target,
  205. u8 attr)
  206. {
  207. void __iomem *addr = mbus->mbuswins_base +
  208. mbus->soc->win_cfg_offset(win);
  209. u32 ctrl, remap_addr;
  210. ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
  211. (attr << WIN_CTRL_ATTR_SHIFT) |
  212. (target << WIN_CTRL_TGT_SHIFT) |
  213. WIN_CTRL_ENABLE;
  214. writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
  215. writel(ctrl, addr + WIN_CTRL_OFF);
  216. if (win < mbus->soc->num_remappable_wins) {
  217. if (remap == MVEBU_MBUS_NO_REMAP)
  218. remap_addr = base;
  219. else
  220. remap_addr = remap;
  221. writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
  222. writel(0, addr + WIN_REMAP_HI_OFF);
  223. }
  224. return 0;
  225. }
  226. static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
  227. phys_addr_t base, size_t size,
  228. phys_addr_t remap, u8 target,
  229. u8 attr)
  230. {
  231. int win;
  232. if (remap == MVEBU_MBUS_NO_REMAP) {
  233. for (win = mbus->soc->num_remappable_wins;
  234. win < mbus->soc->num_wins; win++)
  235. if (mvebu_mbus_window_is_free(mbus, win))
  236. return mvebu_mbus_setup_window(mbus, win, base,
  237. size, remap,
  238. target, attr);
  239. }
  240. for (win = 0; win < mbus->soc->num_wins; win++)
  241. if (mvebu_mbus_window_is_free(mbus, win))
  242. return mvebu_mbus_setup_window(mbus, win, base, size,
  243. remap, target, attr);
  244. return -ENOMEM;
  245. }
  246. /*
  247. * SoC-specific functions and definitions
  248. */
  249. static unsigned int armada_370_xp_mbus_win_offset(int win)
  250. {
  251. /* The register layout is a bit annoying and the below code
  252. * tries to cope with it.
  253. * - At offset 0x0, there are the registers for the first 8
  254. * windows, with 4 registers of 32 bits per window (ctrl,
  255. * base, remap low, remap high)
  256. * - Then at offset 0x80, there is a hole of 0x10 bytes for
  257. * the internal registers base address and internal units
  258. * sync barrier register.
  259. * - Then at offset 0x90, there the registers for 12
  260. * windows, with only 2 registers of 32 bits per window
  261. * (ctrl, base).
  262. */
  263. if (win < 8)
  264. return win << 4;
  265. else
  266. return 0x90 + ((win - 8) << 3);
  267. }
  268. static unsigned int orion5x_mbus_win_offset(int win)
  269. {
  270. return win << 4;
  271. }
  272. static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
  273. {
  274. int i;
  275. int cs;
  276. mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
  277. for (i = 0, cs = 0; i < 4; i++) {
  278. u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
  279. u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
  280. /*
  281. * We only take care of entries for which the chip
  282. * select is enabled, and that don't have high base
  283. * address bits set (devices can only access the first
  284. * 32 bits of the memory).
  285. */
  286. if ((size & DDR_SIZE_ENABLED) &&
  287. !(base & DDR_BASE_CS_HIGH_MASK)) {
  288. struct mbus_dram_window *w;
  289. w = &mbus_dram_info.cs[cs++];
  290. w->cs_index = i;
  291. w->mbus_attr = 0xf & ~(1 << i);
  292. w->base = base & DDR_BASE_CS_LOW_MASK;
  293. w->size = (size | ~DDR_SIZE_MASK) + 1;
  294. }
  295. }
  296. mbus_dram_info.num_cs = cs;
  297. #if defined(CONFIG_ARMADA_MSYS)
  298. /* Disable MBUS Err Prop - in order to avoid data aborts */
  299. clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
  300. #endif
  301. }
  302. static const struct mvebu_mbus_soc_data
  303. armada_370_xp_mbus_data __maybe_unused = {
  304. .num_wins = 20,
  305. .num_remappable_wins = 8,
  306. .win_cfg_offset = armada_370_xp_mbus_win_offset,
  307. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  308. };
  309. static const struct mvebu_mbus_soc_data
  310. kirkwood_mbus_data __maybe_unused = {
  311. .num_wins = 8,
  312. .num_remappable_wins = 4,
  313. .win_cfg_offset = orion5x_mbus_win_offset,
  314. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  315. };
  316. /*
  317. * Public API of the driver
  318. */
  319. const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
  320. {
  321. return &mbus_dram_info;
  322. }
  323. int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  324. unsigned int attribute,
  325. phys_addr_t base, size_t size,
  326. phys_addr_t remap)
  327. {
  328. struct mvebu_mbus_state *s = &mbus_state;
  329. if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
  330. printf("Cannot add window '%x:%x', conflicts with another window\n",
  331. target, attribute);
  332. return -EINVAL;
  333. }
  334. return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
  335. }
  336. int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
  337. phys_addr_t base, size_t size)
  338. {
  339. return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
  340. size, MVEBU_MBUS_NO_REMAP);
  341. }
  342. int mvebu_mbus_del_window(phys_addr_t base, size_t size)
  343. {
  344. int win;
  345. win = mvebu_mbus_find_window(&mbus_state, base, size);
  346. if (win < 0)
  347. return win;
  348. mvebu_mbus_disable_window(&mbus_state, win);
  349. return 0;
  350. }
  351. #ifndef CONFIG_ARCH_KIRKWOOD
  352. static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
  353. phys_addr_t *base)
  354. {
  355. int win;
  356. *base = 0xffffffff;
  357. for (win = 0; win < mbus->soc->num_wins; win++) {
  358. u64 wbase;
  359. u32 wsize;
  360. u8 wtarget, wattr;
  361. int enabled;
  362. mvebu_mbus_read_window(mbus, win,
  363. &enabled, &wbase, &wsize,
  364. &wtarget, &wattr, NULL);
  365. if (!enabled)
  366. continue;
  367. if (wbase < *base)
  368. *base = wbase;
  369. }
  370. }
  371. static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
  372. {
  373. phys_addr_t base;
  374. u32 val;
  375. u32 size;
  376. /* Set MBUS bridge base/ctrl */
  377. mvebu_mbus_get_lowest_base(&mbus_state, &base);
  378. size = 0xffffffff - base + 1;
  379. if (!is_power_of_2(size)) {
  380. /* Round up to next power of 2 */
  381. size = 1 << (ffs(base) + 1);
  382. base = 0xffffffff - size + 1;
  383. }
  384. /* Now write base and size */
  385. writel(base, MBUS_BRIDGE_WIN_BASE_REG);
  386. /* Align window size to 64KiB */
  387. val = (size / (64 << 10)) - 1;
  388. writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
  389. }
  390. #endif
  391. int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
  392. u32 base, u32 size, u8 target, u8 attr)
  393. {
  394. if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
  395. printf("Cannot add window '%04x:%04x', conflicts with another window\n",
  396. target, attr);
  397. return -EBUSY;
  398. }
  399. /*
  400. * In U-Boot we first try to add the mbus window to the remap windows.
  401. * If this fails, lets try to add the windows to the non-remap windows.
  402. */
  403. if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
  404. if (mvebu_mbus_alloc_window(mbus, base, size,
  405. MVEBU_MBUS_NO_REMAP, target, attr))
  406. return -ENOMEM;
  407. }
  408. #ifndef CONFIG_ARCH_KIRKWOOD
  409. /*
  410. * Re-configure the mbus bridge registers each time this function
  411. * is called. Since it may get called from the board code in
  412. * later boot stages as well.
  413. */
  414. mvebu_config_mbus_bridge(mbus);
  415. #endif
  416. return 0;
  417. }
  418. int mvebu_mbus_probe(struct mbus_win windows[], int count)
  419. {
  420. int win;
  421. int ret;
  422. int i;
  423. #if defined(CONFIG_ARCH_KIRKWOOD)
  424. mbus_state.soc = &kirkwood_mbus_data;
  425. #endif
  426. #if defined(CONFIG_ARCH_MVEBU)
  427. mbus_state.soc = &armada_370_xp_mbus_data;
  428. #endif
  429. mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
  430. mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
  431. for (win = 0; win < mbus_state.soc->num_wins; win++)
  432. mvebu_mbus_disable_window(&mbus_state, win);
  433. mbus_state.soc->setup_cpu_target(&mbus_state);
  434. /* Setup statically declared windows in the DT */
  435. for (i = 0; i < count; i++) {
  436. u32 base, size;
  437. u8 target, attr;
  438. target = windows[i].target;
  439. attr = windows[i].attr;
  440. base = windows[i].base;
  441. size = windows[i].size;
  442. ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
  443. if (ret < 0)
  444. return ret;
  445. }
  446. return 0;
  447. }