pci-uclass.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #define LOG_CATEGORY UCLASS_PCI
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <pci.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/lists.h>
  18. #include <dm/uclass-internal.h>
  19. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  20. #include <asm/fsp/fsp_support.h>
  21. #endif
  22. #include <linux/delay.h>
  23. #include "pci_internal.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int pci_get_bus(int busnum, struct udevice **busp)
  26. {
  27. int ret;
  28. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  29. /* Since buses may not be numbered yet try a little harder with bus 0 */
  30. if (ret == -ENODEV) {
  31. ret = uclass_first_device_err(UCLASS_PCI, busp);
  32. if (ret)
  33. return ret;
  34. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  35. }
  36. return ret;
  37. }
  38. struct udevice *pci_get_controller(struct udevice *dev)
  39. {
  40. while (device_is_on_pci_bus(dev))
  41. dev = dev->parent;
  42. return dev;
  43. }
  44. pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
  45. {
  46. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  47. struct udevice *bus = dev->parent;
  48. /*
  49. * This error indicates that @dev is a device on an unprobed PCI bus.
  50. * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
  51. * will produce a bad BDF>
  52. *
  53. * A common cause of this problem is that this function is called in the
  54. * of_to_plat() method of @dev. Accessing the PCI bus in that
  55. * method is not allowed, since it has not yet been probed. To fix this,
  56. * move that access to the probe() method of @dev instead.
  57. */
  58. if (!device_active(bus))
  59. log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
  60. bus->name);
  61. return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
  62. }
  63. /**
  64. * pci_get_bus_max() - returns the bus number of the last active bus
  65. *
  66. * @return last bus number, or -1 if no active buses
  67. */
  68. static int pci_get_bus_max(void)
  69. {
  70. struct udevice *bus;
  71. struct uclass *uc;
  72. int ret = -1;
  73. ret = uclass_get(UCLASS_PCI, &uc);
  74. uclass_foreach_dev(bus, uc) {
  75. if (dev_seq(bus) > ret)
  76. ret = dev_seq(bus);
  77. }
  78. debug("%s: ret=%d\n", __func__, ret);
  79. return ret;
  80. }
  81. int pci_last_busno(void)
  82. {
  83. return pci_get_bus_max();
  84. }
  85. int pci_get_ff(enum pci_size_t size)
  86. {
  87. switch (size) {
  88. case PCI_SIZE_8:
  89. return 0xff;
  90. case PCI_SIZE_16:
  91. return 0xffff;
  92. default:
  93. return 0xffffffff;
  94. }
  95. }
  96. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  97. ofnode *rnode)
  98. {
  99. struct fdt_pci_addr addr;
  100. ofnode node;
  101. int ret;
  102. dev_for_each_subnode(node, bus) {
  103. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  104. &addr);
  105. if (ret)
  106. continue;
  107. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  108. continue;
  109. *rnode = node;
  110. break;
  111. }
  112. };
  113. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  114. struct udevice **devp)
  115. {
  116. struct udevice *dev;
  117. for (device_find_first_child(bus, &dev);
  118. dev;
  119. device_find_next_child(&dev)) {
  120. struct pci_child_plat *pplat;
  121. pplat = dev_get_parent_plat(dev);
  122. if (pplat && pplat->devfn == find_devfn) {
  123. *devp = dev;
  124. return 0;
  125. }
  126. }
  127. return -ENODEV;
  128. }
  129. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  130. {
  131. struct udevice *bus;
  132. int ret;
  133. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  134. if (ret)
  135. return ret;
  136. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  137. }
  138. static int pci_device_matches_ids(struct udevice *dev,
  139. struct pci_device_id *ids)
  140. {
  141. struct pci_child_plat *pplat;
  142. int i;
  143. pplat = dev_get_parent_plat(dev);
  144. if (!pplat)
  145. return -EINVAL;
  146. for (i = 0; ids[i].vendor != 0; i++) {
  147. if (pplat->vendor == ids[i].vendor &&
  148. pplat->device == ids[i].device)
  149. return i;
  150. }
  151. return -EINVAL;
  152. }
  153. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  154. int *indexp, struct udevice **devp)
  155. {
  156. struct udevice *dev;
  157. /* Scan all devices on this bus */
  158. for (device_find_first_child(bus, &dev);
  159. dev;
  160. device_find_next_child(&dev)) {
  161. if (pci_device_matches_ids(dev, ids) >= 0) {
  162. if ((*indexp)-- <= 0) {
  163. *devp = dev;
  164. return 0;
  165. }
  166. }
  167. }
  168. return -ENODEV;
  169. }
  170. int pci_find_device_id(struct pci_device_id *ids, int index,
  171. struct udevice **devp)
  172. {
  173. struct udevice *bus;
  174. /* Scan all known buses */
  175. for (uclass_first_device(UCLASS_PCI, &bus);
  176. bus;
  177. uclass_next_device(&bus)) {
  178. if (!pci_bus_find_devices(bus, ids, &index, devp))
  179. return 0;
  180. }
  181. *devp = NULL;
  182. return -ENODEV;
  183. }
  184. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  185. unsigned int device, int *indexp,
  186. struct udevice **devp)
  187. {
  188. struct pci_child_plat *pplat;
  189. struct udevice *dev;
  190. for (device_find_first_child(bus, &dev);
  191. dev;
  192. device_find_next_child(&dev)) {
  193. pplat = dev_get_parent_plat(dev);
  194. if (pplat->vendor == vendor && pplat->device == device) {
  195. if (!(*indexp)--) {
  196. *devp = dev;
  197. return 0;
  198. }
  199. }
  200. }
  201. return -ENODEV;
  202. }
  203. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  204. struct udevice **devp)
  205. {
  206. struct udevice *bus;
  207. /* Scan all known buses */
  208. for (uclass_first_device(UCLASS_PCI, &bus);
  209. bus;
  210. uclass_next_device(&bus)) {
  211. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  212. return device_probe(*devp);
  213. }
  214. *devp = NULL;
  215. return -ENODEV;
  216. }
  217. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  218. {
  219. struct udevice *dev;
  220. /* Scan all known buses */
  221. for (pci_find_first_device(&dev);
  222. dev;
  223. pci_find_next_device(&dev)) {
  224. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  225. if (pplat->class == find_class && !index--) {
  226. *devp = dev;
  227. return device_probe(*devp);
  228. }
  229. }
  230. *devp = NULL;
  231. return -ENODEV;
  232. }
  233. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  234. unsigned long value, enum pci_size_t size)
  235. {
  236. struct dm_pci_ops *ops;
  237. ops = pci_get_ops(bus);
  238. if (!ops->write_config)
  239. return -ENOSYS;
  240. return ops->write_config(bus, bdf, offset, value, size);
  241. }
  242. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  243. u32 clr, u32 set)
  244. {
  245. ulong val;
  246. int ret;
  247. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  248. if (ret)
  249. return ret;
  250. val &= ~clr;
  251. val |= set;
  252. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  253. }
  254. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  255. enum pci_size_t size)
  256. {
  257. struct udevice *bus;
  258. int ret;
  259. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  260. if (ret)
  261. return ret;
  262. return pci_bus_write_config(bus, bdf, offset, value, size);
  263. }
  264. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  265. enum pci_size_t size)
  266. {
  267. struct udevice *bus;
  268. for (bus = dev; device_is_on_pci_bus(bus);)
  269. bus = bus->parent;
  270. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  271. size);
  272. }
  273. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  274. {
  275. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  276. }
  277. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  278. {
  279. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  280. }
  281. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  282. {
  283. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  284. }
  285. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  286. {
  287. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  288. }
  289. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  290. {
  291. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  292. }
  293. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  294. {
  295. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  296. }
  297. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  298. unsigned long *valuep, enum pci_size_t size)
  299. {
  300. struct dm_pci_ops *ops;
  301. ops = pci_get_ops(bus);
  302. if (!ops->read_config)
  303. return -ENOSYS;
  304. return ops->read_config(bus, bdf, offset, valuep, size);
  305. }
  306. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  307. enum pci_size_t size)
  308. {
  309. struct udevice *bus;
  310. int ret;
  311. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  312. if (ret)
  313. return ret;
  314. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  315. }
  316. int dm_pci_read_config(const struct udevice *dev, int offset,
  317. unsigned long *valuep, enum pci_size_t size)
  318. {
  319. const struct udevice *bus;
  320. for (bus = dev; device_is_on_pci_bus(bus);)
  321. bus = bus->parent;
  322. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  323. size);
  324. }
  325. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  326. {
  327. unsigned long value;
  328. int ret;
  329. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  330. if (ret)
  331. return ret;
  332. *valuep = value;
  333. return 0;
  334. }
  335. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  336. {
  337. unsigned long value;
  338. int ret;
  339. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  340. if (ret)
  341. return ret;
  342. *valuep = value;
  343. return 0;
  344. }
  345. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  346. {
  347. unsigned long value;
  348. int ret;
  349. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  350. if (ret)
  351. return ret;
  352. *valuep = value;
  353. return 0;
  354. }
  355. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
  356. {
  357. unsigned long value;
  358. int ret;
  359. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  360. if (ret)
  361. return ret;
  362. *valuep = value;
  363. return 0;
  364. }
  365. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
  366. {
  367. unsigned long value;
  368. int ret;
  369. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  370. if (ret)
  371. return ret;
  372. *valuep = value;
  373. return 0;
  374. }
  375. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
  376. {
  377. unsigned long value;
  378. int ret;
  379. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  380. if (ret)
  381. return ret;
  382. *valuep = value;
  383. return 0;
  384. }
  385. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  386. {
  387. u8 val;
  388. int ret;
  389. ret = dm_pci_read_config8(dev, offset, &val);
  390. if (ret)
  391. return ret;
  392. val &= ~clr;
  393. val |= set;
  394. return dm_pci_write_config8(dev, offset, val);
  395. }
  396. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  397. {
  398. u16 val;
  399. int ret;
  400. ret = dm_pci_read_config16(dev, offset, &val);
  401. if (ret)
  402. return ret;
  403. val &= ~clr;
  404. val |= set;
  405. return dm_pci_write_config16(dev, offset, val);
  406. }
  407. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  408. {
  409. u32 val;
  410. int ret;
  411. ret = dm_pci_read_config32(dev, offset, &val);
  412. if (ret)
  413. return ret;
  414. val &= ~clr;
  415. val |= set;
  416. return dm_pci_write_config32(dev, offset, val);
  417. }
  418. static void set_vga_bridge_bits(struct udevice *dev)
  419. {
  420. struct udevice *parent = dev->parent;
  421. u16 bc;
  422. while (dev_seq(parent) != 0) {
  423. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  424. bc |= PCI_BRIDGE_CTL_VGA;
  425. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  426. parent = parent->parent;
  427. }
  428. }
  429. int pci_auto_config_devices(struct udevice *bus)
  430. {
  431. struct pci_controller *hose = dev_get_uclass_priv(bus);
  432. struct pci_child_plat *pplat;
  433. unsigned int sub_bus;
  434. struct udevice *dev;
  435. int ret;
  436. sub_bus = dev_seq(bus);
  437. debug("%s: start\n", __func__);
  438. pciauto_config_init(hose);
  439. for (ret = device_find_first_child(bus, &dev);
  440. !ret && dev;
  441. ret = device_find_next_child(&dev)) {
  442. unsigned int max_bus;
  443. int ret;
  444. debug("%s: device %s\n", __func__, dev->name);
  445. if (dev_has_ofnode(dev) &&
  446. dev_read_bool(dev, "pci,no-autoconfig"))
  447. continue;
  448. ret = dm_pciauto_config_device(dev);
  449. if (ret < 0)
  450. return log_msg_ret("auto", ret);
  451. max_bus = ret;
  452. sub_bus = max(sub_bus, max_bus);
  453. pplat = dev_get_parent_plat(dev);
  454. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  455. set_vga_bridge_bits(dev);
  456. }
  457. debug("%s: done\n", __func__);
  458. return log_msg_ret("sub", sub_bus);
  459. }
  460. int pci_generic_mmap_write_config(
  461. const struct udevice *bus,
  462. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  463. void **addrp),
  464. pci_dev_t bdf,
  465. uint offset,
  466. ulong value,
  467. enum pci_size_t size)
  468. {
  469. void *address;
  470. if (addr_f(bus, bdf, offset, &address) < 0)
  471. return 0;
  472. switch (size) {
  473. case PCI_SIZE_8:
  474. writeb(value, address);
  475. return 0;
  476. case PCI_SIZE_16:
  477. writew(value, address);
  478. return 0;
  479. case PCI_SIZE_32:
  480. writel(value, address);
  481. return 0;
  482. default:
  483. return -EINVAL;
  484. }
  485. }
  486. int pci_generic_mmap_read_config(
  487. const struct udevice *bus,
  488. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  489. void **addrp),
  490. pci_dev_t bdf,
  491. uint offset,
  492. ulong *valuep,
  493. enum pci_size_t size)
  494. {
  495. void *address;
  496. if (addr_f(bus, bdf, offset, &address) < 0) {
  497. *valuep = pci_get_ff(size);
  498. return 0;
  499. }
  500. switch (size) {
  501. case PCI_SIZE_8:
  502. *valuep = readb(address);
  503. return 0;
  504. case PCI_SIZE_16:
  505. *valuep = readw(address);
  506. return 0;
  507. case PCI_SIZE_32:
  508. *valuep = readl(address);
  509. return 0;
  510. default:
  511. return -EINVAL;
  512. }
  513. }
  514. int dm_pci_hose_probe_bus(struct udevice *bus)
  515. {
  516. int sub_bus;
  517. int ret;
  518. int ea_pos;
  519. u8 reg;
  520. debug("%s\n", __func__);
  521. ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
  522. if (ea_pos) {
  523. dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
  524. &reg);
  525. sub_bus = reg;
  526. } else {
  527. sub_bus = pci_get_bus_max() + 1;
  528. }
  529. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  530. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  531. ret = device_probe(bus);
  532. if (ret) {
  533. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  534. ret);
  535. return log_msg_ret("probe", ret);
  536. }
  537. if (!ea_pos)
  538. sub_bus = pci_get_bus_max();
  539. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  540. return sub_bus;
  541. }
  542. /**
  543. * pci_match_one_device - Tell if a PCI device structure has a matching
  544. * PCI device id structure
  545. * @id: single PCI device id structure to match
  546. * @find: the PCI device id structure to match against
  547. *
  548. * Returns true if the finding pci_device_id structure matched or false if
  549. * there is no match.
  550. */
  551. static bool pci_match_one_id(const struct pci_device_id *id,
  552. const struct pci_device_id *find)
  553. {
  554. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  555. (id->device == PCI_ANY_ID || id->device == find->device) &&
  556. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  557. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  558. !((id->class ^ find->class) & id->class_mask))
  559. return true;
  560. return false;
  561. }
  562. /**
  563. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  564. *
  565. * This only looks at certain fields in the descriptor.
  566. *
  567. * @parent: Parent bus
  568. * @find_id: Specification of the driver to find
  569. * @bdf: Bus/device/function addreess - see PCI_BDF()
  570. * @devp: Returns a pointer to the device created
  571. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  572. * therefore was not created, other -ve value on error
  573. */
  574. static int pci_find_and_bind_driver(struct udevice *parent,
  575. struct pci_device_id *find_id,
  576. pci_dev_t bdf, struct udevice **devp)
  577. {
  578. struct pci_driver_entry *start, *entry;
  579. ofnode node = ofnode_null();
  580. const char *drv;
  581. int n_ents;
  582. int ret;
  583. char name[30], *str;
  584. bool bridge;
  585. *devp = NULL;
  586. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  587. find_id->vendor, find_id->device);
  588. /* Determine optional OF node */
  589. if (ofnode_valid(dev_ofnode(parent)))
  590. pci_dev_find_ofnode(parent, bdf, &node);
  591. if (ofnode_valid(node) && !ofnode_is_available(node)) {
  592. debug("%s: Ignoring disabled device\n", __func__);
  593. return log_msg_ret("dis", -EPERM);
  594. }
  595. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  596. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  597. for (entry = start; entry != start + n_ents; entry++) {
  598. const struct pci_device_id *id;
  599. struct udevice *dev;
  600. const struct driver *drv;
  601. for (id = entry->match;
  602. id->vendor || id->subvendor || id->class_mask;
  603. id++) {
  604. if (!pci_match_one_id(id, find_id))
  605. continue;
  606. drv = entry->driver;
  607. /*
  608. * In the pre-relocation phase, we only bind devices
  609. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  610. * precious memory space as on some platforms as that
  611. * space is pretty limited (ie: using Cache As RAM).
  612. */
  613. if (!(gd->flags & GD_FLG_RELOC) &&
  614. !(drv->flags & DM_FLAG_PRE_RELOC))
  615. return log_msg_ret("pre", -EPERM);
  616. /*
  617. * We could pass the descriptor to the driver as
  618. * plat (instead of NULL) and allow its bind()
  619. * method to return -ENOENT if it doesn't support this
  620. * device. That way we could continue the search to
  621. * find another driver. For now this doesn't seem
  622. * necesssary, so just bind the first match.
  623. */
  624. ret = device_bind(parent, drv, drv->name, NULL, node,
  625. &dev);
  626. if (ret)
  627. goto error;
  628. debug("%s: Match found: %s\n", __func__, drv->name);
  629. dev->driver_data = id->driver_data;
  630. *devp = dev;
  631. return 0;
  632. }
  633. }
  634. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  635. /*
  636. * In the pre-relocation phase, we only bind bridge devices to save
  637. * precious memory space as on some platforms as that space is pretty
  638. * limited (ie: using Cache As RAM).
  639. */
  640. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  641. return log_msg_ret("notbr", -EPERM);
  642. /* Bind a generic driver so that the device can be used */
  643. sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
  644. PCI_FUNC(bdf));
  645. str = strdup(name);
  646. if (!str)
  647. return -ENOMEM;
  648. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  649. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  650. if (ret) {
  651. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  652. free(str);
  653. return ret;
  654. }
  655. debug("%s: No match found: bound generic driver instead\n", __func__);
  656. return 0;
  657. error:
  658. debug("%s: No match found: error %d\n", __func__, ret);
  659. return ret;
  660. }
  661. __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
  662. {
  663. }
  664. int pci_bind_bus_devices(struct udevice *bus)
  665. {
  666. ulong vendor, device;
  667. ulong header_type;
  668. pci_dev_t bdf, end;
  669. bool found_multi;
  670. int ari_off;
  671. int ret;
  672. found_multi = false;
  673. end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
  674. PCI_MAX_PCI_FUNCTIONS - 1);
  675. for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
  676. bdf += PCI_BDF(0, 0, 1)) {
  677. struct pci_child_plat *pplat;
  678. struct udevice *dev;
  679. ulong class;
  680. if (!PCI_FUNC(bdf))
  681. found_multi = false;
  682. if (PCI_FUNC(bdf) && !found_multi)
  683. continue;
  684. /* Check only the first access, we don't expect problems */
  685. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  686. PCI_SIZE_16);
  687. if (ret)
  688. goto error;
  689. if (vendor == 0xffff || vendor == 0x0000)
  690. continue;
  691. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  692. &header_type, PCI_SIZE_8);
  693. if (!PCI_FUNC(bdf))
  694. found_multi = header_type & 0x80;
  695. debug("%s: bus %d/%s: found device %x, function %d", __func__,
  696. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  697. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  698. PCI_SIZE_16);
  699. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  700. PCI_SIZE_32);
  701. class >>= 8;
  702. /* Find this device in the device tree */
  703. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  704. debug(": find ret=%d\n", ret);
  705. /* If nothing in the device tree, bind a device */
  706. if (ret == -ENODEV) {
  707. struct pci_device_id find_id;
  708. ulong val;
  709. memset(&find_id, '\0', sizeof(find_id));
  710. find_id.vendor = vendor;
  711. find_id.device = device;
  712. find_id.class = class;
  713. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  714. pci_bus_read_config(bus, bdf,
  715. PCI_SUBSYSTEM_VENDOR_ID,
  716. &val, PCI_SIZE_32);
  717. find_id.subvendor = val & 0xffff;
  718. find_id.subdevice = val >> 16;
  719. }
  720. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  721. &dev);
  722. }
  723. if (ret == -EPERM)
  724. continue;
  725. else if (ret)
  726. return ret;
  727. /* Update the platform data */
  728. pplat = dev_get_parent_plat(dev);
  729. pplat->devfn = PCI_MASK_BUS(bdf);
  730. pplat->vendor = vendor;
  731. pplat->device = device;
  732. pplat->class = class;
  733. if (IS_ENABLED(CONFIG_PCI_ARID)) {
  734. ari_off = dm_pci_find_ext_capability(dev,
  735. PCI_EXT_CAP_ID_ARI);
  736. if (ari_off) {
  737. u16 ari_cap;
  738. /*
  739. * Read Next Function number in ARI Cap
  740. * Register
  741. */
  742. dm_pci_read_config16(dev, ari_off + 4,
  743. &ari_cap);
  744. /*
  745. * Update next scan on this function number,
  746. * subtract 1 in BDF to satisfy loop increment.
  747. */
  748. if (ari_cap & 0xff00) {
  749. bdf = PCI_BDF(PCI_BUS(bdf),
  750. PCI_DEV(ari_cap),
  751. PCI_FUNC(ari_cap));
  752. bdf = bdf - 0x100;
  753. }
  754. }
  755. }
  756. board_pci_fixup_dev(bus, dev);
  757. }
  758. return 0;
  759. error:
  760. printf("Cannot read bus configuration: %d\n", ret);
  761. return ret;
  762. }
  763. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  764. ofnode node)
  765. {
  766. int pci_addr_cells, addr_cells, size_cells;
  767. int cells_per_record;
  768. struct bd_info *bd;
  769. const u32 *prop;
  770. int max_regions;
  771. int len;
  772. int i;
  773. prop = ofnode_get_property(node, "ranges", &len);
  774. if (!prop) {
  775. debug("%s: Cannot decode regions\n", __func__);
  776. return;
  777. }
  778. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  779. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  780. size_cells = ofnode_read_simple_size_cells(node);
  781. /* PCI addresses are always 3-cells */
  782. len /= sizeof(u32);
  783. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  784. hose->region_count = 0;
  785. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  786. cells_per_record);
  787. /* Dynamically allocate the regions array */
  788. max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
  789. hose->regions = (struct pci_region *)
  790. calloc(1, max_regions * sizeof(struct pci_region));
  791. for (i = 0; i < max_regions; i++, len -= cells_per_record) {
  792. u64 pci_addr, addr, size;
  793. int space_code;
  794. u32 flags;
  795. int type;
  796. int pos;
  797. if (len < cells_per_record)
  798. break;
  799. flags = fdt32_to_cpu(prop[0]);
  800. space_code = (flags >> 24) & 3;
  801. pci_addr = fdtdec_get_number(prop + 1, 2);
  802. prop += pci_addr_cells;
  803. addr = fdtdec_get_number(prop, addr_cells);
  804. prop += addr_cells;
  805. size = fdtdec_get_number(prop, size_cells);
  806. prop += size_cells;
  807. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  808. __func__, hose->region_count, pci_addr, addr, size, space_code);
  809. if (space_code & 2) {
  810. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  811. PCI_REGION_MEM;
  812. } else if (space_code & 1) {
  813. type = PCI_REGION_IO;
  814. } else {
  815. continue;
  816. }
  817. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  818. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  819. debug(" - beyond the 32-bit boundary, ignoring\n");
  820. continue;
  821. }
  822. pos = -1;
  823. if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
  824. for (i = 0; i < hose->region_count; i++) {
  825. if (hose->regions[i].flags == type)
  826. pos = i;
  827. }
  828. }
  829. if (pos == -1)
  830. pos = hose->region_count++;
  831. debug(" - type=%d, pos=%d\n", type, pos);
  832. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  833. }
  834. /* Add a region for our local memory */
  835. bd = gd->bd;
  836. if (!bd)
  837. return;
  838. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  839. if (bd->bi_dram[i].size) {
  840. pci_set_region(hose->regions + hose->region_count++,
  841. bd->bi_dram[i].start,
  842. bd->bi_dram[i].start,
  843. bd->bi_dram[i].size,
  844. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  845. }
  846. }
  847. return;
  848. }
  849. static int pci_uclass_pre_probe(struct udevice *bus)
  850. {
  851. struct pci_controller *hose;
  852. struct uclass *uc;
  853. int ret;
  854. debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
  855. bus->parent->name);
  856. hose = dev_get_uclass_priv(bus);
  857. /*
  858. * Set the sequence number, if device_bind() doesn't. We want control
  859. * of this so that numbers are allocated as devices are probed. That
  860. * ensures that sub-bus numbered is correct (sub-buses must get numbers
  861. * higher than their parents)
  862. */
  863. if (dev_seq(bus) == -1) {
  864. ret = uclass_get(UCLASS_PCI, &uc);
  865. if (ret)
  866. return ret;
  867. bus->seq_ = uclass_find_next_free_seq(uc);
  868. }
  869. /* For bridges, use the top-level PCI controller */
  870. if (!device_is_on_pci_bus(bus)) {
  871. hose->ctlr = bus;
  872. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  873. } else {
  874. struct pci_controller *parent_hose;
  875. parent_hose = dev_get_uclass_priv(bus->parent);
  876. hose->ctlr = parent_hose->bus;
  877. }
  878. hose->bus = bus;
  879. hose->first_busno = dev_seq(bus);
  880. hose->last_busno = dev_seq(bus);
  881. if (dev_has_ofnode(bus)) {
  882. hose->skip_auto_config_until_reloc =
  883. dev_read_bool(bus,
  884. "u-boot,skip-auto-config-until-reloc");
  885. }
  886. return 0;
  887. }
  888. static int pci_uclass_post_probe(struct udevice *bus)
  889. {
  890. struct pci_controller *hose = dev_get_uclass_priv(bus);
  891. int ret;
  892. debug("%s: probing bus %d\n", __func__, dev_seq(bus));
  893. ret = pci_bind_bus_devices(bus);
  894. if (ret)
  895. return log_msg_ret("bind", ret);
  896. if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
  897. (!hose->skip_auto_config_until_reloc ||
  898. (gd->flags & GD_FLG_RELOC))) {
  899. ret = pci_auto_config_devices(bus);
  900. if (ret < 0)
  901. return log_msg_ret("cfg", ret);
  902. }
  903. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  904. /*
  905. * Per Intel FSP specification, we should call FSP notify API to
  906. * inform FSP that PCI enumeration has been done so that FSP will
  907. * do any necessary initialization as required by the chipset's
  908. * BIOS Writer's Guide (BWG).
  909. *
  910. * Unfortunately we have to put this call here as with driver model,
  911. * the enumeration is all done on a lazy basis as needed, so until
  912. * something is touched on PCI it won't happen.
  913. *
  914. * Note we only call this 1) after U-Boot is relocated, and 2)
  915. * root bus has finished probing.
  916. */
  917. if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
  918. ret = fsp_init_phase_pci();
  919. if (ret)
  920. return log_msg_ret("fsp", ret);
  921. }
  922. #endif
  923. return 0;
  924. }
  925. static int pci_uclass_child_post_bind(struct udevice *dev)
  926. {
  927. struct pci_child_plat *pplat;
  928. if (!dev_has_ofnode(dev))
  929. return 0;
  930. pplat = dev_get_parent_plat(dev);
  931. /* Extract vendor id and device id if available */
  932. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  933. /* Extract the devfn from fdt_pci_addr */
  934. pplat->devfn = pci_get_devfn(dev);
  935. return 0;
  936. }
  937. static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
  938. uint offset, ulong *valuep,
  939. enum pci_size_t size)
  940. {
  941. struct pci_controller *hose = dev_get_uclass_priv(bus);
  942. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  943. }
  944. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  945. uint offset, ulong value,
  946. enum pci_size_t size)
  947. {
  948. struct pci_controller *hose = dev_get_uclass_priv(bus);
  949. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  950. }
  951. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  952. {
  953. struct udevice *dev;
  954. int ret = 0;
  955. /*
  956. * Scan through all the PCI controllers. On x86 there will only be one
  957. * but that is not necessarily true on other hardware.
  958. */
  959. do {
  960. device_find_first_child(bus, &dev);
  961. if (dev) {
  962. *devp = dev;
  963. return 0;
  964. }
  965. ret = uclass_next_device(&bus);
  966. if (ret)
  967. return ret;
  968. } while (bus);
  969. return 0;
  970. }
  971. int pci_find_next_device(struct udevice **devp)
  972. {
  973. struct udevice *child = *devp;
  974. struct udevice *bus = child->parent;
  975. int ret;
  976. /* First try all the siblings */
  977. *devp = NULL;
  978. while (child) {
  979. device_find_next_child(&child);
  980. if (child) {
  981. *devp = child;
  982. return 0;
  983. }
  984. }
  985. /* We ran out of siblings. Try the next bus */
  986. ret = uclass_next_device(&bus);
  987. if (ret)
  988. return ret;
  989. return bus ? skip_to_next_device(bus, devp) : 0;
  990. }
  991. int pci_find_first_device(struct udevice **devp)
  992. {
  993. struct udevice *bus;
  994. int ret;
  995. *devp = NULL;
  996. ret = uclass_first_device(UCLASS_PCI, &bus);
  997. if (ret)
  998. return ret;
  999. return skip_to_next_device(bus, devp);
  1000. }
  1001. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  1002. {
  1003. switch (size) {
  1004. case PCI_SIZE_8:
  1005. return (value >> ((offset & 3) * 8)) & 0xff;
  1006. case PCI_SIZE_16:
  1007. return (value >> ((offset & 2) * 8)) & 0xffff;
  1008. default:
  1009. return value;
  1010. }
  1011. }
  1012. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  1013. enum pci_size_t size)
  1014. {
  1015. uint off_mask;
  1016. uint val_mask, shift;
  1017. ulong ldata, mask;
  1018. switch (size) {
  1019. case PCI_SIZE_8:
  1020. off_mask = 3;
  1021. val_mask = 0xff;
  1022. break;
  1023. case PCI_SIZE_16:
  1024. off_mask = 2;
  1025. val_mask = 0xffff;
  1026. break;
  1027. default:
  1028. return value;
  1029. }
  1030. shift = (offset & off_mask) * 8;
  1031. ldata = (value & val_mask) << shift;
  1032. mask = val_mask << shift;
  1033. value = (old & ~mask) | ldata;
  1034. return value;
  1035. }
  1036. int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
  1037. {
  1038. int pci_addr_cells, addr_cells, size_cells;
  1039. int cells_per_record;
  1040. const u32 *prop;
  1041. int len;
  1042. int i = 0;
  1043. prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
  1044. if (!prop) {
  1045. log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
  1046. dev->name);
  1047. return -EINVAL;
  1048. }
  1049. pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
  1050. addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
  1051. size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
  1052. /* PCI addresses are always 3-cells */
  1053. len /= sizeof(u32);
  1054. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  1055. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  1056. cells_per_record);
  1057. while (len) {
  1058. memp->bus_start = fdtdec_get_number(prop + 1, 2);
  1059. prop += pci_addr_cells;
  1060. memp->phys_start = fdtdec_get_number(prop, addr_cells);
  1061. prop += addr_cells;
  1062. memp->size = fdtdec_get_number(prop, size_cells);
  1063. prop += size_cells;
  1064. if (i == index)
  1065. return 0;
  1066. i++;
  1067. len -= cells_per_record;
  1068. }
  1069. return -EINVAL;
  1070. }
  1071. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  1072. struct pci_region **memp, struct pci_region **prefp)
  1073. {
  1074. struct udevice *bus = pci_get_controller(dev);
  1075. struct pci_controller *hose = dev_get_uclass_priv(bus);
  1076. int i;
  1077. *iop = NULL;
  1078. *memp = NULL;
  1079. *prefp = NULL;
  1080. for (i = 0; i < hose->region_count; i++) {
  1081. switch (hose->regions[i].flags) {
  1082. case PCI_REGION_IO:
  1083. if (!*iop || (*iop)->size < hose->regions[i].size)
  1084. *iop = hose->regions + i;
  1085. break;
  1086. case PCI_REGION_MEM:
  1087. if (!*memp || (*memp)->size < hose->regions[i].size)
  1088. *memp = hose->regions + i;
  1089. break;
  1090. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  1091. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  1092. *prefp = hose->regions + i;
  1093. break;
  1094. }
  1095. }
  1096. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  1097. }
  1098. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
  1099. {
  1100. u32 addr;
  1101. int bar;
  1102. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1103. dm_pci_read_config32(dev, bar, &addr);
  1104. /*
  1105. * If we get an invalid address, return this so that comparisons with
  1106. * FDT_ADDR_T_NONE work correctly
  1107. */
  1108. if (addr == 0xffffffff)
  1109. return addr;
  1110. else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1111. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1112. else
  1113. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1114. }
  1115. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1116. {
  1117. int bar;
  1118. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1119. dm_pci_write_config32(dev, bar, addr);
  1120. }
  1121. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1122. pci_addr_t bus_addr, unsigned long flags,
  1123. unsigned long skip_mask, phys_addr_t *pa)
  1124. {
  1125. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1126. struct pci_region *res;
  1127. int i;
  1128. if (hose->region_count == 0) {
  1129. *pa = bus_addr;
  1130. return 0;
  1131. }
  1132. for (i = 0; i < hose->region_count; i++) {
  1133. res = &hose->regions[i];
  1134. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1135. continue;
  1136. if (res->flags & skip_mask)
  1137. continue;
  1138. if (bus_addr >= res->bus_start &&
  1139. (bus_addr - res->bus_start) < res->size) {
  1140. *pa = (bus_addr - res->bus_start + res->phys_start);
  1141. return 0;
  1142. }
  1143. }
  1144. return 1;
  1145. }
  1146. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1147. unsigned long flags)
  1148. {
  1149. phys_addr_t phys_addr = 0;
  1150. struct udevice *ctlr;
  1151. int ret;
  1152. /* The root controller has the region information */
  1153. ctlr = pci_get_controller(dev);
  1154. /*
  1155. * if PCI_REGION_MEM is set we do a two pass search with preference
  1156. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1157. */
  1158. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1159. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1160. flags, PCI_REGION_SYS_MEMORY,
  1161. &phys_addr);
  1162. if (!ret)
  1163. return phys_addr;
  1164. }
  1165. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1166. if (ret)
  1167. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1168. return phys_addr;
  1169. }
  1170. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1171. unsigned long flags, unsigned long skip_mask,
  1172. pci_addr_t *ba)
  1173. {
  1174. struct pci_region *res;
  1175. struct udevice *ctlr;
  1176. pci_addr_t bus_addr;
  1177. int i;
  1178. struct pci_controller *hose;
  1179. /* The root controller has the region information */
  1180. ctlr = pci_get_controller(dev);
  1181. hose = dev_get_uclass_priv(ctlr);
  1182. if (hose->region_count == 0) {
  1183. *ba = phys_addr;
  1184. return 0;
  1185. }
  1186. for (i = 0; i < hose->region_count; i++) {
  1187. res = &hose->regions[i];
  1188. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1189. continue;
  1190. if (res->flags & skip_mask)
  1191. continue;
  1192. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1193. if (bus_addr >= res->bus_start &&
  1194. (bus_addr - res->bus_start) < res->size) {
  1195. *ba = bus_addr;
  1196. return 0;
  1197. }
  1198. }
  1199. return 1;
  1200. }
  1201. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1202. unsigned long flags)
  1203. {
  1204. pci_addr_t bus_addr = 0;
  1205. int ret;
  1206. /*
  1207. * if PCI_REGION_MEM is set we do a two pass search with preference
  1208. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1209. */
  1210. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1211. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1212. PCI_REGION_SYS_MEMORY, &bus_addr);
  1213. if (!ret)
  1214. return bus_addr;
  1215. }
  1216. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1217. if (ret)
  1218. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1219. return bus_addr;
  1220. }
  1221. static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
  1222. struct pci_child_plat *pdata)
  1223. {
  1224. phys_addr_t addr = 0;
  1225. /*
  1226. * In the case of a Virtual Function device using BAR
  1227. * base and size, add offset for VFn BAR(1, 2, 3...n)
  1228. */
  1229. if (pdata->is_virtfn) {
  1230. size_t sz;
  1231. u32 ea_entry;
  1232. /* MaxOffset, 1st DW */
  1233. dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
  1234. sz = ea_entry & PCI_EA_FIELD_MASK;
  1235. /* Fill up lower 2 bits */
  1236. sz |= (~PCI_EA_FIELD_MASK);
  1237. if (ea_entry & PCI_EA_IS_64) {
  1238. /* MaxOffset 2nd DW */
  1239. dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
  1240. sz |= ((u64)ea_entry) << 32;
  1241. }
  1242. addr = (pdata->virtid - 1) * (sz + 1);
  1243. }
  1244. return addr;
  1245. }
  1246. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1247. int ea_off, struct pci_child_plat *pdata)
  1248. {
  1249. int ea_cnt, i, entry_size;
  1250. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1251. u32 ea_entry;
  1252. phys_addr_t addr;
  1253. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1254. /*
  1255. * In the case of a Virtual Function device, device is
  1256. * Physical function, so pdata will point to required VF
  1257. * specific data.
  1258. */
  1259. if (pdata->is_virtfn)
  1260. bar_id += PCI_EA_BEI_VF_BAR0;
  1261. }
  1262. /* EA capability structure header */
  1263. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1264. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1265. ea_off += PCI_EA_FIRST_ENT;
  1266. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1267. /* Entry header */
  1268. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1269. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1270. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1271. continue;
  1272. /* Base address, 1st DW */
  1273. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1274. addr = ea_entry & PCI_EA_FIELD_MASK;
  1275. if (ea_entry & PCI_EA_IS_64) {
  1276. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1277. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1278. addr |= ((u64)ea_entry) << 32;
  1279. }
  1280. if (IS_ENABLED(CONFIG_PCI_SRIOV))
  1281. addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
  1282. /* size ignored for now */
  1283. return map_physmem(addr, 0, flags);
  1284. }
  1285. return 0;
  1286. }
  1287. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1288. {
  1289. struct pci_child_plat *pdata = dev_get_parent_plat(dev);
  1290. struct udevice *udev = dev;
  1291. pci_addr_t pci_bus_addr;
  1292. u32 bar_response;
  1293. int ea_off;
  1294. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1295. /*
  1296. * In case of Virtual Function devices, use PF udevice
  1297. * as EA capability is defined in Physical Function
  1298. */
  1299. if (pdata->is_virtfn)
  1300. udev = pdata->pfdev;
  1301. }
  1302. /*
  1303. * if the function supports Enhanced Allocation use that instead of
  1304. * BARs
  1305. * Incase of virtual functions, pdata will help read VF BEI
  1306. * and EA entry size.
  1307. */
  1308. ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
  1309. if (ea_off)
  1310. return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
  1311. /* read BAR address */
  1312. dm_pci_read_config32(udev, bar, &bar_response);
  1313. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1314. /*
  1315. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1316. * isn't actually used on any platform because U-Boot assumes a static
  1317. * linear mapping. In the future, this could read the BAR size
  1318. * and pass that as the size if needed.
  1319. */
  1320. return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1321. }
  1322. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1323. {
  1324. int ttl = PCI_FIND_CAP_TTL;
  1325. u8 id;
  1326. u16 ent;
  1327. dm_pci_read_config8(dev, pos, &pos);
  1328. while (ttl--) {
  1329. if (pos < PCI_STD_HEADER_SIZEOF)
  1330. break;
  1331. pos &= ~3;
  1332. dm_pci_read_config16(dev, pos, &ent);
  1333. id = ent & 0xff;
  1334. if (id == 0xff)
  1335. break;
  1336. if (id == cap)
  1337. return pos;
  1338. pos = (ent >> 8);
  1339. }
  1340. return 0;
  1341. }
  1342. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1343. {
  1344. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1345. cap);
  1346. }
  1347. int dm_pci_find_capability(struct udevice *dev, int cap)
  1348. {
  1349. u16 status;
  1350. u8 header_type;
  1351. u8 pos;
  1352. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1353. if (!(status & PCI_STATUS_CAP_LIST))
  1354. return 0;
  1355. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1356. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1357. pos = PCI_CB_CAPABILITY_LIST;
  1358. else
  1359. pos = PCI_CAPABILITY_LIST;
  1360. return _dm_pci_find_next_capability(dev, pos, cap);
  1361. }
  1362. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1363. {
  1364. u32 header;
  1365. int ttl;
  1366. int pos = PCI_CFG_SPACE_SIZE;
  1367. /* minimum 8 bytes per capability */
  1368. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1369. if (start)
  1370. pos = start;
  1371. dm_pci_read_config32(dev, pos, &header);
  1372. /*
  1373. * If we have no capabilities, this is indicated by cap ID,
  1374. * cap version and next pointer all being 0.
  1375. */
  1376. if (header == 0)
  1377. return 0;
  1378. while (ttl--) {
  1379. if (PCI_EXT_CAP_ID(header) == cap)
  1380. return pos;
  1381. pos = PCI_EXT_CAP_NEXT(header);
  1382. if (pos < PCI_CFG_SPACE_SIZE)
  1383. break;
  1384. dm_pci_read_config32(dev, pos, &header);
  1385. }
  1386. return 0;
  1387. }
  1388. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1389. {
  1390. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1391. }
  1392. int dm_pci_flr(struct udevice *dev)
  1393. {
  1394. int pcie_off;
  1395. u32 cap;
  1396. /* look for PCI Express Capability */
  1397. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1398. if (!pcie_off)
  1399. return -ENOENT;
  1400. /* check FLR capability */
  1401. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1402. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1403. return -ENOENT;
  1404. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1405. PCI_EXP_DEVCTL_BCR_FLR);
  1406. /* wait 100ms, per PCI spec */
  1407. mdelay(100);
  1408. return 0;
  1409. }
  1410. #if defined(CONFIG_PCI_SRIOV)
  1411. int pci_sriov_init(struct udevice *pdev, int vf_en)
  1412. {
  1413. u16 vendor, device;
  1414. struct udevice *bus;
  1415. struct udevice *dev;
  1416. pci_dev_t bdf;
  1417. u16 ctrl;
  1418. u16 num_vfs;
  1419. u16 total_vf;
  1420. u16 vf_offset;
  1421. u16 vf_stride;
  1422. int vf, ret;
  1423. int pos;
  1424. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1425. if (!pos) {
  1426. debug("Error: SRIOV capability not found\n");
  1427. return -ENOENT;
  1428. }
  1429. dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
  1430. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1431. if (vf_en > total_vf)
  1432. vf_en = total_vf;
  1433. dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
  1434. ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
  1435. dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
  1436. dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
  1437. if (num_vfs > vf_en)
  1438. num_vfs = vf_en;
  1439. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
  1440. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
  1441. dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
  1442. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
  1443. bdf = dm_pci_get_bdf(pdev);
  1444. pci_get_bus(PCI_BUS(bdf), &bus);
  1445. if (!bus)
  1446. return -ENODEV;
  1447. bdf += PCI_BDF(0, 0, vf_offset);
  1448. for (vf = 0; vf < num_vfs; vf++) {
  1449. struct pci_child_plat *pplat;
  1450. ulong class;
  1451. pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
  1452. &class, PCI_SIZE_16);
  1453. debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
  1454. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  1455. /* Find this device in the device tree */
  1456. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  1457. if (ret == -ENODEV) {
  1458. struct pci_device_id find_id;
  1459. memset(&find_id, '\0', sizeof(find_id));
  1460. find_id.vendor = vendor;
  1461. find_id.device = device;
  1462. find_id.class = class;
  1463. ret = pci_find_and_bind_driver(bus, &find_id,
  1464. bdf, &dev);
  1465. if (ret)
  1466. return ret;
  1467. }
  1468. /* Update the platform data */
  1469. pplat = dev_get_parent_plat(dev);
  1470. pplat->devfn = PCI_MASK_BUS(bdf);
  1471. pplat->vendor = vendor;
  1472. pplat->device = device;
  1473. pplat->class = class;
  1474. pplat->is_virtfn = true;
  1475. pplat->pfdev = pdev;
  1476. pplat->virtid = vf * vf_stride + vf_offset;
  1477. debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
  1478. __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
  1479. PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
  1480. bdf += PCI_BDF(0, 0, vf_stride);
  1481. }
  1482. return 0;
  1483. }
  1484. int pci_sriov_get_totalvfs(struct udevice *pdev)
  1485. {
  1486. u16 total_vf;
  1487. int pos;
  1488. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1489. if (!pos) {
  1490. debug("Error: SRIOV capability not found\n");
  1491. return -ENOENT;
  1492. }
  1493. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1494. return total_vf;
  1495. }
  1496. #endif /* SRIOV */
  1497. UCLASS_DRIVER(pci) = {
  1498. .id = UCLASS_PCI,
  1499. .name = "pci",
  1500. .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
  1501. .post_bind = dm_scan_fdt_dev,
  1502. .pre_probe = pci_uclass_pre_probe,
  1503. .post_probe = pci_uclass_post_probe,
  1504. .child_post_bind = pci_uclass_child_post_bind,
  1505. .per_device_auto = sizeof(struct pci_controller),
  1506. .per_child_plat_auto = sizeof(struct pci_child_plat),
  1507. };
  1508. static const struct dm_pci_ops pci_bridge_ops = {
  1509. .read_config = pci_bridge_read_config,
  1510. .write_config = pci_bridge_write_config,
  1511. };
  1512. static const struct udevice_id pci_bridge_ids[] = {
  1513. { .compatible = "pci-bridge" },
  1514. { }
  1515. };
  1516. U_BOOT_DRIVER(pci_bridge_drv) = {
  1517. .name = "pci_bridge_drv",
  1518. .id = UCLASS_PCI,
  1519. .of_match = pci_bridge_ids,
  1520. .ops = &pci_bridge_ops,
  1521. };
  1522. UCLASS_DRIVER(pci_generic) = {
  1523. .id = UCLASS_PCI_GENERIC,
  1524. .name = "pci_generic",
  1525. };
  1526. static const struct udevice_id pci_generic_ids[] = {
  1527. { .compatible = "pci-generic" },
  1528. { }
  1529. };
  1530. U_BOOT_DRIVER(pci_generic_drv) = {
  1531. .name = "pci_generic_drv",
  1532. .id = UCLASS_PCI_GENERIC,
  1533. .of_match = pci_generic_ids,
  1534. };
  1535. int pci_init(void)
  1536. {
  1537. struct udevice *bus;
  1538. /*
  1539. * Enumerate all known controller devices. Enumeration has the side-
  1540. * effect of probing them, so PCIe devices will be enumerated too.
  1541. */
  1542. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1543. bus;
  1544. uclass_next_device_check(&bus)) {
  1545. ;
  1546. }
  1547. return 0;
  1548. }