clk-uclass.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #define LOG_CATEGORY UCLASS_CLK
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <dt-structs.h>
  14. #include <errno.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <dm/device_compat.h>
  18. #include <dm/device-internal.h>
  19. #include <dm/devres.h>
  20. #include <dm/read.h>
  21. #include <linux/bug.h>
  22. #include <linux/clk-provider.h>
  23. #include <linux/err.h>
  24. #include <asm/global_data.h>
  25. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  26. {
  27. return (const struct clk_ops *)dev->driver->ops;
  28. }
  29. struct clk *dev_get_clk_ptr(struct udevice *dev)
  30. {
  31. return (struct clk *)dev_get_uclass_priv(dev);
  32. }
  33. #if CONFIG_IS_ENABLED(OF_CONTROL)
  34. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  35. int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
  36. struct clk *clk)
  37. {
  38. int ret;
  39. ret = device_get_by_ofplat_idx(cells->idx, &clk->dev);
  40. if (ret)
  41. return ret;
  42. clk->id = cells->arg[0];
  43. return 0;
  44. }
  45. # else
  46. static int clk_of_xlate_default(struct clk *clk,
  47. struct ofnode_phandle_args *args)
  48. {
  49. debug("%s(clk=%p)\n", __func__, clk);
  50. if (args->args_count > 1) {
  51. debug("Invaild args_count: %d\n", args->args_count);
  52. return -EINVAL;
  53. }
  54. if (args->args_count)
  55. clk->id = args->args[0];
  56. else
  57. clk->id = 0;
  58. clk->data = 0;
  59. return 0;
  60. }
  61. static int clk_get_by_index_tail(int ret, ofnode node,
  62. struct ofnode_phandle_args *args,
  63. const char *list_name, int index,
  64. struct clk *clk)
  65. {
  66. struct udevice *dev_clk;
  67. const struct clk_ops *ops;
  68. assert(clk);
  69. clk->dev = NULL;
  70. if (ret)
  71. goto err;
  72. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  73. if (ret) {
  74. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  75. __func__, ret);
  76. return log_msg_ret("get", ret);
  77. }
  78. clk->dev = dev_clk;
  79. ops = clk_dev_ops(dev_clk);
  80. if (ops->of_xlate)
  81. ret = ops->of_xlate(clk, args);
  82. else
  83. ret = clk_of_xlate_default(clk, args);
  84. if (ret) {
  85. debug("of_xlate() failed: %d\n", ret);
  86. return log_msg_ret("xlate", ret);
  87. }
  88. return clk_request(dev_clk, clk);
  89. err:
  90. debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  91. __func__, ofnode_get_name(node), list_name, index, ret);
  92. return log_msg_ret("prop", ret);
  93. }
  94. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  95. int index, struct clk *clk)
  96. {
  97. int ret;
  98. struct ofnode_phandle_args args;
  99. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  100. assert(clk);
  101. clk->dev = NULL;
  102. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  103. index, &args);
  104. if (ret) {
  105. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  106. __func__, ret);
  107. return log_ret(ret);
  108. }
  109. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  110. index, clk);
  111. }
  112. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  113. {
  114. struct ofnode_phandle_args args;
  115. int ret;
  116. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  117. index, &args);
  118. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  119. index, clk);
  120. }
  121. int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
  122. {
  123. struct ofnode_phandle_args args;
  124. int ret;
  125. ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
  126. index, &args);
  127. return clk_get_by_index_tail(ret, node, &args, "clocks",
  128. index, clk);
  129. }
  130. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  131. {
  132. int i, ret, err, count;
  133. bulk->count = 0;
  134. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0);
  135. if (count < 1)
  136. return count;
  137. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  138. if (!bulk->clks)
  139. return -ENOMEM;
  140. for (i = 0; i < count; i++) {
  141. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  142. if (ret < 0)
  143. goto bulk_get_err;
  144. ++bulk->count;
  145. }
  146. return 0;
  147. bulk_get_err:
  148. err = clk_release_all(bulk->clks, bulk->count);
  149. if (err)
  150. debug("%s: could release all clocks for %p\n",
  151. __func__, dev);
  152. return ret;
  153. }
  154. static struct clk *clk_set_default_get_by_id(struct clk *clk)
  155. {
  156. struct clk *c = clk;
  157. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  158. int ret = clk_get_by_id(clk->id, &c);
  159. if (ret) {
  160. debug("%s(): could not get parent clock pointer, id %lu\n",
  161. __func__, clk->id);
  162. ERR_PTR(ret);
  163. }
  164. }
  165. return c;
  166. }
  167. static int clk_set_default_parents(struct udevice *dev,
  168. enum clk_defaults_stage stage)
  169. {
  170. struct clk clk, parent_clk, *c, *p;
  171. int index;
  172. int num_parents;
  173. int ret;
  174. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  175. "#clock-cells", 0);
  176. if (num_parents < 0) {
  177. debug("%s: could not read assigned-clock-parents for %p\n",
  178. __func__, dev);
  179. return 0;
  180. }
  181. for (index = 0; index < num_parents; index++) {
  182. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  183. index, &parent_clk);
  184. /* If -ENOENT, this is a no-op entry */
  185. if (ret == -ENOENT)
  186. continue;
  187. if (ret) {
  188. debug("%s: could not get parent clock %d for %s\n",
  189. __func__, index, dev_read_name(dev));
  190. return ret;
  191. }
  192. p = clk_set_default_get_by_id(&parent_clk);
  193. if (IS_ERR(p))
  194. return PTR_ERR(p);
  195. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  196. index, &clk);
  197. /*
  198. * If the clock provider is not ready yet, let it handle
  199. * the re-programming later.
  200. */
  201. if (ret == -EPROBE_DEFER) {
  202. ret = 0;
  203. continue;
  204. }
  205. if (ret) {
  206. debug("%s: could not get assigned clock %d for %s\n",
  207. __func__, index, dev_read_name(dev));
  208. return ret;
  209. }
  210. /* This is clk provider device trying to reparent itself
  211. * It cannot be done right now but need to wait after the
  212. * device is probed
  213. */
  214. if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
  215. continue;
  216. if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
  217. /* do not setup twice the parent clocks */
  218. continue;
  219. c = clk_set_default_get_by_id(&clk);
  220. if (IS_ERR(c))
  221. return PTR_ERR(c);
  222. ret = clk_set_parent(c, p);
  223. /*
  224. * Not all drivers may support clock-reparenting (as of now).
  225. * Ignore errors due to this.
  226. */
  227. if (ret == -ENOSYS)
  228. continue;
  229. if (ret < 0) {
  230. debug("%s: failed to reparent clock %d for %s\n",
  231. __func__, index, dev_read_name(dev));
  232. return ret;
  233. }
  234. }
  235. return 0;
  236. }
  237. static int clk_set_default_rates(struct udevice *dev,
  238. enum clk_defaults_stage stage)
  239. {
  240. struct clk clk, *c;
  241. int index;
  242. int num_rates;
  243. int size;
  244. int ret = 0;
  245. u32 *rates = NULL;
  246. size = dev_read_size(dev, "assigned-clock-rates");
  247. if (size < 0)
  248. return 0;
  249. num_rates = size / sizeof(u32);
  250. rates = calloc(num_rates, sizeof(u32));
  251. if (!rates)
  252. return -ENOMEM;
  253. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  254. if (ret)
  255. goto fail;
  256. for (index = 0; index < num_rates; index++) {
  257. /* If 0 is passed, this is a no-op */
  258. if (!rates[index])
  259. continue;
  260. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  261. index, &clk);
  262. /*
  263. * If the clock provider is not ready yet, let it handle
  264. * the re-programming later.
  265. */
  266. if (ret == -EPROBE_DEFER) {
  267. ret = 0;
  268. continue;
  269. }
  270. if (ret) {
  271. dev_dbg(dev,
  272. "could not get assigned clock %d (err = %d)\n",
  273. index, ret);
  274. continue;
  275. }
  276. /* This is clk provider device trying to program itself
  277. * It cannot be done right now but need to wait after the
  278. * device is probed
  279. */
  280. if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
  281. continue;
  282. if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
  283. /* do not setup twice the parent clocks */
  284. continue;
  285. c = clk_set_default_get_by_id(&clk);
  286. if (IS_ERR(c))
  287. return PTR_ERR(c);
  288. ret = clk_set_rate(c, rates[index]);
  289. if (ret < 0) {
  290. dev_warn(dev,
  291. "failed to set rate on clock index %d (%ld) (error = %d)\n",
  292. index, clk.id, ret);
  293. break;
  294. }
  295. }
  296. fail:
  297. free(rates);
  298. return ret;
  299. }
  300. int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage)
  301. {
  302. int ret;
  303. if (!dev_has_ofnode(dev))
  304. return 0;
  305. /*
  306. * To avoid setting defaults twice, don't set them before relocation.
  307. * However, still set them for SPL. And still set them if explicitly
  308. * asked.
  309. */
  310. if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
  311. if (stage != CLK_DEFAULTS_POST_FORCE)
  312. return 0;
  313. debug("%s(%s)\n", __func__, dev_read_name(dev));
  314. ret = clk_set_default_parents(dev, stage);
  315. if (ret)
  316. return ret;
  317. ret = clk_set_default_rates(dev, stage);
  318. if (ret < 0)
  319. return ret;
  320. return 0;
  321. }
  322. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  323. {
  324. int index;
  325. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  326. clk->dev = NULL;
  327. index = dev_read_stringlist_search(dev, "clock-names", name);
  328. if (index < 0) {
  329. debug("fdt_stringlist_search() failed: %d\n", index);
  330. return index;
  331. }
  332. return clk_get_by_index(dev, index, clk);
  333. }
  334. # endif /* OF_PLATDATA */
  335. int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
  336. {
  337. int index;
  338. debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
  339. ofnode_get_name(node), name, clk);
  340. clk->dev = NULL;
  341. index = ofnode_stringlist_search(node, "clock-names", name);
  342. if (index < 0) {
  343. debug("fdt_stringlist_search() failed: %d\n", index);
  344. return index;
  345. }
  346. return clk_get_by_index_nodev(node, index, clk);
  347. }
  348. int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
  349. {
  350. int ret;
  351. ret = clk_get_by_name_nodev(node, name, clk);
  352. if (ret == -ENODATA)
  353. return 0;
  354. return ret;
  355. }
  356. int clk_release_all(struct clk *clk, int count)
  357. {
  358. int i, ret;
  359. for (i = 0; i < count; i++) {
  360. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  361. /* check if clock has been previously requested */
  362. if (!clk[i].dev)
  363. continue;
  364. ret = clk_disable(&clk[i]);
  365. if (ret && ret != -ENOSYS)
  366. return ret;
  367. ret = clk_free(&clk[i]);
  368. if (ret && ret != -ENOSYS)
  369. return ret;
  370. }
  371. return 0;
  372. }
  373. #endif /* OF_CONTROL */
  374. int clk_request(struct udevice *dev, struct clk *clk)
  375. {
  376. const struct clk_ops *ops;
  377. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  378. if (!clk)
  379. return 0;
  380. ops = clk_dev_ops(dev);
  381. clk->dev = dev;
  382. if (!ops->request)
  383. return 0;
  384. return ops->request(clk);
  385. }
  386. int clk_free(struct clk *clk)
  387. {
  388. const struct clk_ops *ops;
  389. debug("%s(clk=%p)\n", __func__, clk);
  390. if (!clk_valid(clk))
  391. return 0;
  392. ops = clk_dev_ops(clk->dev);
  393. if (!ops->rfree)
  394. return 0;
  395. return ops->rfree(clk);
  396. }
  397. ulong clk_get_rate(struct clk *clk)
  398. {
  399. const struct clk_ops *ops;
  400. int ret;
  401. debug("%s(clk=%p)\n", __func__, clk);
  402. if (!clk_valid(clk))
  403. return 0;
  404. ops = clk_dev_ops(clk->dev);
  405. if (!ops->get_rate)
  406. return -ENOSYS;
  407. ret = ops->get_rate(clk);
  408. if (ret)
  409. return log_ret(ret);
  410. return 0;
  411. }
  412. struct clk *clk_get_parent(struct clk *clk)
  413. {
  414. struct udevice *pdev;
  415. struct clk *pclk;
  416. debug("%s(clk=%p)\n", __func__, clk);
  417. if (!clk_valid(clk))
  418. return NULL;
  419. pdev = dev_get_parent(clk->dev);
  420. if (!pdev)
  421. return ERR_PTR(-ENODEV);
  422. pclk = dev_get_clk_ptr(pdev);
  423. if (!pclk)
  424. return ERR_PTR(-ENODEV);
  425. return pclk;
  426. }
  427. long long clk_get_parent_rate(struct clk *clk)
  428. {
  429. const struct clk_ops *ops;
  430. struct clk *pclk;
  431. debug("%s(clk=%p)\n", __func__, clk);
  432. if (!clk_valid(clk))
  433. return 0;
  434. pclk = clk_get_parent(clk);
  435. if (IS_ERR(pclk))
  436. return -ENODEV;
  437. ops = clk_dev_ops(pclk->dev);
  438. if (!ops->get_rate)
  439. return -ENOSYS;
  440. /* Read the 'rate' if not already set or if proper flag set*/
  441. if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
  442. pclk->rate = clk_get_rate(pclk);
  443. return pclk->rate;
  444. }
  445. ulong clk_round_rate(struct clk *clk, ulong rate)
  446. {
  447. const struct clk_ops *ops;
  448. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  449. if (!clk_valid(clk))
  450. return 0;
  451. ops = clk_dev_ops(clk->dev);
  452. if (!ops->round_rate)
  453. return -ENOSYS;
  454. return ops->round_rate(clk, rate);
  455. }
  456. static void clk_clean_rate_cache(struct clk *clk)
  457. {
  458. struct udevice *child_dev;
  459. struct clk *clkp;
  460. if (!clk)
  461. return;
  462. clk->rate = 0;
  463. list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
  464. clkp = dev_get_clk_ptr(child_dev);
  465. clk_clean_rate_cache(clkp);
  466. }
  467. }
  468. ulong clk_set_rate(struct clk *clk, ulong rate)
  469. {
  470. const struct clk_ops *ops;
  471. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  472. if (!clk_valid(clk))
  473. return 0;
  474. ops = clk_dev_ops(clk->dev);
  475. if (!ops->set_rate)
  476. return -ENOSYS;
  477. /* Clean up cached rates for us and all child clocks */
  478. clk_clean_rate_cache(clk);
  479. return ops->set_rate(clk, rate);
  480. }
  481. int clk_set_parent(struct clk *clk, struct clk *parent)
  482. {
  483. const struct clk_ops *ops;
  484. int ret;
  485. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  486. if (!clk_valid(clk))
  487. return 0;
  488. ops = clk_dev_ops(clk->dev);
  489. if (!ops->set_parent)
  490. return -ENOSYS;
  491. ret = ops->set_parent(clk, parent);
  492. if (ret)
  493. return ret;
  494. if (CONFIG_IS_ENABLED(CLK_CCF))
  495. ret = device_reparent(clk->dev, parent->dev);
  496. return ret;
  497. }
  498. int clk_enable(struct clk *clk)
  499. {
  500. const struct clk_ops *ops;
  501. struct clk *clkp = NULL;
  502. int ret;
  503. debug("%s(clk=%p)\n", __func__, clk);
  504. if (!clk_valid(clk))
  505. return 0;
  506. ops = clk_dev_ops(clk->dev);
  507. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  508. /* Take id 0 as a non-valid clk, such as dummy */
  509. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  510. if (clkp->enable_count) {
  511. clkp->enable_count++;
  512. return 0;
  513. }
  514. if (clkp->dev->parent &&
  515. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  516. ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
  517. if (ret) {
  518. printf("Enable %s failed\n",
  519. clkp->dev->parent->name);
  520. return ret;
  521. }
  522. }
  523. }
  524. if (ops->enable) {
  525. ret = ops->enable(clk);
  526. if (ret) {
  527. printf("Enable %s failed\n", clk->dev->name);
  528. return ret;
  529. }
  530. }
  531. if (clkp)
  532. clkp->enable_count++;
  533. } else {
  534. if (!ops->enable)
  535. return -ENOSYS;
  536. return ops->enable(clk);
  537. }
  538. return 0;
  539. }
  540. int clk_enable_bulk(struct clk_bulk *bulk)
  541. {
  542. int i, ret;
  543. for (i = 0; i < bulk->count; i++) {
  544. ret = clk_enable(&bulk->clks[i]);
  545. if (ret < 0 && ret != -ENOSYS)
  546. return ret;
  547. }
  548. return 0;
  549. }
  550. int clk_disable(struct clk *clk)
  551. {
  552. const struct clk_ops *ops;
  553. struct clk *clkp = NULL;
  554. int ret;
  555. debug("%s(clk=%p)\n", __func__, clk);
  556. if (!clk_valid(clk))
  557. return 0;
  558. ops = clk_dev_ops(clk->dev);
  559. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  560. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  561. if (clkp->flags & CLK_IS_CRITICAL)
  562. return 0;
  563. if (clkp->enable_count == 0) {
  564. printf("clk %s already disabled\n",
  565. clkp->dev->name);
  566. return 0;
  567. }
  568. if (--clkp->enable_count > 0)
  569. return 0;
  570. }
  571. if (ops->disable) {
  572. ret = ops->disable(clk);
  573. if (ret)
  574. return ret;
  575. }
  576. if (clkp && clkp->dev->parent &&
  577. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  578. ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
  579. if (ret) {
  580. printf("Disable %s failed\n",
  581. clkp->dev->parent->name);
  582. return ret;
  583. }
  584. }
  585. } else {
  586. if (!ops->disable)
  587. return -ENOSYS;
  588. return ops->disable(clk);
  589. }
  590. return 0;
  591. }
  592. int clk_disable_bulk(struct clk_bulk *bulk)
  593. {
  594. int i, ret;
  595. for (i = 0; i < bulk->count; i++) {
  596. ret = clk_disable(&bulk->clks[i]);
  597. if (ret < 0 && ret != -ENOSYS)
  598. return ret;
  599. }
  600. return 0;
  601. }
  602. int clk_get_by_id(ulong id, struct clk **clkp)
  603. {
  604. struct udevice *dev;
  605. struct uclass *uc;
  606. int ret;
  607. ret = uclass_get(UCLASS_CLK, &uc);
  608. if (ret)
  609. return ret;
  610. uclass_foreach_dev(dev, uc) {
  611. struct clk *clk = dev_get_clk_ptr(dev);
  612. if (clk && clk->id == id) {
  613. *clkp = clk;
  614. return 0;
  615. }
  616. }
  617. return -ENOENT;
  618. }
  619. bool clk_is_match(const struct clk *p, const struct clk *q)
  620. {
  621. /* trivial case: identical struct clk's or both NULL */
  622. if (p == q)
  623. return true;
  624. /* trivial case #2: on the clk pointer is NULL */
  625. if (!p || !q)
  626. return false;
  627. /* same device, id and data */
  628. if (p->dev == q->dev && p->id == q->id && p->data == q->data)
  629. return true;
  630. return false;
  631. }
  632. static void devm_clk_release(struct udevice *dev, void *res)
  633. {
  634. clk_free(res);
  635. }
  636. static int devm_clk_match(struct udevice *dev, void *res, void *data)
  637. {
  638. return res == data;
  639. }
  640. struct clk *devm_clk_get(struct udevice *dev, const char *id)
  641. {
  642. int rc;
  643. struct clk *clk;
  644. clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
  645. if (unlikely(!clk))
  646. return ERR_PTR(-ENOMEM);
  647. rc = clk_get_by_name(dev, id, clk);
  648. if (rc)
  649. return ERR_PTR(rc);
  650. devres_add(dev, clk);
  651. return clk;
  652. }
  653. struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
  654. {
  655. struct clk *clk = devm_clk_get(dev, id);
  656. if (PTR_ERR(clk) == -ENODATA)
  657. return NULL;
  658. return clk;
  659. }
  660. void devm_clk_put(struct udevice *dev, struct clk *clk)
  661. {
  662. int rc;
  663. if (!clk)
  664. return;
  665. rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
  666. WARN_ON(rc);
  667. }
  668. int clk_uclass_post_probe(struct udevice *dev)
  669. {
  670. /*
  671. * when a clock provider is probed. Call clk_set_defaults()
  672. * also after the device is probed. This takes care of cases
  673. * where the DT is used to setup default parents and rates
  674. * using assigned-clocks
  675. */
  676. clk_set_defaults(dev, CLK_DEFAULTS_POST);
  677. return 0;
  678. }
  679. UCLASS_DRIVER(clk) = {
  680. .id = UCLASS_CLK,
  681. .name = "clk",
  682. .post_probe = clk_uclass_post_probe,
  683. };