sromc.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010 Samsung Electronics
  4. * Naveen Krishna Ch <ch.naveen@samsung.com>
  5. *
  6. * Note: This file contains the register description for SROMC
  7. */
  8. #ifndef __ASM_ARCH_SROMC_H_
  9. #define __ASM_ARCH_SROMC_H_
  10. #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
  11. #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
  12. /* 1-> Byte base address*/
  13. #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
  14. #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
  15. #define SROMC_BC_TACS(x) (x << 28) /* address set-up */
  16. #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
  17. #define SROMC_BC_TACC(x) (x << 16) /* access cycle */
  18. #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
  19. #define SROMC_BC_TAH(x) (x << 8) /* address holding time */
  20. #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
  21. #define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
  22. #ifndef __ASSEMBLY__
  23. struct s5p_sromc {
  24. unsigned int bw;
  25. unsigned int bc[4];
  26. };
  27. #endif /* __ASSEMBLY__ */
  28. /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
  29. void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
  30. #endif /* __ASM_ARCH_SROMC_H_ */