config_mpc85xx.h 33 KB

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  1. /*
  2. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _ASM_MPC85xx_CONFIG_H_
  7. #define _ASM_MPC85xx_CONFIG_H_
  8. /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
  9. #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
  10. #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
  11. #endif
  12. /*
  13. * This macro should be removed when we no longer care about backwards
  14. * compatibility with older operating systems.
  15. */
  16. #define CONFIG_PPC_SPINTABLE_COMPATIBLE
  17. #include <fsl_ddrc_version.h>
  18. #define CONFIG_SYS_FSL_DDR_BE
  19. /* IP endianness */
  20. #define CONFIG_SYS_FSL_IFC_BE
  21. #define CONFIG_SYS_FSL_SEC_BE
  22. /* Number of TLB CAM entries we have on FSL Book-E chips */
  23. #if defined(CONFIG_E500MC)
  24. #define CONFIG_SYS_NUM_TLBCAMS 64
  25. #elif defined(CONFIG_E500)
  26. #define CONFIG_SYS_NUM_TLBCAMS 16
  27. #endif
  28. #if defined(CONFIG_MPC8536)
  29. #define CONFIG_MAX_CPUS 1
  30. #define CONFIG_SYS_FSL_NUM_LAWS 12
  31. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
  32. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  33. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  34. #define CONFIG_SYS_FSL_ERRATUM_A004508
  35. #define CONFIG_SYS_FSL_ERRATUM_A005125
  36. #elif defined(CONFIG_MPC8540)
  37. #define CONFIG_MAX_CPUS 1
  38. #define CONFIG_SYS_FSL_NUM_LAWS 8
  39. #define CONFIG_SYS_FSL_DDRC_GEN1
  40. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  41. #elif defined(CONFIG_MPC8541)
  42. #define CONFIG_MAX_CPUS 1
  43. #define CONFIG_SYS_FSL_NUM_LAWS 8
  44. #define CONFIG_SYS_FSL_DDRC_GEN1
  45. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  46. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  47. #elif defined(CONFIG_MPC8544)
  48. #define CONFIG_MAX_CPUS 1
  49. #define CONFIG_SYS_FSL_NUM_LAWS 10
  50. #define CONFIG_SYS_FSL_DDRC_GEN2
  51. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  52. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  53. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  54. #define CONFIG_SYS_FSL_ERRATUM_A005125
  55. #elif defined(CONFIG_MPC8548)
  56. #define CONFIG_MAX_CPUS 1
  57. #define CONFIG_SYS_FSL_NUM_LAWS 10
  58. #define CONFIG_SYS_FSL_DDRC_GEN2
  59. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  60. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  61. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  62. #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  63. #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  64. #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  65. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  66. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  67. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  68. #define CONFIG_SYS_FSL_RMU
  69. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  70. #define CONFIG_SYS_FSL_ERRATUM_A005125
  71. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  72. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
  73. #elif defined(CONFIG_MPC8555)
  74. #define CONFIG_MAX_CPUS 1
  75. #define CONFIG_SYS_FSL_NUM_LAWS 8
  76. #define CONFIG_SYS_FSL_DDRC_GEN1
  77. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  78. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  79. #elif defined(CONFIG_MPC8560)
  80. #define CONFIG_MAX_CPUS 1
  81. #define CONFIG_SYS_FSL_NUM_LAWS 8
  82. #define CONFIG_SYS_FSL_DDRC_GEN1
  83. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  84. #elif defined(CONFIG_MPC8568)
  85. #define CONFIG_MAX_CPUS 1
  86. #define CONFIG_SYS_FSL_NUM_LAWS 10
  87. #define CONFIG_SYS_FSL_DDRC_GEN2
  88. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  89. #define QE_MURAM_SIZE 0x10000UL
  90. #define MAX_QE_RISC 2
  91. #define QE_NUM_OF_SNUM 28
  92. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  93. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  94. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  95. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  96. #define CONFIG_SYS_FSL_RMU
  97. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  98. #elif defined(CONFIG_MPC8569)
  99. #define CONFIG_MAX_CPUS 1
  100. #define CONFIG_SYS_FSL_NUM_LAWS 10
  101. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  102. #define QE_MURAM_SIZE 0x20000UL
  103. #define MAX_QE_RISC 4
  104. #define QE_NUM_OF_SNUM 46
  105. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  106. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  107. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  108. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  109. #define CONFIG_SYS_FSL_RMU
  110. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  111. #define CONFIG_SYS_FSL_ERRATUM_A004508
  112. #define CONFIG_SYS_FSL_ERRATUM_A005125
  113. #elif defined(CONFIG_MPC8572)
  114. #define CONFIG_MAX_CPUS 2
  115. #define CONFIG_SYS_FSL_NUM_LAWS 12
  116. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  117. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  118. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  119. #define CONFIG_SYS_FSL_ERRATUM_DDR_115
  120. #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  121. #define CONFIG_SYS_FSL_ERRATUM_A004508
  122. #define CONFIG_SYS_FSL_ERRATUM_A005125
  123. #elif defined(CONFIG_P1010)
  124. #define CONFIG_MAX_CPUS 1
  125. #define CONFIG_FSL_SDHC_V2_3
  126. #define CONFIG_SYS_FSL_NUM_LAWS 12
  127. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  128. #define CONFIG_TSECV2
  129. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  130. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  131. #define CONFIG_NUM_DDR_CONTROLLERS 1
  132. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  133. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  134. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  135. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  136. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  137. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  138. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  139. #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  140. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  141. #define CONFIG_SYS_FSL_ERRATUM_A005125
  142. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  143. #define CONFIG_SYS_FSL_ERRATUM_A004508
  144. #define CONFIG_SYS_FSL_ERRATUM_A007075
  145. #define CONFIG_SYS_FSL_ERRATUM_A006261
  146. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
  147. #define CONFIG_ESDHC_HC_BLK_ADDR
  148. /* P1011 is single core version of P1020 */
  149. #elif defined(CONFIG_P1011)
  150. #define CONFIG_MAX_CPUS 1
  151. #define CONFIG_SYS_FSL_NUM_LAWS 12
  152. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  153. #define CONFIG_TSECV2
  154. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  155. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  156. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  157. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  158. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  159. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  160. #define CONFIG_SYS_FSL_ERRATUM_A004508
  161. #define CONFIG_SYS_FSL_ERRATUM_A005125
  162. /* P1012 is single core version of P1021 */
  163. #elif defined(CONFIG_P1012)
  164. #define CONFIG_MAX_CPUS 1
  165. #define CONFIG_SYS_FSL_NUM_LAWS 12
  166. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  167. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  168. #define CONFIG_TSECV2
  169. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  170. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  171. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  172. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  173. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  174. #define QE_MURAM_SIZE 0x6000UL
  175. #define MAX_QE_RISC 1
  176. #define QE_NUM_OF_SNUM 28
  177. #define CONFIG_SYS_FSL_ERRATUM_A004508
  178. #define CONFIG_SYS_FSL_ERRATUM_A005125
  179. /* P1013 is single core version of P1022 */
  180. #elif defined(CONFIG_P1013)
  181. #define CONFIG_MAX_CPUS 1
  182. #define CONFIG_SYS_FSL_NUM_LAWS 12
  183. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  184. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  185. #define CONFIG_TSECV2
  186. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  187. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  188. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  189. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  190. #define CONFIG_FSL_SATA_ERRATUM_A001
  191. #define CONFIG_SYS_FSL_ERRATUM_A004508
  192. #define CONFIG_SYS_FSL_ERRATUM_A005125
  193. #elif defined(CONFIG_P1014)
  194. #define CONFIG_MAX_CPUS 1
  195. #define CONFIG_FSL_SDHC_V2_3
  196. #define CONFIG_SYS_FSL_NUM_LAWS 12
  197. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  198. #define CONFIG_TSECV2
  199. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  200. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  201. #define CONFIG_NUM_DDR_CONTROLLERS 1
  202. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  203. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  204. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  205. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  206. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  207. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  208. #define CONFIG_SYS_FSL_ERRATUM_A004508
  209. /* P1017 is single core version of P1023 */
  210. #elif defined(CONFIG_P1017)
  211. #define CONFIG_MAX_CPUS 1
  212. #define CONFIG_SYS_FSL_NUM_LAWS 12
  213. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  214. #define CONFIG_SYS_NUM_FMAN 1
  215. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  216. #define CONFIG_NUM_DDR_CONTROLLERS 1
  217. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  218. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  219. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  220. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  221. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  222. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
  223. #define CONFIG_SYS_FSL_ERRATUM_A004508
  224. #define CONFIG_SYS_FSL_ERRATUM_A005125
  225. #elif defined(CONFIG_P1020)
  226. #define CONFIG_MAX_CPUS 2
  227. #define CONFIG_SYS_FSL_NUM_LAWS 12
  228. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  229. #define CONFIG_TSECV2
  230. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  231. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  232. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  233. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  234. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  235. #define CONFIG_SYS_FSL_ERRATUM_A004508
  236. #define CONFIG_SYS_FSL_ERRATUM_A005125
  237. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  238. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  239. #endif
  240. #elif defined(CONFIG_P1021)
  241. #define CONFIG_MAX_CPUS 2
  242. #define CONFIG_SYS_FSL_NUM_LAWS 12
  243. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  244. #define CONFIG_TSECV2
  245. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  246. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  247. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  248. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  249. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  250. #define QE_MURAM_SIZE 0x6000UL
  251. #define MAX_QE_RISC 1
  252. #define QE_NUM_OF_SNUM 28
  253. #define CONFIG_SYS_FSL_ERRATUM_A004508
  254. #define CONFIG_SYS_FSL_ERRATUM_A005125
  255. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  256. #elif defined(CONFIG_P1022)
  257. #define CONFIG_MAX_CPUS 2
  258. #define CONFIG_SYS_FSL_NUM_LAWS 12
  259. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  260. #define CONFIG_TSECV2
  261. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  262. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  263. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  264. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  265. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  266. #define CONFIG_FSL_SATA_ERRATUM_A001
  267. #define CONFIG_SYS_FSL_ERRATUM_A004508
  268. #define CONFIG_SYS_FSL_ERRATUM_A005125
  269. #elif defined(CONFIG_P1023)
  270. #define CONFIG_MAX_CPUS 2
  271. #define CONFIG_SYS_FSL_NUM_LAWS 12
  272. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  273. #define CONFIG_SYS_NUM_FMAN 1
  274. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  275. #define CONFIG_NUM_DDR_CONTROLLERS 1
  276. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  277. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  278. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  279. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  280. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  281. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
  282. #define CONFIG_SYS_FSL_ERRATUM_A004508
  283. #define CONFIG_SYS_FSL_ERRATUM_A005125
  284. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  285. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  286. /* P1024 is lower end variant of P1020 */
  287. #elif defined(CONFIG_P1024)
  288. #define CONFIG_MAX_CPUS 2
  289. #define CONFIG_SYS_FSL_NUM_LAWS 12
  290. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  291. #define CONFIG_TSECV2
  292. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  293. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  294. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  295. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  296. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  297. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  298. #define CONFIG_SYS_FSL_ERRATUM_A004508
  299. #define CONFIG_SYS_FSL_ERRATUM_A005125
  300. /* P1025 is lower end variant of P1021 */
  301. #elif defined(CONFIG_P1025)
  302. #define CONFIG_MAX_CPUS 2
  303. #define CONFIG_SYS_FSL_NUM_LAWS 12
  304. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  305. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  306. #define CONFIG_TSECV2
  307. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  308. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  309. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  310. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  311. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  312. #define QE_MURAM_SIZE 0x6000UL
  313. #define MAX_QE_RISC 1
  314. #define QE_NUM_OF_SNUM 28
  315. #define CONFIG_SYS_FSL_ERRATUM_A004508
  316. #define CONFIG_SYS_FSL_ERRATUM_A005125
  317. /* P2010 is single core version of P2020 */
  318. #elif defined(CONFIG_P2010)
  319. #define CONFIG_MAX_CPUS 1
  320. #define CONFIG_SYS_FSL_NUM_LAWS 12
  321. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  322. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  323. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  324. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  325. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  326. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  327. #define CONFIG_SYS_FSL_ERRATUM_A004508
  328. #define CONFIG_SYS_FSL_ERRATUM_A005125
  329. #elif defined(CONFIG_P2020)
  330. #define CONFIG_MAX_CPUS 2
  331. #define CONFIG_SYS_FSL_NUM_LAWS 12
  332. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  333. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  334. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  335. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  336. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  337. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  338. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  339. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  340. #define CONFIG_SYS_FSL_RMU
  341. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  342. #define CONFIG_SYS_FSL_ERRATUM_A004508
  343. #define CONFIG_SYS_FSL_ERRATUM_A005125
  344. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  345. #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
  346. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  347. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  348. #define CONFIG_MAX_CPUS 4
  349. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  350. #define CONFIG_SYS_FSL_NUM_LAWS 32
  351. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  352. #define CONFIG_SYS_NUM_FMAN 1
  353. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  354. #define CONFIG_SYS_NUM_FM1_10GEC 1
  355. #define CONFIG_NUM_DDR_CONTROLLERS 1
  356. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  357. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  358. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  359. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  360. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  361. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  362. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  363. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  364. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  365. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  366. #define CONFIG_SYS_FSL_ERRATUM_USB14
  367. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  368. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  369. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  370. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  371. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  372. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  373. #define CONFIG_SYS_FSL_ERRATUM_A004510
  374. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  375. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  376. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  377. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  378. #define CONFIG_SYS_FSL_ERRATUM_A004849
  379. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  380. #define CONFIG_SYS_FSL_ERRATUM_A006261
  381. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  382. #elif defined(CONFIG_PPC_P3041)
  383. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  384. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  385. #define CONFIG_MAX_CPUS 4
  386. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  387. #define CONFIG_SYS_FSL_NUM_LAWS 32
  388. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  389. #define CONFIG_SYS_NUM_FMAN 1
  390. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  391. #define CONFIG_SYS_NUM_FM1_10GEC 1
  392. #define CONFIG_NUM_DDR_CONTROLLERS 1
  393. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
  394. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  395. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  396. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  397. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  398. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  399. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  400. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  401. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  402. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  403. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  404. #define CONFIG_SYS_FSL_ERRATUM_USB14
  405. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  406. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  407. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  408. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  409. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  410. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  411. #define CONFIG_SYS_FSL_ERRATUM_A004510
  412. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  413. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  414. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  415. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  416. #define CONFIG_SYS_FSL_ERRATUM_A004849
  417. #define CONFIG_SYS_FSL_ERRATUM_A005812
  418. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  419. #define CONFIG_SYS_FSL_ERRATUM_A006261
  420. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  421. #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
  422. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  423. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  424. #define CONFIG_MAX_CPUS 8
  425. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  426. #define CONFIG_SYS_FSL_NUM_LAWS 32
  427. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  428. #define CONFIG_SYS_NUM_FMAN 2
  429. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  430. #define CONFIG_SYS_NUM_FM2_DTSEC 4
  431. #define CONFIG_SYS_NUM_FM1_10GEC 1
  432. #define CONFIG_SYS_NUM_FM2_10GEC 1
  433. #define CONFIG_NUM_DDR_CONTROLLERS 2
  434. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  435. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  436. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  437. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  438. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  439. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  440. #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
  441. #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
  442. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  443. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  444. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  445. #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
  446. #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
  447. #define CONFIG_SYS_P4080_ERRATUM_CPU22
  448. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  449. #define CONFIG_SYS_P4080_ERRATUM_SERDES8
  450. #define CONFIG_SYS_P4080_ERRATUM_SERDES9
  451. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  452. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  453. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  454. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  455. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  456. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  457. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  458. #define CONFIG_SYS_FSL_RMU
  459. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  460. #define CONFIG_SYS_FSL_ERRATUM_A004510
  461. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
  462. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
  463. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  464. #define CONFIG_SYS_FSL_ERRATUM_A004849
  465. #define CONFIG_SYS_FSL_ERRATUM_A004580
  466. #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  467. #define CONFIG_SYS_FSL_ERRATUM_A005812
  468. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  469. #define CONFIG_SYS_FSL_ERRATUM_A007075
  470. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  471. #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
  472. #define CONFIG_SYS_PPC64 /* 64-bit core */
  473. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  474. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  475. #define CONFIG_MAX_CPUS 2
  476. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  477. #define CONFIG_SYS_FSL_NUM_LAWS 32
  478. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  479. #define CONFIG_SYS_NUM_FMAN 1
  480. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  481. #define CONFIG_SYS_NUM_FM1_10GEC 1
  482. #define CONFIG_NUM_DDR_CONTROLLERS 2
  483. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  484. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  485. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  486. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  487. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  488. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  489. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  490. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  491. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  492. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  493. #define CONFIG_SYS_FSL_ERRATUM_USB14
  494. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  495. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  496. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  497. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  498. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  499. #define CONFIG_SYS_FSL_ERRATUM_A004510
  500. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  501. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
  502. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  503. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  504. #define CONFIG_SYS_FSL_ERRATUM_A006261
  505. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  506. #elif defined(CONFIG_PPC_P5040)
  507. #define CONFIG_SYS_PPC64
  508. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  509. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  510. #define CONFIG_MAX_CPUS 4
  511. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  512. #define CONFIG_SYS_FSL_NUM_LAWS 32
  513. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  514. #define CONFIG_SYS_NUM_FMAN 2
  515. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  516. #define CONFIG_SYS_NUM_FM1_10GEC 1
  517. #define CONFIG_SYS_NUM_FM2_DTSEC 5
  518. #define CONFIG_SYS_NUM_FM2_10GEC 1
  519. #define CONFIG_NUM_DDR_CONTROLLERS 2
  520. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  521. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  522. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  523. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  524. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  525. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  526. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  527. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  528. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  529. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  530. #define CONFIG_SYS_FSL_ERRATUM_USB14
  531. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  532. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  533. #define CONFIG_SYS_FSL_ERRATUM_A004699
  534. #define CONFIG_SYS_FSL_ERRATUM_A004510
  535. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  536. #define CONFIG_SYS_FSL_ERRATUM_A006261
  537. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  538. #define CONFIG_SYS_FSL_ERRATUM_A005812
  539. #elif defined(CONFIG_BSC9131)
  540. #define CONFIG_MAX_CPUS 1
  541. #define CONFIG_FSL_SDHC_V2_3
  542. #define CONFIG_SYS_FSL_NUM_LAWS 12
  543. #define CONFIG_TSECV2
  544. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  545. #define CONFIG_NUM_DDR_CONTROLLERS 1
  546. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  547. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  548. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  549. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  550. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  551. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  552. #define CONFIG_NAND_FSL_IFC
  553. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  554. #define CONFIG_SYS_FSL_ERRATUM_A005125
  555. #define CONFIG_ESDHC_HC_BLK_ADDR
  556. #elif defined(CONFIG_BSC9132)
  557. #define CONFIG_MAX_CPUS 2
  558. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  559. #define CONFIG_FSL_SDHC_V2_3
  560. #define CONFIG_SYS_FSL_NUM_LAWS 12
  561. #define CONFIG_TSECV2
  562. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  563. #define CONFIG_NUM_DDR_CONTROLLERS 2
  564. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  565. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  566. #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
  567. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  568. #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
  569. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  570. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  571. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  572. #define CONFIG_NAND_FSL_IFC
  573. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  574. #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
  575. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  576. #define CONFIG_SYS_FSL_ERRATUM_A005125
  577. #define CONFIG_SYS_FSL_ERRATUM_A005434
  578. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  579. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  580. #define CONFIG_ESDHC_HC_BLK_ADDR
  581. #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  582. defined(CONFIG_PPC_T4080)
  583. #define CONFIG_E6500
  584. #define CONFIG_SYS_PPC64 /* 64-bit core */
  585. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  586. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  587. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  588. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  589. #ifdef CONFIG_PPC_T4240
  590. #define CONFIG_MAX_CPUS 12
  591. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
  592. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  593. #define CONFIG_SYS_NUM_FM1_10GEC 2
  594. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  595. #define CONFIG_SYS_NUM_FM2_10GEC 2
  596. #define CONFIG_NUM_DDR_CONTROLLERS 3
  597. #else
  598. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  599. #define CONFIG_SYS_NUM_FM1_10GEC 1
  600. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  601. #define CONFIG_SYS_NUM_FM2_10GEC 1
  602. #define CONFIG_NUM_DDR_CONTROLLERS 2
  603. #if defined(CONFIG_PPC_T4160)
  604. #define CONFIG_MAX_CPUS 8
  605. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  606. #elif defined(CONFIG_PPC_T4080)
  607. #define CONFIG_MAX_CPUS 4
  608. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
  609. #endif
  610. #endif
  611. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  612. #define CONFIG_SYS_FSL_NUM_LAWS 32
  613. #define CONFIG_SYS_FSL_SRDS_1
  614. #define CONFIG_SYS_FSL_SRDS_2
  615. #define CONFIG_SYS_FSL_SRDS_3
  616. #define CONFIG_SYS_FSL_SRDS_4
  617. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  618. #define CONFIG_SYS_NUM_FMAN 2
  619. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  620. #define CONFIG_SYS_PME_CLK 0
  621. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  622. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  623. #define CONFIG_SYS_FMAN_V3
  624. #define CONFIG_SYS_FM1_CLK 3
  625. #define CONFIG_SYS_FM2_CLK 3
  626. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  627. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  628. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  629. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  630. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  631. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  632. #define CONFIG_SYS_FSL_SRIO_LIODN
  633. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  634. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  635. #define CONFIG_SYS_FSL_ERRATUM_A004468
  636. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  637. #define CONFIG_SYS_FSL_ERRATUM_A005871
  638. #define CONFIG_SYS_FSL_ERRATUM_A006261
  639. #define CONFIG_SYS_FSL_ERRATUM_A006379
  640. #define CONFIG_SYS_FSL_ERRATUM_A007186
  641. #define CONFIG_SYS_FSL_ERRATUM_A006593
  642. #define CONFIG_SYS_FSL_ERRATUM_A007798
  643. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  644. #define CONFIG_SYS_FSL_SFP_VER_3_0
  645. #define CONFIG_SYS_FSL_PCI_VER_3_X
  646. #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
  647. #define CONFIG_E6500
  648. #define CONFIG_SYS_PPC64 /* 64-bit core */
  649. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  650. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  651. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  652. #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
  653. #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
  654. #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
  655. #define CONFIG_SYS_FSL_NUM_LAWS 32
  656. #define CONFIG_SYS_FSL_SRDS_1
  657. #define CONFIG_SYS_FSL_SRDS_2
  658. #define CONFIG_SYS_MAPLE
  659. #define CONFIG_SYS_CPRI
  660. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  661. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  662. #define CONFIG_SYS_NUM_FMAN 1
  663. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  664. #define CONFIG_SYS_FM1_CLK 0
  665. #define CONFIG_SYS_CPRI_CLK 3
  666. #define CONFIG_SYS_ULB_CLK 4
  667. #define CONFIG_SYS_ETVPE_CLK 1
  668. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  669. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  670. #define CONFIG_SYS_FMAN_V3
  671. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  672. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  673. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  674. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  675. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  676. #define CONFIG_SYS_FSL_ERRATUM_A005871
  677. #define CONFIG_SYS_FSL_ERRATUM_A006379
  678. #define CONFIG_SYS_FSL_ERRATUM_A007186
  679. #define CONFIG_SYS_FSL_ERRATUM_A006593
  680. #define CONFIG_SYS_FSL_ERRATUM_A007075
  681. #define CONFIG_SYS_FSL_ERRATUM_A006475
  682. #define CONFIG_SYS_FSL_ERRATUM_A006384
  683. #define CONFIG_SYS_FSL_ERRATUM_A007212
  684. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  685. #define CONFIG_SYS_FSL_SFP_VER_3_0
  686. #ifdef CONFIG_PPC_B4860
  687. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  688. #define CONFIG_MAX_CPUS 4
  689. #define CONFIG_MAX_DSP_CPUS 12
  690. #define CONFIG_NUM_DSP_CPUS 6
  691. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
  692. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  693. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  694. #define CONFIG_SYS_NUM_FM1_10GEC 2
  695. #define CONFIG_NUM_DDR_CONTROLLERS 2
  696. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  697. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  698. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  699. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  700. #define CONFIG_SYS_FSL_SRIO_LIODN
  701. #else
  702. #define CONFIG_MAX_CPUS 2
  703. #define CONFIG_MAX_DSP_CPUS 2
  704. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
  705. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
  706. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
  707. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  708. #define CONFIG_SYS_NUM_FM1_10GEC 0
  709. #define CONFIG_NUM_DDR_CONTROLLERS 1
  710. #endif
  711. #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
  712. defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
  713. #define CONFIG_E5500
  714. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  715. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  716. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  717. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  718. #ifdef CONFIG_SYS_FSL_DDR4
  719. #define CONFIG_SYS_FSL_DDRC_GEN4
  720. #endif
  721. #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
  722. #define CONFIG_MAX_CPUS 4
  723. #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
  724. #define CONFIG_MAX_CPUS 2
  725. #endif
  726. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  727. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  728. #define CONFIG_SYS_SDHC_CLOCK 0
  729. #define CONFIG_SYS_FSL_NUM_LAWS 16
  730. #define CONFIG_SYS_FSL_SRDS_1
  731. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  732. #define CONFIG_SYS_NUM_FMAN 1
  733. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  734. #define CONFIG_NUM_DDR_CONTROLLERS 1
  735. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  736. #define CONFIG_PME_PLAT_CLK_DIV 2
  737. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  738. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  739. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  740. #define CONFIG_SYS_FSL_ERRATUM_A008044
  741. #define CONFIG_SYS_FMAN_V3
  742. #define CONFIG_FM_PLAT_CLK_DIV 1
  743. #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
  744. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  745. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  746. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  747. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  748. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  749. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  750. #define CONFIG_SYS_FSL_ERRATUM_A006261
  751. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  752. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  753. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  754. #define QE_MURAM_SIZE 0x6000UL
  755. #define MAX_QE_RISC 1
  756. #define QE_NUM_OF_SNUM 28
  757. #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
  758. defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
  759. #define CONFIG_E5500
  760. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  761. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  762. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  763. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  764. #define CONFIG_SYS_FMAN_V3
  765. #ifdef CONFIG_SYS_FSL_DDR4
  766. #define CONFIG_SYS_FSL_DDRC_GEN4
  767. #endif
  768. #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
  769. #define CONFIG_MAX_CPUS 2
  770. #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
  771. #define CONFIG_MAX_CPUS 1
  772. #endif
  773. #define CONFIG_SYS_FSL_NUM_CC_PLL 2
  774. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  775. #define CONFIG_SYS_SDHC_CLOCK 0
  776. #define CONFIG_SYS_FSL_NUM_LAWS 16
  777. #define CONFIG_SYS_FSL_SRDS_1
  778. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  779. #define CONFIG_SYS_NUM_FMAN 1
  780. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  781. #define CONFIG_SYS_NUM_FM1_10GEC 1
  782. #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  783. #define CONFIG_NUM_DDR_CONTROLLERS 1
  784. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  785. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  786. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  787. #define CONFIG_SYS_FM1_CLK 0
  788. #define CONFIG_QBMAN_CLK_DIV 1
  789. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  790. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  791. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  792. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  793. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  794. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  795. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  796. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  797. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  798. #define QE_MURAM_SIZE 0x6000UL
  799. #define MAX_QE_RISC 1
  800. #define QE_NUM_OF_SNUM 28
  801. #define CONFIG_SYS_FSL_SFP_VER_3_0
  802. #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
  803. #define CONFIG_E6500
  804. #define CONFIG_SYS_PPC64 /* 64-bit core */
  805. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  806. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  807. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  808. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  809. #define CONFIG_SYS_FSL_QMAN_V3
  810. #define CONFIG_MAX_CPUS 4
  811. #define CONFIG_SYS_FSL_NUM_LAWS 32
  812. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  813. #define CONFIG_SYS_NUM_FMAN 1
  814. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  815. #define CONFIG_SYS_FSL_SRDS_1
  816. #define CONFIG_SYS_FSL_PCI_VER_3_X
  817. #if defined(CONFIG_PPC_T2080)
  818. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  819. #define CONFIG_SYS_NUM_FM1_10GEC 4
  820. #define CONFIG_SYS_FSL_SRDS_2
  821. #define CONFIG_SYS_FSL_SRIO_LIODN
  822. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  823. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  824. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  825. #elif defined(CONFIG_PPC_T2081)
  826. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  827. #define CONFIG_SYS_NUM_FM1_10GEC 2
  828. #endif
  829. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  830. #define CONFIG_NUM_DDR_CONTROLLERS 1
  831. #define CONFIG_PME_PLAT_CLK_DIV 1
  832. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  833. #define CONFIG_SYS_FM1_CLK 0
  834. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  835. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  836. #define CONFIG_SYS_FMAN_V3
  837. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  838. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  839. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  840. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  841. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  842. #define CONFIG_SYS_FSL_ERRATUM_A007212
  843. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  844. #define CONFIG_SYS_FSL_SFP_VER_3_0
  845. #define CONFIG_SYS_FSL_ISBC_VER 2
  846. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  847. #define CONFIG_SYS_FSL_ERRATUM_A006261
  848. #define CONFIG_SYS_FSL_ERRATUM_A006593
  849. #define CONFIG_SYS_FSL_ERRATUM_A007186
  850. #define CONFIG_SYS_FSL_ERRATUM_A006379
  851. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  852. #define CONFIG_SYS_FSL_SFP_VER_3_0
  853. #elif defined(CONFIG_PPC_C29X)
  854. #define CONFIG_MAX_CPUS 1
  855. #define CONFIG_FSL_SDHC_V2_3
  856. #define CONFIG_SYS_FSL_NUM_LAWS 12
  857. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  858. #define CONFIG_TSECV2_1
  859. #define CONFIG_SYS_FSL_SEC_COMPAT 6
  860. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  861. #define CONFIG_NUM_DDR_CONTROLLERS 1
  862. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  863. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  864. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  865. #define CONFIG_SYS_FSL_ERRATUM_A005125
  866. #elif defined(CONFIG_QEMU_E500)
  867. #define CONFIG_MAX_CPUS 1
  868. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
  869. #else
  870. #error Processor type not defined for this platform
  871. #endif
  872. #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
  873. #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
  874. #endif
  875. #ifdef CONFIG_E6500
  876. #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
  877. #else
  878. #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
  879. #endif
  880. #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
  881. !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
  882. !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
  883. !defined(CONFIG_SYS_FSL_DDRC_GEN4)
  884. #define CONFIG_SYS_FSL_DDRC_GEN3
  885. #endif
  886. #endif /* _ASM_MPC85xx_CONFIG_H_ */