speed.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699
  1. /*
  2. * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  3. *
  4. * (C) Copyright 2003 Motorola Inc.
  5. * Xianghua Xiao, (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <ppc_asm.tmpl>
  14. #include <linux/compiler.h>
  15. #include <asm/processor.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  19. #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
  20. #endif
  21. /* --------------------------------------------------------------- */
  22. void get_sys_info(sys_info_t *sys_info)
  23. {
  24. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  25. #ifdef CONFIG_FSL_IFC
  26. struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
  27. u32 ccr;
  28. #endif
  29. #ifdef CONFIG_FSL_CORENET
  30. volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  31. unsigned int cpu;
  32. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  33. unsigned int dsp_cpu;
  34. uint rcw_tmp1, rcw_tmp2;
  35. #endif
  36. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  37. int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  38. #endif
  39. __maybe_unused u32 svr;
  40. const u8 core_cplx_PLL[16] = {
  41. [ 0] = 0, /* CC1 PPL / 1 */
  42. [ 1] = 0, /* CC1 PPL / 2 */
  43. [ 2] = 0, /* CC1 PPL / 4 */
  44. [ 4] = 1, /* CC2 PPL / 1 */
  45. [ 5] = 1, /* CC2 PPL / 2 */
  46. [ 6] = 1, /* CC2 PPL / 4 */
  47. [ 8] = 2, /* CC3 PPL / 1 */
  48. [ 9] = 2, /* CC3 PPL / 2 */
  49. [10] = 2, /* CC3 PPL / 4 */
  50. [12] = 3, /* CC4 PPL / 1 */
  51. [13] = 3, /* CC4 PPL / 2 */
  52. [14] = 3, /* CC4 PPL / 4 */
  53. };
  54. const u8 core_cplx_pll_div[16] = {
  55. [ 0] = 1, /* CC1 PPL / 1 */
  56. [ 1] = 2, /* CC1 PPL / 2 */
  57. [ 2] = 4, /* CC1 PPL / 4 */
  58. [ 4] = 1, /* CC2 PPL / 1 */
  59. [ 5] = 2, /* CC2 PPL / 2 */
  60. [ 6] = 4, /* CC2 PPL / 4 */
  61. [ 8] = 1, /* CC3 PPL / 1 */
  62. [ 9] = 2, /* CC3 PPL / 2 */
  63. [10] = 4, /* CC3 PPL / 4 */
  64. [12] = 1, /* CC4 PPL / 1 */
  65. [13] = 2, /* CC4 PPL / 2 */
  66. [14] = 4, /* CC4 PPL / 4 */
  67. };
  68. uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  69. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  70. uint rcw_tmp;
  71. #endif
  72. uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  73. unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  74. uint mem_pll_rat;
  75. sys_info->freq_systembus = sysclk;
  76. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  77. uint ddr_refclk_sel;
  78. unsigned int porsr1_sys_clk;
  79. porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
  80. & FSL_DCFG_PORSR1_SYSCLK_MASK;
  81. if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
  82. sys_info->diff_sysclk = 1;
  83. else
  84. sys_info->diff_sysclk = 0;
  85. /*
  86. * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
  87. * are driven by separate DDR Refclock or single source
  88. * differential clock.
  89. */
  90. ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
  91. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
  92. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
  93. /*
  94. * For single source clocking, both ddrclock and sysclock
  95. * are driven by differential sysclock.
  96. */
  97. if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
  98. sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
  99. else
  100. #endif
  101. #ifdef CONFIG_DDR_CLK_FREQ
  102. sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  103. #else
  104. sys_info->freq_ddrbus = sysclk;
  105. #endif
  106. sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  107. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  108. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
  109. & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  110. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  111. if (mem_pll_rat == 0) {
  112. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  113. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  114. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  115. }
  116. #endif
  117. /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
  118. * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
  119. * it uses 6.
  120. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
  121. */
  122. #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  123. defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
  124. svr = get_svr();
  125. switch (SVR_SOC_VER(svr)) {
  126. case SVR_T4240:
  127. case SVR_T4160:
  128. case SVR_T4120:
  129. case SVR_T4080:
  130. if (SVR_MAJ(svr) >= 2)
  131. mem_pll_rat *= 2;
  132. break;
  133. case SVR_T2080:
  134. case SVR_T2081:
  135. if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
  136. mem_pll_rat *= 2;
  137. break;
  138. default:
  139. break;
  140. }
  141. #endif
  142. if (mem_pll_rat > 2)
  143. sys_info->freq_ddrbus *= mem_pll_rat;
  144. else
  145. sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
  146. for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  147. ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
  148. if (ratio[i] > 4)
  149. freq_c_pll[i] = sysclk * ratio[i];
  150. else
  151. freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
  152. }
  153. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  154. /*
  155. * As per CHASSIS2 architeture total 12 clusters are posible and
  156. * Each cluster has up to 4 cores, sharing the same PLL selection.
  157. * The cluster clock assignment is SoC defined.
  158. *
  159. * Total 4 clock groups are possible with 3 PLLs each.
  160. * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
  161. * clock group B has 3, 4, 6 and so on.
  162. *
  163. * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
  164. * depends upon the SoC architeture. Same applies to other
  165. * clock groups and clusters.
  166. *
  167. */
  168. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  169. int cluster = fsl_qoriq_core_to_cluster(cpu);
  170. u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
  171. & 0xf;
  172. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  173. cplx_pll += cc_group[cluster] - 1;
  174. sys_info->freq_processor[cpu] =
  175. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  176. }
  177. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  178. for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
  179. int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
  180. u32 c_pll_sel = (in_be32
  181. (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
  182. & 0xf;
  183. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  184. cplx_pll += cc_group[dsp_cluster] - 1;
  185. sys_info->freq_processor_dsp[dsp_cpu] =
  186. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  187. }
  188. #endif
  189. #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
  190. defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
  191. #define FM1_CLK_SEL 0xe0000000
  192. #define FM1_CLK_SHIFT 29
  193. #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
  194. #define FM1_CLK_SEL 0x00000007
  195. #define FM1_CLK_SHIFT 0
  196. #else
  197. #define PME_CLK_SEL 0xe0000000
  198. #define PME_CLK_SHIFT 29
  199. #define FM1_CLK_SEL 0x1c000000
  200. #define FM1_CLK_SHIFT 26
  201. #endif
  202. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  203. #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
  204. rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
  205. #else
  206. rcw_tmp = in_be32(&gur->rcwsr[7]);
  207. #endif
  208. #endif
  209. #ifdef CONFIG_SYS_DPAA_PME
  210. #ifndef CONFIG_PME_PLAT_CLK_DIV
  211. switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
  212. case 1:
  213. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
  214. break;
  215. case 2:
  216. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
  217. break;
  218. case 3:
  219. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
  220. break;
  221. case 4:
  222. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
  223. break;
  224. case 6:
  225. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
  226. break;
  227. case 7:
  228. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
  229. break;
  230. default:
  231. printf("Error: Unknown PME clock select!\n");
  232. case 0:
  233. sys_info->freq_pme = sys_info->freq_systembus / 2;
  234. break;
  235. }
  236. #else
  237. sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
  238. #endif
  239. #endif
  240. #ifdef CONFIG_SYS_DPAA_QBMAN
  241. #ifndef CONFIG_QBMAN_CLK_DIV
  242. #define CONFIG_QBMAN_CLK_DIV 2
  243. #endif
  244. sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
  245. #endif
  246. #if defined(CONFIG_SYS_MAPLE)
  247. #define CPRI_CLK_SEL 0x1C000000
  248. #define CPRI_CLK_SHIFT 26
  249. #define CPRI_ALT_CLK_SEL 0x00007000
  250. #define CPRI_ALT_CLK_SHIFT 12
  251. rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
  252. rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
  253. /* For MAPLE and CPRI frequency */
  254. switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
  255. case 1:
  256. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  257. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  258. break;
  259. case 2:
  260. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  261. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  262. break;
  263. case 3:
  264. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  265. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  266. break;
  267. case 4:
  268. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  269. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  270. break;
  271. case 5:
  272. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  273. >> CPRI_ALT_CLK_SHIFT) == 6) {
  274. sys_info->freq_maple =
  275. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  276. sys_info->freq_cpri =
  277. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  278. }
  279. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  280. >> CPRI_ALT_CLK_SHIFT) == 7) {
  281. sys_info->freq_maple =
  282. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  283. sys_info->freq_cpri =
  284. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  285. }
  286. break;
  287. case 6:
  288. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  289. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  290. break;
  291. case 7:
  292. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  293. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  294. break;
  295. default:
  296. printf("Error: Unknown MAPLE/CPRI clock select!\n");
  297. }
  298. /* For MAPLE ULB and eTVPE frequencies */
  299. #define ULB_CLK_SEL 0x00000038
  300. #define ULB_CLK_SHIFT 3
  301. #define ETVPE_CLK_SEL 0x00000007
  302. #define ETVPE_CLK_SHIFT 0
  303. switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
  304. case 1:
  305. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
  306. break;
  307. case 2:
  308. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
  309. break;
  310. case 3:
  311. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
  312. break;
  313. case 4:
  314. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
  315. break;
  316. case 5:
  317. sys_info->freq_maple_ulb = sys_info->freq_systembus;
  318. break;
  319. case 6:
  320. sys_info->freq_maple_ulb =
  321. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
  322. break;
  323. case 7:
  324. sys_info->freq_maple_ulb =
  325. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
  326. break;
  327. default:
  328. printf("Error: Unknown MAPLE ULB clock select!\n");
  329. }
  330. switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
  331. case 1:
  332. sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
  333. break;
  334. case 2:
  335. sys_info->freq_maple_etvpe =
  336. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
  337. break;
  338. case 3:
  339. sys_info->freq_maple_etvpe =
  340. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
  341. break;
  342. case 4:
  343. sys_info->freq_maple_etvpe =
  344. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
  345. break;
  346. case 5:
  347. sys_info->freq_maple_etvpe = sys_info->freq_systembus;
  348. break;
  349. case 6:
  350. sys_info->freq_maple_etvpe =
  351. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
  352. break;
  353. case 7:
  354. sys_info->freq_maple_etvpe =
  355. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
  356. break;
  357. default:
  358. printf("Error: Unknown MAPLE eTVPE clock select!\n");
  359. }
  360. #endif
  361. #ifdef CONFIG_SYS_DPAA_FMAN
  362. #ifndef CONFIG_FM_PLAT_CLK_DIV
  363. switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
  364. case 1:
  365. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
  366. break;
  367. case 2:
  368. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
  369. break;
  370. case 3:
  371. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
  372. break;
  373. case 4:
  374. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
  375. break;
  376. case 5:
  377. sys_info->freq_fman[0] = sys_info->freq_systembus;
  378. break;
  379. case 6:
  380. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
  381. break;
  382. case 7:
  383. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
  384. break;
  385. default:
  386. printf("Error: Unknown FMan1 clock select!\n");
  387. case 0:
  388. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  389. break;
  390. }
  391. #if (CONFIG_SYS_NUM_FMAN) == 2
  392. #ifdef CONFIG_SYS_FM2_CLK
  393. #define FM2_CLK_SEL 0x00000038
  394. #define FM2_CLK_SHIFT 3
  395. rcw_tmp = in_be32(&gur->rcwsr[15]);
  396. switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
  397. case 1:
  398. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
  399. break;
  400. case 2:
  401. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
  402. break;
  403. case 3:
  404. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
  405. break;
  406. case 4:
  407. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
  408. break;
  409. case 5:
  410. sys_info->freq_fman[1] = sys_info->freq_systembus;
  411. break;
  412. case 6:
  413. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
  414. break;
  415. case 7:
  416. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
  417. break;
  418. default:
  419. printf("Error: Unknown FMan2 clock select!\n");
  420. case 0:
  421. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  422. break;
  423. }
  424. #endif
  425. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  426. #else
  427. sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
  428. #endif
  429. #endif
  430. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  431. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  432. u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
  433. & 0xf;
  434. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  435. sys_info->freq_processor[cpu] =
  436. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  437. }
  438. #define PME_CLK_SEL 0x80000000
  439. #define FM1_CLK_SEL 0x40000000
  440. #define FM2_CLK_SEL 0x20000000
  441. #define HWA_ASYNC_DIV 0x04000000
  442. #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
  443. #define HWA_CC_PLL 1
  444. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
  445. #define HWA_CC_PLL 2
  446. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
  447. #define HWA_CC_PLL 2
  448. #else
  449. #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
  450. #endif
  451. rcw_tmp = in_be32(&gur->rcwsr[7]);
  452. #ifdef CONFIG_SYS_DPAA_PME
  453. if (rcw_tmp & PME_CLK_SEL) {
  454. if (rcw_tmp & HWA_ASYNC_DIV)
  455. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
  456. else
  457. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
  458. } else {
  459. sys_info->freq_pme = sys_info->freq_systembus / 2;
  460. }
  461. #endif
  462. #ifdef CONFIG_SYS_DPAA_FMAN
  463. if (rcw_tmp & FM1_CLK_SEL) {
  464. if (rcw_tmp & HWA_ASYNC_DIV)
  465. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
  466. else
  467. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
  468. } else {
  469. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  470. }
  471. #if (CONFIG_SYS_NUM_FMAN) == 2
  472. if (rcw_tmp & FM2_CLK_SEL) {
  473. if (rcw_tmp & HWA_ASYNC_DIV)
  474. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
  475. else
  476. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
  477. } else {
  478. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  479. }
  480. #endif
  481. #endif
  482. #ifdef CONFIG_SYS_DPAA_QBMAN
  483. sys_info->freq_qman = sys_info->freq_systembus / 2;
  484. #endif
  485. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  486. #ifdef CONFIG_U_QE
  487. sys_info->freq_qe = sys_info->freq_systembus / 2;
  488. #endif
  489. #else /* CONFIG_FSL_CORENET */
  490. uint plat_ratio, e500_ratio, half_freq_systembus;
  491. int i;
  492. #ifdef CONFIG_QE
  493. __maybe_unused u32 qe_ratio;
  494. #endif
  495. plat_ratio = (gur->porpllsr) & 0x0000003e;
  496. plat_ratio >>= 1;
  497. sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
  498. /* Divide before multiply to avoid integer
  499. * overflow for processor speeds above 2GHz */
  500. half_freq_systembus = sys_info->freq_systembus/2;
  501. for (i = 0; i < cpu_numcores(); i++) {
  502. e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
  503. sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
  504. }
  505. /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
  506. sys_info->freq_ddrbus = sys_info->freq_systembus;
  507. #ifdef CONFIG_DDR_CLK_FREQ
  508. {
  509. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  510. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  511. if (ddr_ratio != 0x7)
  512. sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
  513. }
  514. #endif
  515. #ifdef CONFIG_QE
  516. #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
  517. sys_info->freq_qe = sys_info->freq_systembus;
  518. #else
  519. qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
  520. >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
  521. sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
  522. #endif
  523. #endif
  524. #ifdef CONFIG_SYS_DPAA_FMAN
  525. sys_info->freq_fman[0] = sys_info->freq_systembus;
  526. #endif
  527. #endif /* CONFIG_FSL_CORENET */
  528. #if defined(CONFIG_FSL_LBC)
  529. uint lcrr_div;
  530. #if defined(CONFIG_SYS_LBC_LCRR)
  531. /* We will program LCRR to this value later */
  532. lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
  533. #else
  534. lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
  535. #endif
  536. if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
  537. #if defined(CONFIG_FSL_CORENET)
  538. /* If this is corenet based SoC, bit-representation
  539. * for four times the clock divider values.
  540. */
  541. lcrr_div *= 4;
  542. #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
  543. !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
  544. /*
  545. * Yes, the entire PQ38 family use the same
  546. * bit-representation for twice the clock divider values.
  547. */
  548. lcrr_div *= 2;
  549. #endif
  550. sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
  551. } else {
  552. /* In case anyone cares what the unknown value is */
  553. sys_info->freq_localbus = lcrr_div;
  554. }
  555. #endif
  556. #if defined(CONFIG_FSL_IFC)
  557. ccr = ifc_in32(&ifc_regs->ifc_ccr);
  558. ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
  559. sys_info->freq_localbus = sys_info->freq_systembus / ccr;
  560. #endif
  561. }
  562. int get_clocks (void)
  563. {
  564. sys_info_t sys_info;
  565. #ifdef CONFIG_MPC8544
  566. volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
  567. #endif
  568. #if defined(CONFIG_CPM2)
  569. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  570. uint sccr, dfbrg;
  571. /* set VCO = 4 * BRG */
  572. cpm->im_cpm_intctl.sccr &= 0xfffffffc;
  573. sccr = cpm->im_cpm_intctl.sccr;
  574. dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
  575. #endif
  576. get_sys_info (&sys_info);
  577. gd->cpu_clk = sys_info.freq_processor[0];
  578. gd->bus_clk = sys_info.freq_systembus;
  579. gd->mem_clk = sys_info.freq_ddrbus;
  580. gd->arch.lbc_clk = sys_info.freq_localbus;
  581. #ifdef CONFIG_QE
  582. gd->arch.qe_clk = sys_info.freq_qe;
  583. gd->arch.brg_clk = gd->arch.qe_clk / 2;
  584. #endif
  585. /*
  586. * The base clock for I2C depends on the actual SOC. Unfortunately,
  587. * there is no pattern that can be used to determine the frequency, so
  588. * the only choice is to look up the actual SOC number and use the value
  589. * for that SOC. This information is taken from application note
  590. * AN2919.
  591. */
  592. #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
  593. defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
  594. defined(CONFIG_P1022)
  595. gd->arch.i2c1_clk = sys_info.freq_systembus;
  596. #elif defined(CONFIG_MPC8544)
  597. /*
  598. * On the 8544, the I2C clock is the same as the SEC clock. This can be
  599. * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
  600. * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
  601. * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
  602. * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
  603. */
  604. if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
  605. gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
  606. else
  607. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  608. #else
  609. /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
  610. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  611. #endif
  612. gd->arch.i2c2_clk = gd->arch.i2c1_clk;
  613. #if defined(CONFIG_FSL_ESDHC)
  614. #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
  615. defined(CONFIG_P1014)
  616. gd->arch.sdhc_clk = gd->bus_clk;
  617. #else
  618. gd->arch.sdhc_clk = gd->bus_clk / 2;
  619. #endif
  620. #endif /* defined(CONFIG_FSL_ESDHC) */
  621. #if defined(CONFIG_CPM2)
  622. gd->arch.vco_out = 2*sys_info.freq_systembus;
  623. gd->arch.cpm_clk = gd->arch.vco_out / 2;
  624. gd->arch.scc_clk = gd->arch.vco_out / 4;
  625. gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
  626. #endif
  627. if(gd->cpu_clk != 0) return (0);
  628. else return (1);
  629. }
  630. /********************************************
  631. * get_bus_freq
  632. * return system bus freq in Hz
  633. *********************************************/
  634. ulong get_bus_freq (ulong dummy)
  635. {
  636. return gd->bus_clk;
  637. }
  638. /********************************************
  639. * get_ddr_freq
  640. * return ddr bus freq in Hz
  641. *********************************************/
  642. ulong get_ddr_freq (ulong dummy)
  643. {
  644. return gd->mem_clk;
  645. }