stm32_flash.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015
  4. * Kamil Lulko, <kamil.lulko@gmail.com>
  5. */
  6. #include <common.h>
  7. #include <flash.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/stm32.h>
  10. #include "stm32_flash.h"
  11. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  12. #define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE)
  13. void stm32_flash_latency_cfg(int latency)
  14. {
  15. /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
  16. writel(FLASH_ACR_WS(latency) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
  17. | FLASH_ACR_DCEN, &STM32_FLASH->acr);
  18. }
  19. static void stm32_flash_lock(u8 lock)
  20. {
  21. if (lock) {
  22. setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
  23. } else {
  24. writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
  25. writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
  26. }
  27. }
  28. unsigned long flash_init(void)
  29. {
  30. unsigned long total_size = 0;
  31. u8 i, j;
  32. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  33. flash_info[i].flash_id = FLASH_STM32;
  34. flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
  35. flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
  36. flash_info[i].size = sect_sz_kb[0];
  37. for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
  38. flash_info[i].start[j] = flash_info[i].start[j - 1]
  39. + (sect_sz_kb[j - 1]);
  40. flash_info[i].size += sect_sz_kb[j];
  41. }
  42. total_size += flash_info[i].size;
  43. }
  44. return total_size;
  45. }
  46. void flash_print_info(flash_info_t *info)
  47. {
  48. int i;
  49. if (info->flash_id == FLASH_UNKNOWN) {
  50. printf("missing or unknown FLASH type\n");
  51. return;
  52. } else if (info->flash_id == FLASH_STM32) {
  53. printf("stm32 Embedded Flash\n");
  54. }
  55. printf(" Size: %ld MB in %d Sectors\n",
  56. info->size >> 20, info->sector_count);
  57. printf(" Sector Start Addresses:");
  58. for (i = 0; i < info->sector_count; ++i) {
  59. if ((i % 5) == 0)
  60. printf("\n ");
  61. printf(" %08lX%s",
  62. info->start[i],
  63. info->protect[i] ? " (RO)" : " ");
  64. }
  65. printf("\n");
  66. return;
  67. }
  68. int flash_erase(flash_info_t *info, int first, int last)
  69. {
  70. u8 bank = 0xFF;
  71. int i;
  72. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  73. if (info == &flash_info[i]) {
  74. bank = i;
  75. break;
  76. }
  77. }
  78. if (bank == 0xFF)
  79. return -1;
  80. stm32_flash_lock(0);
  81. for (i = first; i <= last; i++) {
  82. while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
  83. ;
  84. /* clear old sector number before writing a new one */
  85. clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
  86. if (bank == 0) {
  87. setbits_le32(&STM32_FLASH->cr,
  88. (i << STM32_FLASH_CR_SNB_OFFSET));
  89. } else if (bank == 1) {
  90. setbits_le32(&STM32_FLASH->cr,
  91. ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
  92. } else {
  93. stm32_flash_lock(1);
  94. return -1;
  95. }
  96. setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
  97. setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
  98. while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
  99. ;
  100. clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
  101. }
  102. stm32_flash_lock(1);
  103. return 0;
  104. }
  105. int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  106. {
  107. ulong i;
  108. while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
  109. ;
  110. stm32_flash_lock(0);
  111. setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
  112. /* To make things simple use byte writes only */
  113. for (i = 0; i < cnt; i++) {
  114. *(uchar *)(addr + i) = src[i];
  115. /* avoid re-ordering flash data write and busy status
  116. * check as flash memory space attributes are generally Normal
  117. */
  118. mb();
  119. while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
  120. ;
  121. }
  122. clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
  123. stm32_flash_lock(1);
  124. return 0;
  125. }