sf_dataflash.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel DataFlash probing
  4. *
  5. * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  6. * Haikun Wang (haikun.wang@freescale.com)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <flash.h>
  13. #include <spi.h>
  14. #include <spi_flash.h>
  15. #include <div64.h>
  16. #include <linux/err.h>
  17. #include <linux/math64.h>
  18. #include "sf_internal.h"
  19. #define CMD_READ_ID 0x9f
  20. /* reads can bypass the buffers */
  21. #define OP_READ_CONTINUOUS 0xE8
  22. #define OP_READ_PAGE 0xD2
  23. /* group B requests can run even while status reports "busy" */
  24. #define OP_READ_STATUS 0xD7 /* group B */
  25. /* move data between host and buffer */
  26. #define OP_READ_BUFFER1 0xD4 /* group B */
  27. #define OP_READ_BUFFER2 0xD6 /* group B */
  28. #define OP_WRITE_BUFFER1 0x84 /* group B */
  29. #define OP_WRITE_BUFFER2 0x87 /* group B */
  30. /* erasing flash */
  31. #define OP_ERASE_PAGE 0x81
  32. #define OP_ERASE_BLOCK 0x50
  33. /* move data between buffer and flash */
  34. #define OP_TRANSFER_BUF1 0x53
  35. #define OP_TRANSFER_BUF2 0x55
  36. #define OP_MREAD_BUFFER1 0xD4
  37. #define OP_MREAD_BUFFER2 0xD6
  38. #define OP_MWERASE_BUFFER1 0x83
  39. #define OP_MWERASE_BUFFER2 0x86
  40. #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
  41. #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
  42. /* write to buffer, then write-erase to flash */
  43. #define OP_PROGRAM_VIA_BUF1 0x82
  44. #define OP_PROGRAM_VIA_BUF2 0x85
  45. /* compare buffer to flash */
  46. #define OP_COMPARE_BUF1 0x60
  47. #define OP_COMPARE_BUF2 0x61
  48. /* read flash to buffer, then write-erase to flash */
  49. #define OP_REWRITE_VIA_BUF1 0x58
  50. #define OP_REWRITE_VIA_BUF2 0x59
  51. /*
  52. * newer chips report JEDEC manufacturer and device IDs; chip
  53. * serial number and OTP bits; and per-sector writeprotect.
  54. */
  55. #define OP_READ_ID 0x9F
  56. #define OP_READ_SECURITY 0x77
  57. #define OP_WRITE_SECURITY_REVC 0x9A
  58. #define OP_WRITE_SECURITY 0x9B /* revision D */
  59. struct dataflash {
  60. uint8_t command[16];
  61. unsigned short page_offset; /* offset in flash address */
  62. };
  63. /* Return the status of the DataFlash device */
  64. static inline int dataflash_status(struct spi_slave *spi)
  65. {
  66. int ret;
  67. u8 opcode = OP_READ_STATUS;
  68. u8 status;
  69. /*
  70. * NOTE: at45db321c over 25 MHz wants to write
  71. * a dummy byte after the opcode...
  72. */
  73. ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
  74. return ret ? -EIO : status;
  75. }
  76. /*
  77. * Poll the DataFlash device until it is READY.
  78. * This usually takes 5-20 msec or so; more for sector erase.
  79. * ready: return > 0
  80. */
  81. static int dataflash_waitready(struct spi_slave *spi)
  82. {
  83. int status;
  84. int timeout = 2 * CONFIG_SYS_HZ;
  85. int timebase;
  86. timebase = get_timer(0);
  87. do {
  88. status = dataflash_status(spi);
  89. if (status < 0)
  90. status = 0;
  91. if (status & (1 << 7)) /* RDY/nBSY */
  92. return status;
  93. mdelay(3);
  94. } while (get_timer(timebase) < timeout);
  95. return -ETIME;
  96. }
  97. /* Erase pages of flash */
  98. static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
  99. {
  100. struct dataflash *dataflash;
  101. struct spi_flash *spi_flash;
  102. struct spi_slave *spi;
  103. unsigned blocksize;
  104. uint8_t *command;
  105. uint32_t rem;
  106. int status;
  107. dataflash = dev_get_priv(dev);
  108. spi_flash = dev_get_uclass_priv(dev);
  109. spi = spi_flash->spi;
  110. blocksize = spi_flash->page_size << 3;
  111. memset(dataflash->command, 0 , sizeof(dataflash->command));
  112. command = dataflash->command;
  113. debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
  114. div_u64_rem(len, spi_flash->page_size, &rem);
  115. if (rem) {
  116. printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
  117. dev->name, len, spi_flash->page_size);
  118. return -EINVAL;
  119. }
  120. div_u64_rem(offset, spi_flash->page_size, &rem);
  121. if (rem) {
  122. printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
  123. dev->name, offset, spi_flash->page_size);
  124. return -EINVAL;
  125. }
  126. status = spi_claim_bus(spi);
  127. if (status) {
  128. debug("dataflash: unable to claim SPI bus\n");
  129. return status;
  130. }
  131. while (len > 0) {
  132. unsigned int pageaddr;
  133. int do_block;
  134. /*
  135. * Calculate flash page address; use block erase (for speed) if
  136. * we're at a block boundary and need to erase the whole block.
  137. */
  138. pageaddr = div_u64(offset, spi_flash->page_size);
  139. do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
  140. pageaddr = pageaddr << dataflash->page_offset;
  141. command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
  142. command[1] = (uint8_t)(pageaddr >> 16);
  143. command[2] = (uint8_t)(pageaddr >> 8);
  144. command[3] = 0;
  145. debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
  146. dev->name, do_block ? "block" : "page",
  147. command[0], command[1], command[2], command[3],
  148. pageaddr);
  149. status = spi_write_then_read(spi, command, 4, NULL, NULL, 0);
  150. if (status < 0) {
  151. debug("%s: erase send command error!\n", dev->name);
  152. return -EIO;
  153. }
  154. status = dataflash_waitready(spi);
  155. if (status < 0) {
  156. debug("%s: erase waitready error!\n", dev->name);
  157. return status;
  158. }
  159. if (do_block) {
  160. offset += blocksize;
  161. len -= blocksize;
  162. } else {
  163. offset += spi_flash->page_size;
  164. len -= spi_flash->page_size;
  165. }
  166. }
  167. spi_release_bus(spi);
  168. return 0;
  169. }
  170. /*
  171. * Read from the DataFlash device.
  172. * offset : Start offset in flash device
  173. * len : Amount to read
  174. * buf : Buffer containing the data
  175. */
  176. static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
  177. void *buf)
  178. {
  179. struct dataflash *dataflash;
  180. struct spi_flash *spi_flash;
  181. struct spi_slave *spi;
  182. unsigned int addr;
  183. uint8_t *command;
  184. int status;
  185. dataflash = dev_get_priv(dev);
  186. spi_flash = dev_get_uclass_priv(dev);
  187. spi = spi_flash->spi;
  188. memset(dataflash->command, 0 , sizeof(dataflash->command));
  189. command = dataflash->command;
  190. debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
  191. debug("READ: (%x) %x %x %x\n",
  192. command[0], command[1], command[2], command[3]);
  193. /* Calculate flash page/byte address */
  194. addr = (((unsigned)offset / spi_flash->page_size)
  195. << dataflash->page_offset)
  196. + ((unsigned)offset % spi_flash->page_size);
  197. status = spi_claim_bus(spi);
  198. if (status) {
  199. debug("dataflash: unable to claim SPI bus\n");
  200. return status;
  201. }
  202. /*
  203. * Continuous read, max clock = f(car) which may be less than
  204. * the peak rate available. Some chips support commands with
  205. * fewer "don't care" bytes. Both buffers stay unchanged.
  206. */
  207. command[0] = OP_READ_CONTINUOUS;
  208. command[1] = (uint8_t)(addr >> 16);
  209. command[2] = (uint8_t)(addr >> 8);
  210. command[3] = (uint8_t)(addr >> 0);
  211. /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
  212. status = spi_write_then_read(spi, command, 8, NULL, buf, len);
  213. spi_release_bus(spi);
  214. return status;
  215. }
  216. /*
  217. * Write to the DataFlash device.
  218. * offset : Start offset in flash device
  219. * len : Amount to write
  220. * buf : Buffer containing the data
  221. */
  222. int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
  223. const void *buf)
  224. {
  225. struct dataflash *dataflash;
  226. struct spi_flash *spi_flash;
  227. struct spi_slave *spi;
  228. uint8_t *command;
  229. unsigned int pageaddr, addr, to, writelen;
  230. size_t remaining = len;
  231. u_char *writebuf = (u_char *)buf;
  232. int status = -EINVAL;
  233. dataflash = dev_get_priv(dev);
  234. spi_flash = dev_get_uclass_priv(dev);
  235. spi = spi_flash->spi;
  236. memset(dataflash->command, 0 , sizeof(dataflash->command));
  237. command = dataflash->command;
  238. debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
  239. pageaddr = ((unsigned)offset / spi_flash->page_size);
  240. to = ((unsigned)offset % spi_flash->page_size);
  241. if (to + len > spi_flash->page_size)
  242. writelen = spi_flash->page_size - to;
  243. else
  244. writelen = len;
  245. status = spi_claim_bus(spi);
  246. if (status) {
  247. debug("dataflash: unable to claim SPI bus\n");
  248. return status;
  249. }
  250. while (remaining > 0) {
  251. debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
  252. /*
  253. * REVISIT:
  254. * (a) each page in a sector must be rewritten at least
  255. * once every 10K sibling erase/program operations.
  256. * (b) for pages that are already erased, we could
  257. * use WRITE+MWRITE not PROGRAM for ~30% speedup.
  258. * (c) WRITE to buffer could be done while waiting for
  259. * a previous MWRITE/MWERASE to complete ...
  260. * (d) error handling here seems to be mostly missing.
  261. *
  262. * Two persistent bits per page, plus a per-sector counter,
  263. * could support (a) and (b) ... we might consider using
  264. * the second half of sector zero, which is just one block,
  265. * to track that state. (On AT91, that sector should also
  266. * support boot-from-DataFlash.)
  267. */
  268. addr = pageaddr << dataflash->page_offset;
  269. /* (1) Maybe transfer partial page to Buffer1 */
  270. if (writelen != spi_flash->page_size) {
  271. command[0] = OP_TRANSFER_BUF1;
  272. command[1] = (addr & 0x00FF0000) >> 16;
  273. command[2] = (addr & 0x0000FF00) >> 8;
  274. command[3] = 0;
  275. debug("TRANSFER: (%x) %x %x %x\n",
  276. command[0], command[1], command[2], command[3]);
  277. status = spi_write_then_read(spi, command, 4,
  278. NULL, NULL, 0);
  279. if (status < 0) {
  280. debug("%s: write(<pagesize) command error!\n",
  281. dev->name);
  282. return -EIO;
  283. }
  284. status = dataflash_waitready(spi);
  285. if (status < 0) {
  286. debug("%s: write(<pagesize) waitready error!\n",
  287. dev->name);
  288. return status;
  289. }
  290. }
  291. /* (2) Program full page via Buffer1 */
  292. addr += to;
  293. command[0] = OP_PROGRAM_VIA_BUF1;
  294. command[1] = (addr & 0x00FF0000) >> 16;
  295. command[2] = (addr & 0x0000FF00) >> 8;
  296. command[3] = (addr & 0x000000FF);
  297. debug("PROGRAM: (%x) %x %x %x\n",
  298. command[0], command[1], command[2], command[3]);
  299. status = spi_write_then_read(spi, command, 4,
  300. writebuf, NULL, writelen);
  301. if (status < 0) {
  302. debug("%s: write send command error!\n", dev->name);
  303. return -EIO;
  304. }
  305. status = dataflash_waitready(spi);
  306. if (status < 0) {
  307. debug("%s: write waitready error!\n", dev->name);
  308. return status;
  309. }
  310. #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
  311. /* (3) Compare to Buffer1 */
  312. addr = pageaddr << dataflash->page_offset;
  313. command[0] = OP_COMPARE_BUF1;
  314. command[1] = (addr & 0x00FF0000) >> 16;
  315. command[2] = (addr & 0x0000FF00) >> 8;
  316. command[3] = 0;
  317. debug("COMPARE: (%x) %x %x %x\n",
  318. command[0], command[1], command[2], command[3]);
  319. status = spi_write_then_read(spi, command, 4,
  320. writebuf, NULL, writelen);
  321. if (status < 0) {
  322. debug("%s: write(compare) send command error!\n",
  323. dev->name);
  324. return -EIO;
  325. }
  326. status = dataflash_waitready(spi);
  327. /* Check result of the compare operation */
  328. if (status & (1 << 6)) {
  329. printf("dataflash: write compare page %u, err %d\n",
  330. pageaddr, status);
  331. remaining = 0;
  332. status = -EIO;
  333. break;
  334. } else {
  335. status = 0;
  336. }
  337. #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
  338. remaining = remaining - writelen;
  339. pageaddr++;
  340. to = 0;
  341. writebuf += writelen;
  342. if (remaining > spi_flash->page_size)
  343. writelen = spi_flash->page_size;
  344. else
  345. writelen = remaining;
  346. }
  347. spi_release_bus(spi);
  348. return 0;
  349. }
  350. static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
  351. int pagesize, int pageoffset, char revision)
  352. {
  353. struct spi_flash *spi_flash;
  354. struct dataflash *dataflash;
  355. dataflash = dev_get_priv(dev);
  356. spi_flash = dev_get_uclass_priv(dev);
  357. dataflash->page_offset = pageoffset;
  358. spi_flash->name = name;
  359. spi_flash->page_size = pagesize;
  360. spi_flash->size = nr_pages * pagesize;
  361. spi_flash->erase_size = pagesize;
  362. #ifndef CONFIG_SPL_BUILD
  363. printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
  364. print_size(spi_flash->page_size, ", erase size ");
  365. print_size(spi_flash->erase_size, ", total ");
  366. print_size(spi_flash->size, "");
  367. printf(", revision %c", revision);
  368. puts("\n");
  369. #endif
  370. return 0;
  371. }
  372. struct data_flash_info {
  373. char *name;
  374. /*
  375. * JEDEC id has a high byte of zero plus three data bytes:
  376. * the manufacturer id, then a two byte device id.
  377. */
  378. uint32_t jedec_id;
  379. /* The size listed here is what works with OP_ERASE_PAGE. */
  380. unsigned nr_pages;
  381. uint16_t pagesize;
  382. uint16_t pageoffset;
  383. uint16_t flags;
  384. #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
  385. #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
  386. };
  387. static struct data_flash_info dataflash_data[] = {
  388. /*
  389. * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
  390. * one with IS_POW2PS and the other without. The entry with the
  391. * non-2^N byte page size can't name exact chip revisions without
  392. * losing backwards compatibility for cmdlinepart.
  393. *
  394. * Those two entries have different name spelling format in order to
  395. * show their difference obviously.
  396. * The upper case refer to the chip isn't in normal 2^N bytes page-size
  397. * mode.
  398. * The lower case refer to the chip is in normal 2^N bytes page-size
  399. * mode.
  400. *
  401. * These newer chips also support 128-byte security registers (with
  402. * 64 bytes one-time-programmable) and software write-protection.
  403. */
  404. { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
  405. { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
  406. { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
  407. { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
  408. { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
  409. { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
  410. { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
  411. { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
  412. { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
  413. { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
  414. { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
  415. { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
  416. { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
  417. { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
  418. { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
  419. };
  420. static struct data_flash_info *jedec_probe(struct spi_slave *spi)
  421. {
  422. int tmp;
  423. uint8_t id[5];
  424. uint32_t jedec;
  425. struct data_flash_info *info;
  426. u8 opcode = CMD_READ_ID;
  427. int status;
  428. /*
  429. * JEDEC also defines an optional "extended device information"
  430. * string for after vendor-specific data, after the three bytes
  431. * we use here. Supporting some chips might require using it.
  432. *
  433. * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
  434. * That's not an error; only rev C and newer chips handle it, and
  435. * only Atmel sells these chips.
  436. */
  437. tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, sizeof(id));
  438. if (tmp < 0) {
  439. printf("dataflash: error %d reading JEDEC ID\n", tmp);
  440. return ERR_PTR(tmp);
  441. }
  442. if (id[0] != 0x1f)
  443. return NULL;
  444. jedec = id[0];
  445. jedec = jedec << 8;
  446. jedec |= id[1];
  447. jedec = jedec << 8;
  448. jedec |= id[2];
  449. for (tmp = 0, info = dataflash_data;
  450. tmp < ARRAY_SIZE(dataflash_data);
  451. tmp++, info++) {
  452. if (info->jedec_id == jedec) {
  453. if (info->flags & SUP_POW2PS) {
  454. status = dataflash_status(spi);
  455. if (status < 0) {
  456. debug("dataflash: status error %d\n",
  457. status);
  458. return NULL;
  459. }
  460. if (status & 0x1) {
  461. if (info->flags & IS_POW2PS)
  462. return info;
  463. } else {
  464. if (!(info->flags & IS_POW2PS))
  465. return info;
  466. }
  467. } else {
  468. return info;
  469. }
  470. }
  471. }
  472. /*
  473. * Treat other chips as errors ... we won't know the right page
  474. * size (it might be binary) even when we can tell which density
  475. * class is involved (legacy chip id scheme).
  476. */
  477. printf("dataflash: JEDEC id %06x not handled\n", jedec);
  478. return ERR_PTR(-ENODEV);
  479. }
  480. /*
  481. * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
  482. * or else the ID code embedded in the status bits:
  483. *
  484. * Device Density ID code #Pages PageSize Offset
  485. * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
  486. * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
  487. * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
  488. * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
  489. * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
  490. * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
  491. * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
  492. * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
  493. */
  494. static int spi_dataflash_probe(struct udevice *dev)
  495. {
  496. struct spi_slave *spi = dev_get_parent_priv(dev);
  497. struct spi_flash *spi_flash;
  498. struct data_flash_info *info;
  499. int status;
  500. spi_flash = dev_get_uclass_priv(dev);
  501. spi_flash->spi = spi;
  502. spi_flash->dev = dev;
  503. status = spi_claim_bus(spi);
  504. if (status)
  505. return status;
  506. /*
  507. * Try to detect dataflash by JEDEC ID.
  508. * If it succeeds we know we have either a C or D part.
  509. * D will support power of 2 pagesize option.
  510. * Both support the security register, though with different
  511. * write procedures.
  512. */
  513. info = jedec_probe(spi);
  514. if (IS_ERR(info))
  515. goto err_jedec_probe;
  516. if (info != NULL) {
  517. status = add_dataflash(dev, info->name, info->nr_pages,
  518. info->pagesize, info->pageoffset,
  519. (info->flags & SUP_POW2PS) ? 'd' : 'c');
  520. if (status < 0)
  521. goto err_status;
  522. }
  523. /*
  524. * Older chips support only legacy commands, identifing
  525. * capacity using bits in the status byte.
  526. */
  527. status = dataflash_status(spi);
  528. if (status <= 0 || status == 0xff) {
  529. printf("dataflash: read status error %d\n", status);
  530. if (status == 0 || status == 0xff)
  531. status = -ENODEV;
  532. goto err_jedec_probe;
  533. }
  534. /*
  535. * if there's a device there, assume it's dataflash.
  536. * board setup should have set spi->max_speed_max to
  537. * match f(car) for continuous reads, mode 0 or 3.
  538. */
  539. switch (status & 0x3c) {
  540. case 0x0c: /* 0 0 1 1 x x */
  541. status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
  542. break;
  543. case 0x14: /* 0 1 0 1 x x */
  544. status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
  545. break;
  546. case 0x1c: /* 0 1 1 1 x x */
  547. status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
  548. break;
  549. case 0x24: /* 1 0 0 1 x x */
  550. status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
  551. break;
  552. case 0x2c: /* 1 0 1 1 x x */
  553. status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
  554. break;
  555. case 0x34: /* 1 1 0 1 x x */
  556. status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
  557. break;
  558. case 0x38: /* 1 1 1 x x x */
  559. case 0x3c:
  560. status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
  561. break;
  562. /* obsolete AT45DB1282 not (yet?) supported */
  563. default:
  564. printf("dataflash: unsupported device (%x)\n", status & 0x3c);
  565. status = -ENODEV;
  566. goto err_status;
  567. }
  568. return status;
  569. err_status:
  570. spi_free_slave(spi);
  571. err_jedec_probe:
  572. spi_release_bus(spi);
  573. return status;
  574. }
  575. static const struct dm_spi_flash_ops spi_dataflash_ops = {
  576. .read = spi_dataflash_read,
  577. .write = spi_dataflash_write,
  578. .erase = spi_dataflash_erase,
  579. };
  580. static const struct udevice_id spi_dataflash_ids[] = {
  581. { .compatible = "atmel,at45", },
  582. { .compatible = "atmel,dataflash", },
  583. { }
  584. };
  585. U_BOOT_DRIVER(spi_dataflash) = {
  586. .name = "spi_dataflash",
  587. .id = UCLASS_SPI_FLASH,
  588. .of_match = spi_dataflash_ids,
  589. .probe = spi_dataflash_probe,
  590. .priv_auto_alloc_size = sizeof(struct dataflash),
  591. .ops = &spi_dataflash_ops,
  592. };