jedec_flash.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Michael Schwingen, <michael@schwingen.org>
  5. *
  6. * based in great part on jedec_probe.c from linux kernel:
  7. * (C) 2000 Red Hat. GPL'd.
  8. * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  9. */
  10. /* The DEBUG define must be before common to enable debugging */
  11. /*#define DEBUG*/
  12. #include <common.h>
  13. #include <flash.h>
  14. #include <asm/processor.h>
  15. #include <asm/io.h>
  16. #include <asm/byteorder.h>
  17. #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
  18. /* AMD */
  19. #define AM29DL800BB 0x22CB
  20. #define AM29DL800BT 0x224A
  21. #define AM29F400BB 0x22AB
  22. #define AM29F800BB 0x2258
  23. #define AM29F800BT 0x22D6
  24. #define AM29LV400BB 0x22BA
  25. #define AM29LV400BT 0x22B9
  26. #define AM29LV800BB 0x225B
  27. #define AM29LV800BT 0x22DA
  28. #define AM29LV160DT 0x22C4
  29. #define AM29LV160DB 0x2249
  30. #define AM29F017D 0x003D
  31. #define AM29F016D 0x00AD
  32. #define AM29F080 0x00D5
  33. #define AM29F040 0x00A4
  34. #define AM29LV040B 0x004F
  35. #define AM29F032B 0x0041
  36. #define AM29F002T 0x00B0
  37. /* SST */
  38. #define SST39LF800 0x2781
  39. #define SST39LF160 0x2782
  40. #define SST39VF1601 0x234b
  41. #define SST39LF512 0x00D4
  42. #define SST39LF010 0x00D5
  43. #define SST39LF020 0x00D6
  44. #define SST39LF040 0x00D7
  45. #define SST39SF010A 0x00B5
  46. #define SST39SF020A 0x00B6
  47. /* STM */
  48. #define STM29F400BB 0x00D6
  49. /* MXIC */
  50. #define MX29LV040 0x004F
  51. /* WINBOND */
  52. #define W39L040A 0x00D6
  53. /* AMIC */
  54. #define A29L040 0x0092
  55. /* EON */
  56. #define EN29LV040A 0x004F
  57. /*
  58. * Unlock address sets for AMD command sets.
  59. * Intel command sets use the MTD_UADDR_UNNECESSARY.
  60. * Each identifier, except MTD_UADDR_UNNECESSARY, and
  61. * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
  62. * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
  63. * initialization need not require initializing all of the
  64. * unlock addresses for all bit widths.
  65. */
  66. enum uaddr {
  67. MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
  68. MTD_UADDR_0x0555_0x02AA,
  69. MTD_UADDR_0x0555_0x0AAA,
  70. MTD_UADDR_0x5555_0x2AAA,
  71. MTD_UADDR_0x0AAA_0x0555,
  72. MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
  73. MTD_UADDR_UNNECESSARY, /* Does not require any address */
  74. };
  75. struct unlock_addr {
  76. u32 addr1;
  77. u32 addr2;
  78. };
  79. /*
  80. * I don't like the fact that the first entry in unlock_addrs[]
  81. * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
  82. * should not be used. The problem is that structures with
  83. * initializers have extra fields initialized to 0. It is _very_
  84. * desireable to have the unlock address entries for unsupported
  85. * data widths automatically initialized - that means that
  86. * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
  87. * must go unused.
  88. */
  89. static const struct unlock_addr unlock_addrs[] = {
  90. [MTD_UADDR_NOT_SUPPORTED] = {
  91. .addr1 = 0xffff,
  92. .addr2 = 0xffff
  93. },
  94. [MTD_UADDR_0x0555_0x02AA] = {
  95. .addr1 = 0x0555,
  96. .addr2 = 0x02aa
  97. },
  98. [MTD_UADDR_0x0555_0x0AAA] = {
  99. .addr1 = 0x0555,
  100. .addr2 = 0x0aaa
  101. },
  102. [MTD_UADDR_0x5555_0x2AAA] = {
  103. .addr1 = 0x5555,
  104. .addr2 = 0x2aaa
  105. },
  106. [MTD_UADDR_0x0AAA_0x0555] = {
  107. .addr1 = 0x0AAA,
  108. .addr2 = 0x0555
  109. },
  110. [MTD_UADDR_DONT_CARE] = {
  111. .addr1 = 0x0000, /* Doesn't matter which address */
  112. .addr2 = 0x0000 /* is used - must be last entry */
  113. },
  114. [MTD_UADDR_UNNECESSARY] = {
  115. .addr1 = 0x0000,
  116. .addr2 = 0x0000
  117. }
  118. };
  119. struct amd_flash_info {
  120. const __u16 mfr_id;
  121. const __u16 dev_id;
  122. const char *name;
  123. const int DevSize;
  124. const int NumEraseRegions;
  125. const int CmdSet;
  126. const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
  127. const ulong regions[6];
  128. };
  129. #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
  130. #define SIZE_64KiB 16
  131. #define SIZE_128KiB 17
  132. #define SIZE_256KiB 18
  133. #define SIZE_512KiB 19
  134. #define SIZE_1MiB 20
  135. #define SIZE_2MiB 21
  136. #define SIZE_4MiB 22
  137. #define SIZE_8MiB 23
  138. static const struct amd_flash_info jedec_table[] = {
  139. #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
  140. {
  141. .mfr_id = (u16)SST_MANUFACT,
  142. .dev_id = SST39LF020,
  143. .name = "SST 39LF020",
  144. .uaddr = {
  145. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  146. },
  147. .DevSize = SIZE_256KiB,
  148. .CmdSet = P_ID_AMD_STD,
  149. .NumEraseRegions= 1,
  150. .regions = {
  151. ERASEINFO(0x01000,64),
  152. }
  153. },
  154. #endif
  155. #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
  156. {
  157. .mfr_id = (u16)AMD_MANUFACT,
  158. .dev_id = AM29LV040B,
  159. .name = "AMD AM29LV040B",
  160. .uaddr = {
  161. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  162. },
  163. .DevSize = SIZE_512KiB,
  164. .CmdSet = P_ID_AMD_STD,
  165. .NumEraseRegions= 1,
  166. .regions = {
  167. ERASEINFO(0x10000,8),
  168. }
  169. },
  170. {
  171. .mfr_id = (u16)SST_MANUFACT,
  172. .dev_id = SST39LF040,
  173. .name = "SST 39LF040",
  174. .uaddr = {
  175. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  176. },
  177. .DevSize = SIZE_512KiB,
  178. .CmdSet = P_ID_AMD_STD,
  179. .NumEraseRegions= 1,
  180. .regions = {
  181. ERASEINFO(0x01000,128),
  182. }
  183. },
  184. {
  185. .mfr_id = (u16)STM_MANUFACT,
  186. .dev_id = STM_ID_M29W040B,
  187. .name = "ST Micro M29W040B",
  188. .uaddr = {
  189. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  190. },
  191. .DevSize = SIZE_512KiB,
  192. .CmdSet = P_ID_AMD_STD,
  193. .NumEraseRegions= 1,
  194. .regions = {
  195. ERASEINFO(0x10000,8),
  196. }
  197. },
  198. {
  199. .mfr_id = (u16)MX_MANUFACT,
  200. .dev_id = MX29LV040,
  201. .name = "MXIC MX29LV040",
  202. .uaddr = {
  203. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  204. },
  205. .DevSize = SIZE_512KiB,
  206. .CmdSet = P_ID_AMD_STD,
  207. .NumEraseRegions= 1,
  208. .regions = {
  209. ERASEINFO(0x10000, 8),
  210. }
  211. },
  212. {
  213. .mfr_id = (u16)WINB_MANUFACT,
  214. .dev_id = W39L040A,
  215. .name = "WINBOND W39L040A",
  216. .uaddr = {
  217. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  218. },
  219. .DevSize = SIZE_512KiB,
  220. .CmdSet = P_ID_AMD_STD,
  221. .NumEraseRegions= 1,
  222. .regions = {
  223. ERASEINFO(0x10000, 8),
  224. }
  225. },
  226. {
  227. .mfr_id = (u16)AMIC_MANUFACT,
  228. .dev_id = A29L040,
  229. .name = "AMIC A29L040",
  230. .uaddr = {
  231. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  232. },
  233. .DevSize = SIZE_512KiB,
  234. .CmdSet = P_ID_AMD_STD,
  235. .NumEraseRegions= 1,
  236. .regions = {
  237. ERASEINFO(0x10000, 8),
  238. }
  239. },
  240. {
  241. .mfr_id = (u16)EON_MANUFACT,
  242. .dev_id = EN29LV040A,
  243. .name = "EON EN29LV040A",
  244. .uaddr = {
  245. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  246. },
  247. .DevSize = SIZE_512KiB,
  248. .CmdSet = P_ID_AMD_STD,
  249. .NumEraseRegions= 1,
  250. .regions = {
  251. ERASEINFO(0x10000, 8),
  252. }
  253. },
  254. #endif
  255. #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
  256. {
  257. .mfr_id = (u16)AMD_MANUFACT,
  258. .dev_id = AM29F400BB,
  259. .name = "AMD AM29F400BB",
  260. .uaddr = {
  261. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  262. },
  263. .DevSize = SIZE_512KiB,
  264. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  265. .NumEraseRegions= 4,
  266. .regions = {
  267. ERASEINFO(0x04000, 1),
  268. ERASEINFO(0x02000, 2),
  269. ERASEINFO(0x08000, 1),
  270. ERASEINFO(0x10000, 7),
  271. }
  272. },
  273. {
  274. .mfr_id = (u16)AMD_MANUFACT,
  275. .dev_id = AM29LV400BB,
  276. .name = "AMD AM29LV400BB",
  277. .uaddr = {
  278. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  279. },
  280. .DevSize = SIZE_512KiB,
  281. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  282. .NumEraseRegions= 4,
  283. .regions = {
  284. ERASEINFO(0x04000,1),
  285. ERASEINFO(0x02000,2),
  286. ERASEINFO(0x08000,1),
  287. ERASEINFO(0x10000,7),
  288. }
  289. },
  290. {
  291. .mfr_id = (u16)AMD_MANUFACT,
  292. .dev_id = AM29LV800BB,
  293. .name = "AMD AM29LV800BB",
  294. .uaddr = {
  295. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  296. },
  297. .DevSize = SIZE_1MiB,
  298. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  299. .NumEraseRegions= 4,
  300. .regions = {
  301. ERASEINFO(0x04000, 1),
  302. ERASEINFO(0x02000, 2),
  303. ERASEINFO(0x08000, 1),
  304. ERASEINFO(0x10000, 15),
  305. }
  306. },
  307. {
  308. .mfr_id = (u16)AMD_MANUFACT,
  309. .dev_id = AM29LV800BT,
  310. .name = "AMD AM29LV800BT",
  311. .uaddr = {
  312. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  313. },
  314. .DevSize = SIZE_1MiB,
  315. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  316. .NumEraseRegions= 4,
  317. .regions = {
  318. ERASEINFO(0x10000, 15),
  319. ERASEINFO(0x08000, 1),
  320. ERASEINFO(0x02000, 2),
  321. ERASEINFO(0x04000, 1),
  322. }
  323. },
  324. {
  325. .mfr_id = (u16)MX_MANUFACT,
  326. .dev_id = AM29LV800BT,
  327. .name = "MXIC MX29LV800BT",
  328. .uaddr = {
  329. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  330. },
  331. .DevSize = SIZE_1MiB,
  332. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  333. .NumEraseRegions= 4,
  334. .regions = {
  335. ERASEINFO(0x10000, 15),
  336. ERASEINFO(0x08000, 1),
  337. ERASEINFO(0x02000, 2),
  338. ERASEINFO(0x04000, 1),
  339. }
  340. },
  341. {
  342. .mfr_id = (u16)EON_ALT_MANU,
  343. .dev_id = AM29LV800BT,
  344. .name = "EON EN29LV800BT",
  345. .uaddr = {
  346. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  347. },
  348. .DevSize = SIZE_1MiB,
  349. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  350. .NumEraseRegions= 4,
  351. .regions = {
  352. ERASEINFO(0x10000, 15),
  353. ERASEINFO(0x08000, 1),
  354. ERASEINFO(0x02000, 2),
  355. ERASEINFO(0x04000, 1),
  356. }
  357. },
  358. {
  359. .mfr_id = (u16)STM_MANUFACT,
  360. .dev_id = STM29F400BB,
  361. .name = "ST Micro M29F400BB",
  362. .uaddr = {
  363. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  364. },
  365. .DevSize = SIZE_512KiB,
  366. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  367. .NumEraseRegions = 4,
  368. .regions = {
  369. ERASEINFO(0x04000, 1),
  370. ERASEINFO(0x02000, 2),
  371. ERASEINFO(0x08000, 1),
  372. ERASEINFO(0x10000, 7),
  373. }
  374. },
  375. #endif
  376. };
  377. static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
  378. {
  379. int i,j;
  380. int sect_cnt;
  381. int size_ratio;
  382. int total_size;
  383. enum uaddr uaddr_idx;
  384. size_ratio = info->portwidth / info->chipwidth;
  385. debug("Found JEDEC Flash: %s\n", jedec_entry->name);
  386. info->vendor = jedec_entry->CmdSet;
  387. /* Todo: do we need device-specific timeouts? */
  388. info->erase_blk_tout = 30000;
  389. info->buffer_write_tout = 1000;
  390. info->write_tout = 100;
  391. info->name = jedec_entry->name;
  392. /* copy unlock addresses from device table to CFI info struct. This
  393. is just here because the addresses are in the table anyway - if
  394. the flash is not detected due to wrong unlock addresses,
  395. flash_detect_legacy would have to try all of them before we even
  396. get here. */
  397. switch(info->chipwidth) {
  398. case FLASH_CFI_8BIT:
  399. uaddr_idx = jedec_entry->uaddr[0];
  400. break;
  401. case FLASH_CFI_16BIT:
  402. uaddr_idx = jedec_entry->uaddr[1];
  403. break;
  404. case FLASH_CFI_32BIT:
  405. uaddr_idx = jedec_entry->uaddr[2];
  406. break;
  407. default:
  408. uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
  409. break;
  410. }
  411. debug("unlock address index %d\n", uaddr_idx);
  412. info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
  413. info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
  414. debug("unlock addresses are 0x%lx/0x%lx\n",
  415. info->addr_unlock1, info->addr_unlock2);
  416. sect_cnt = 0;
  417. total_size = 0;
  418. for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
  419. ulong erase_region_size = jedec_entry->regions[i] >> 8;
  420. ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
  421. total_size += erase_region_size * erase_region_count;
  422. debug("erase_region_count = %ld erase_region_size = %ld\n",
  423. erase_region_count, erase_region_size);
  424. for (j = 0; j < erase_region_count; j++) {
  425. if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
  426. printf("ERROR: too many flash sectors\n");
  427. break;
  428. }
  429. info->start[sect_cnt] = base;
  430. base += (erase_region_size * size_ratio);
  431. sect_cnt++;
  432. }
  433. }
  434. info->sector_count = sect_cnt;
  435. info->size = total_size * size_ratio;
  436. }
  437. /*-----------------------------------------------------------------------
  438. * match jedec ids against table. If a match is found, fill flash_info entry
  439. */
  440. int jedec_flash_match(flash_info_t *info, ulong base)
  441. {
  442. int ret = 0;
  443. int i;
  444. ulong mask = 0xFFFF;
  445. if (info->chipwidth == 1)
  446. mask = 0xFF;
  447. for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
  448. if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
  449. (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
  450. fill_info(info, &jedec_table[i], base);
  451. ret = 1;
  452. break;
  453. }
  454. }
  455. return ret;
  456. }