x600.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. *
  6. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  7. */
  8. #include <common.h>
  9. #include <flash.h>
  10. #include <init.h>
  11. #include <micrel.h>
  12. #include <nand.h>
  13. #include <netdev.h>
  14. #include <phy.h>
  15. #include <rtc.h>
  16. #include <asm/io.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/spr_defs.h>
  20. #include <asm/arch/spr_misc.h>
  21. #include <linux/mtd/fsmc_nand.h>
  22. #include "fpga.h"
  23. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  24. int board_init(void)
  25. {
  26. /*
  27. * X600 is equipped with an M41T82 RTC. This RTC has the
  28. * HT bit (Halt Update), which needs to be cleared upon
  29. * power-up. Otherwise the RTC is halted.
  30. */
  31. rtc_reset();
  32. return spear_board_init(MACH_TYPE_SPEAR600);
  33. }
  34. int board_late_init(void)
  35. {
  36. /*
  37. * Monitor and env protection on by default
  38. */
  39. flash_protect(FLAG_PROTECT_SET,
  40. CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
  41. CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
  42. 2 * CONFIG_ENV_SECT_SIZE - 1,
  43. &flash_info[0]);
  44. /* Init FPGA subsystem */
  45. x600_init_fpga();
  46. return 0;
  47. }
  48. /*
  49. * board_nand_init - Board specific NAND initialization
  50. * @nand: mtd private chip structure
  51. *
  52. * Called by nand_init_chip to initialize the board specific functions
  53. */
  54. void board_nand_init(void)
  55. {
  56. struct misc_regs *const misc_regs_p =
  57. (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  58. struct nand_chip *nand = &nand_chip[0];
  59. if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
  60. fsmc_nand_init(nand);
  61. }
  62. int board_phy_config(struct phy_device *phydev)
  63. {
  64. unsigned short id1, id2;
  65. /* check whether KSZ9031 or AR8035 has to be configured */
  66. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  67. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  68. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  69. /* PHY configuration for Micrel KSZ9031 */
  70. printf("PHY KSZ9031 detected - ");
  71. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  72. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  73. ksz9031_phy_extended_write(phydev, 0x02,
  74. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  75. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  76. 0x0000);
  77. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  78. ksz9031_phy_extended_write(phydev, 0x02,
  79. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  80. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  81. 0x0000);
  82. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  83. ksz9031_phy_extended_write(phydev, 0x02,
  84. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  85. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  86. 0x0000);
  87. /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
  88. ksz9031_phy_extended_write(phydev, 0x02,
  89. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  90. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  91. 0x03FF);
  92. } else {
  93. /* PHY configuration for Vitesse VSC8641 */
  94. printf("PHY VSC8641 detected - ");
  95. /* Extended PHY control 1, select GMII */
  96. phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
  97. /* Software reset necessary after GMII mode selction */
  98. phy_reset(phydev);
  99. /* Enable extended page register access */
  100. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
  101. /* 17e: Enhanced LED behavior, needs to be written twice */
  102. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
  103. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
  104. /* 16e: Enhanced LED method select */
  105. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
  106. /* Disable extended page register access */
  107. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
  108. /* Enable clock output pin */
  109. phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
  110. }
  111. if (phydev->drv->config)
  112. phydev->drv->config(phydev);
  113. return 0;
  114. }
  115. int board_eth_init(bd_t *bis)
  116. {
  117. int ret = 0;
  118. if (designware_initialize(CONFIG_SPEAR_ETHBASE,
  119. PHY_INTERFACE_MODE_GMII) >= 0)
  120. ret++;
  121. return ret;
  122. }