socrates.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <clock_legacy.h>
  14. #include <env.h>
  15. #include <pci.h>
  16. #include <uuid.h>
  17. #include <asm/processor.h>
  18. #include <asm/immap_85xx.h>
  19. #include <ioports.h>
  20. #include <flash.h>
  21. #include <linux/libfdt.h>
  22. #include <fdt_support.h>
  23. #include <asm/io.h>
  24. #include <i2c.h>
  25. #include <mb862xx.h>
  26. #include <video_fb.h>
  27. #include "upm_table.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. extern flash_info_t flash_info[]; /* FLASH chips info */
  30. extern GraphicDevice mb862xx;
  31. void local_bus_init (void);
  32. ulong flash_get_size (ulong base, int banknum);
  33. int checkboard (void)
  34. {
  35. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  36. char buf[64];
  37. int f;
  38. int i = env_get_f("serial#", buf, sizeof(buf));
  39. #ifdef CONFIG_PCI
  40. char *src;
  41. #endif
  42. puts("Board: Socrates");
  43. if (i > 0) {
  44. puts(", serial# ");
  45. puts(buf);
  46. }
  47. putc('\n');
  48. #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
  49. /* Check the PCI_clk sel bit */
  50. if (in_be32(&gur->porpllsr) & (1<<15)) {
  51. src = "SYSCLK";
  52. f = CONFIG_SYS_CLK_FREQ;
  53. } else {
  54. src = "PCI_CLK";
  55. f = CONFIG_PCI_CLK_FREQ;
  56. }
  57. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  58. #else
  59. printf ("PCI1: disabled\n");
  60. #endif
  61. /*
  62. * Initialize local bus.
  63. */
  64. local_bus_init ();
  65. return 0;
  66. }
  67. int misc_init_r (void)
  68. {
  69. /*
  70. * Adjust flash start and offset to detected values
  71. */
  72. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  73. gd->bd->bi_flashoffset = 0;
  74. /*
  75. * Check if boot FLASH isn't max size
  76. */
  77. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  78. set_lbc_or(0, gd->bd->bi_flashstart |
  79. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  80. set_lbc_br(0, gd->bd->bi_flashstart |
  81. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  82. /*
  83. * Re-check to get correct base address
  84. */
  85. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  86. }
  87. /*
  88. * Check if only one FLASH bank is available
  89. */
  90. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  91. set_lbc_or(1, 0);
  92. set_lbc_br(1, 0);
  93. /*
  94. * Re-do flash protection upon new addresses
  95. */
  96. flash_protect(FLAG_PROTECT_CLEAR,
  97. gd->bd->bi_flashstart, 0xffffffff,
  98. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  99. /* Monitor protection ON by default */
  100. flash_protect(FLAG_PROTECT_SET,
  101. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
  102. monitor_flash_len - 1,
  103. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  104. /* Environment protection ON by default */
  105. flash_protect(FLAG_PROTECT_SET,
  106. CONFIG_ENV_ADDR,
  107. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  108. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  109. /* Redundant environment protection ON by default */
  110. flash_protect(FLAG_PROTECT_SET,
  111. CONFIG_ENV_ADDR_REDUND,
  112. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  113. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  114. }
  115. #if defined(CONFIG_DM_PCI)
  116. pci_init();
  117. #endif
  118. return 0;
  119. }
  120. /*
  121. * Initialize Local Bus
  122. */
  123. void local_bus_init (void)
  124. {
  125. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  126. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  127. sys_info_t sysinfo;
  128. uint clkdiv;
  129. uint lbc_mhz;
  130. uint lcrr = CONFIG_SYS_LBC_LCRR;
  131. get_sys_info (&sysinfo);
  132. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  133. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  134. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  135. if (lbc_mhz >= 66)
  136. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  137. else
  138. lcrr |= LCRR_DBYP; /* DLL Bypass */
  139. out_be32 (&lbc->lcrr, lcrr);
  140. asm ("sync;isync;msync");
  141. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  142. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  143. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  144. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  145. /* Init UPMA for FPGA access */
  146. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  147. upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
  148. /* Init UPMB for Lime controller access */
  149. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  150. upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
  151. }
  152. #ifdef CONFIG_BOARD_EARLY_INIT_R
  153. int board_early_init_r (void)
  154. {
  155. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  156. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  157. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  158. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  159. udelay(200);
  160. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  161. return (0);
  162. }
  163. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  164. #ifdef CONFIG_OF_BOARD_SETUP
  165. int ft_board_setup(void *blob, bd_t *bd)
  166. {
  167. u32 val[12];
  168. int rc, i = 0;
  169. ft_cpu_setup(blob, bd);
  170. /* Fixup NOR FLASH mapping */
  171. val[i++] = 0; /* chip select number */
  172. val[i++] = 0; /* always 0 */
  173. val[i++] = gd->bd->bi_flashstart;
  174. val[i++] = gd->bd->bi_flashsize;
  175. #if defined(CONFIG_VIDEO_MB862xx)
  176. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  177. /* Fixup LIME mapping */
  178. val[i++] = 2; /* chip select number */
  179. val[i++] = 0; /* always 0 */
  180. val[i++] = CONFIG_SYS_LIME_BASE;
  181. val[i++] = CONFIG_SYS_LIME_SIZE;
  182. }
  183. #endif
  184. /* Fixup FPGA mapping */
  185. val[i++] = 3; /* chip select number */
  186. val[i++] = 0; /* always 0 */
  187. val[i++] = CONFIG_SYS_FPGA_BASE;
  188. val[i++] = CONFIG_SYS_FPGA_SIZE;
  189. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  190. val, i * sizeof(u32), 1);
  191. if (rc)
  192. printf("Unable to update localbus ranges, err=%s\n",
  193. fdt_strerror(rc));
  194. return 0;
  195. }
  196. #endif /* CONFIG_OF_BOARD_SETUP */
  197. #if defined(CONFIG_OF_SEPARATE)
  198. void *board_fdt_blob_setup(void)
  199. {
  200. void *fw_dtb;
  201. fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
  202. if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  203. printf("DTB is not passed via %x\n", (u32)fw_dtb);
  204. return NULL;
  205. }
  206. return fw_dtb;
  207. }
  208. #endif
  209. int get_serial_clock(void)
  210. {
  211. return 333333330;
  212. }