taurus.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
  4. * (C) Copyright Siemens AG
  5. *
  6. * Based on:
  7. * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
  8. *
  9. * (C) Copyright 2007-2008
  10. * Stelian Pop <stelian@popies.net>
  11. * Lead Tech Design <www.leadtechdesign.com>
  12. */
  13. #include <command.h>
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <env.h>
  17. #include <flash.h>
  18. #include <init.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/at91sam9260_matrix.h>
  21. #include <asm/arch/at91sam9_smc.h>
  22. #include <asm/arch/at91_common.h>
  23. #include <asm/arch/at91_rstc.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/at91sam9_sdramc.h>
  26. #include <asm/arch/atmel_serial.h>
  27. #include <asm/arch/clk.h>
  28. #include <asm/gpio.h>
  29. #include <linux/mtd/rawnand.h>
  30. #include <atmel_mci.h>
  31. #include <asm/arch/at91_spi.h>
  32. #include <spi.h>
  33. #include <net.h>
  34. #ifndef CONFIG_DM_ETH
  35. #include <netdev.h>
  36. #endif
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static void taurus_request_gpio(void)
  39. {
  40. gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
  41. gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
  42. gpio_request(AT91_PIN_PA25, "ena PHY");
  43. }
  44. static void taurus_nand_hw_init(void)
  45. {
  46. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  47. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  48. unsigned long csa;
  49. /* Assign CS3 to NAND/SmartMedia Interface */
  50. csa = readl(&matrix->ebicsa);
  51. csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  52. writel(csa, &matrix->ebicsa);
  53. /* Configure SMC CS3 for NAND/SmartMedia */
  54. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  55. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  56. &smc->cs[3].setup);
  57. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  58. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
  59. &smc->cs[3].pulse);
  60. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  61. &smc->cs[3].cycle);
  62. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  63. AT91_SMC_MODE_EXNW_DISABLE |
  64. AT91_SMC_MODE_DBW_8 |
  65. AT91_SMC_MODE_TDF_CYCLE(3),
  66. &smc->cs[3].mode);
  67. /* Configure RDY/BSY */
  68. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  69. /* Enable NandFlash */
  70. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71. }
  72. #if defined(CONFIG_SPL_BUILD)
  73. #include <spl.h>
  74. #include <nand.h>
  75. #include <spi_flash.h>
  76. void matrix_init(void)
  77. {
  78. struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  79. writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
  80. | AT91_MATRIX_SLOT_CYCLE_(0x40),
  81. &mat->scfg[3]);
  82. }
  83. #if defined(CONFIG_BOARD_AXM)
  84. static int at91_is_recovery(void)
  85. {
  86. if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
  87. (at91_get_gpio_value(AT91_PIN_PA27) == 0))
  88. return 1;
  89. return 0;
  90. }
  91. #elif defined(CONFIG_BOARD_TAURUS)
  92. static int at91_is_recovery(void)
  93. {
  94. if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
  95. return 1;
  96. return 0;
  97. }
  98. #endif
  99. void spl_board_init(void)
  100. {
  101. taurus_nand_hw_init();
  102. at91_spi0_hw_init(TAURUS_SPI_MASK);
  103. #if defined(CONFIG_BOARD_AXM)
  104. /* Configure LED PINs */
  105. at91_set_gpio_output(AT91_PIN_PA6, 0);
  106. at91_set_gpio_output(AT91_PIN_PA8, 0);
  107. at91_set_gpio_output(AT91_PIN_PA9, 0);
  108. at91_set_gpio_output(AT91_PIN_PA10, 0);
  109. at91_set_gpio_output(AT91_PIN_PA11, 0);
  110. at91_set_gpio_output(AT91_PIN_PA12, 0);
  111. /* Configure recovery button PINs */
  112. at91_set_gpio_input(AT91_PIN_PA26, 1);
  113. at91_set_gpio_input(AT91_PIN_PA27, 1);
  114. #elif defined(CONFIG_BOARD_TAURUS)
  115. at91_set_gpio_input(AT91_PIN_PA31, 1);
  116. #endif
  117. /* check for recovery mode */
  118. if (at91_is_recovery() == 1) {
  119. struct spi_flash *flash;
  120. puts("Recovery button pressed\n");
  121. nand_init();
  122. spl_nand_erase_one(0, 0);
  123. flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
  124. 0,
  125. CONFIG_SF_DEFAULT_SPEED,
  126. CONFIG_SF_DEFAULT_MODE);
  127. if (!flash) {
  128. puts("no flash\n");
  129. } else {
  130. puts("erase spi flash sector 0\n");
  131. spi_flash_erase(flash, 0,
  132. CONFIG_SYS_NAND_U_BOOT_SIZE);
  133. }
  134. }
  135. }
  136. #define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \
  137. |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
  138. | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \
  139. | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \
  140. | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10))
  141. void sdramc_configure(unsigned int mask)
  142. {
  143. struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  144. struct sdramc_reg setting;
  145. at91_sdram_hw_init();
  146. setting.cr = SDRAM_BASE_CONF | mask;
  147. setting.mdr = AT91_SDRAMC_MD_SDRAM;
  148. setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
  149. writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
  150. AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
  151. &ma->ebicsa);
  152. sdramc_initialize(ATMEL_BASE_CS1, &setting);
  153. }
  154. void mem_init(void)
  155. {
  156. unsigned int ram_size = 0;
  157. /* Configure SDRAM for 128MB */
  158. sdramc_configure(AT91_SDRAMC_NC_10);
  159. /* Do memtest for 128MB */
  160. ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  161. CONFIG_SYS_SDRAM_SIZE);
  162. /*
  163. * If 32MB or 16MB should be supported check also for
  164. * expected mirroring at A16 and A17
  165. * To find mirror addresses depends how the collumns are connected
  166. * at RAM (internaly or externaly)
  167. * If the collumns are not in inverted order the mirror size effect
  168. * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
  169. */
  170. /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
  171. if (ram_size == 0x800) {
  172. printf("\n\r 64MB\n");
  173. sdramc_configure(AT91_SDRAMC_NC_9);
  174. } else {
  175. /* Size already initialized */
  176. printf("\n\r 128MB\n");
  177. }
  178. }
  179. #endif
  180. #ifdef CONFIG_MACB
  181. static void siemens_phy_reset(void)
  182. {
  183. /*
  184. * we need to reset PHY for 200us
  185. * because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
  186. */
  187. if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
  188. AT91_RSTC_RSTTYP_GENERAL)
  189. at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
  190. }
  191. static void taurus_macb_hw_init(void)
  192. {
  193. /* Enable EMAC clock */
  194. at91_periph_clk_enable(ATMEL_ID_EMAC0);
  195. /*
  196. * Disable pull-up on:
  197. * RXDV (PA17) => PHY normal mode (not Test mode)
  198. * ERX0 (PA14) => PHY ADDR0
  199. * ERX1 (PA15) => PHY ADDR1
  200. * ERX2 (PA25) => PHY ADDR2
  201. * ERX3 (PA26) => PHY ADDR3
  202. * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
  203. *
  204. * PHY has internal pull-down
  205. */
  206. at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
  207. at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
  208. at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
  209. at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
  210. at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
  211. at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
  212. siemens_phy_reset();
  213. at91_phy_reset();
  214. at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
  215. /* Re-enable pull-up */
  216. at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
  217. at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
  218. at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
  219. at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
  220. at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
  221. at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
  222. /* Initialize EMAC=MACB hardware */
  223. at91_macb_hw_init();
  224. }
  225. #endif
  226. #ifdef CONFIG_GENERIC_ATMEL_MCI
  227. int board_mmc_init(bd_t *bd)
  228. {
  229. at91_mci_hw_init();
  230. return atmel_mci_init((void *)ATMEL_BASE_MCI);
  231. }
  232. #endif
  233. int board_early_init_f(void)
  234. {
  235. /* Enable clocks for all PIOs */
  236. at91_periph_clk_enable(ATMEL_ID_PIOA);
  237. at91_periph_clk_enable(ATMEL_ID_PIOB);
  238. at91_periph_clk_enable(ATMEL_ID_PIOC);
  239. at91_seriald_hw_init();
  240. taurus_request_gpio();
  241. return 0;
  242. }
  243. #ifdef CONFIG_USB_GADGET_AT91
  244. #include <linux/usb/at91_udc.h>
  245. void at91_udp_hw_init(void)
  246. {
  247. /* Enable PLLB */
  248. at91_pllb_clk_enable(get_pllb_init());
  249. /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
  250. at91_periph_clk_enable(ATMEL_ID_UDP);
  251. at91_system_clk_enable(AT91SAM926x_PMC_UDP);
  252. }
  253. struct at91_udc_data board_udc_data = {
  254. .baseaddr = ATMEL_BASE_UDP0,
  255. };
  256. #endif
  257. int board_init(void)
  258. {
  259. /* adress of boot parameters */
  260. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  261. taurus_request_gpio();
  262. #ifdef CONFIG_CMD_NAND
  263. taurus_nand_hw_init();
  264. #endif
  265. #ifdef CONFIG_MACB
  266. taurus_macb_hw_init();
  267. #endif
  268. at91_spi0_hw_init(TAURUS_SPI_MASK);
  269. #ifdef CONFIG_USB_GADGET_AT91
  270. at91_udp_hw_init();
  271. at91_udc_probe(&board_udc_data);
  272. #endif
  273. return 0;
  274. }
  275. int dram_init(void)
  276. {
  277. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  278. CONFIG_SYS_SDRAM_SIZE);
  279. return 0;
  280. }
  281. #if !defined(CONFIG_SPL_BUILD)
  282. #if defined(CONFIG_BOARD_AXM)
  283. /*
  284. * Booting the Fallback Image.
  285. *
  286. * The function is used to provide and
  287. * boot the image with the fallback
  288. * parameters, incase if the faulty image
  289. * in upgraded over the base firmware.
  290. *
  291. */
  292. static int upgrade_failure_fallback(void)
  293. {
  294. char *partitionset_active = NULL;
  295. char *rootfs = NULL;
  296. char *rootfs_fallback = NULL;
  297. char *kern_off;
  298. char *kern_off_fb;
  299. char *kern_size;
  300. char *kern_size_fb;
  301. partitionset_active = env_get("partitionset_active");
  302. if (partitionset_active) {
  303. if (partitionset_active[0] == 'A')
  304. env_set("partitionset_active", "B");
  305. else
  306. env_set("partitionset_active", "A");
  307. } else {
  308. printf("partitionset_active missing.\n");
  309. return -ENOENT;
  310. }
  311. rootfs = env_get("rootfs");
  312. rootfs_fallback = env_get("rootfs_fallback");
  313. env_set("rootfs", rootfs_fallback);
  314. env_set("rootfs_fallback", rootfs);
  315. kern_size = env_get("kernel_size");
  316. kern_size_fb = env_get("kernel_size_fallback");
  317. env_set("kernel_size", kern_size_fb);
  318. env_set("kernel_size_fallback", kern_size);
  319. kern_off = env_get("kernel_Off");
  320. kern_off_fb = env_get("kernel_Off_fallback");
  321. env_set("kernel_Off", kern_off_fb);
  322. env_set("kernel_Off_fallback", kern_off);
  323. env_set("bootargs", '\0');
  324. env_set("upgrade_available", '\0');
  325. env_set("boot_retries", '\0');
  326. env_save();
  327. return 0;
  328. }
  329. static int do_upgrade_available(cmd_tbl_t *cmdtp, int flag, int argc,
  330. char * const argv[])
  331. {
  332. unsigned long upgrade_available = 0;
  333. unsigned long boot_retry = 0;
  334. char boot_buf[10];
  335. upgrade_available = simple_strtoul(env_get("upgrade_available"), NULL,
  336. 10);
  337. if (upgrade_available) {
  338. boot_retry = simple_strtoul(env_get("boot_retries"), NULL, 10);
  339. boot_retry++;
  340. sprintf(boot_buf, "%lx", boot_retry);
  341. env_set("boot_retries", boot_buf);
  342. env_save();
  343. /*
  344. * Here the boot_retries count is checked, and if the
  345. * count becomes greater than 2 switch back to the
  346. * fallback, and reset the board.
  347. */
  348. if (boot_retry > 2) {
  349. if (upgrade_failure_fallback() == 0)
  350. do_reset(NULL, 0, 0, NULL);
  351. return -1;
  352. }
  353. }
  354. return 0;
  355. }
  356. U_BOOT_CMD(
  357. upgrade_available, 1, 1, do_upgrade_available,
  358. "check Siemens update",
  359. "no parameters"
  360. );
  361. #endif
  362. #endif