sh7752evb.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <flash.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <asm/processor.h>
  11. #include <asm/io.h>
  12. #include <asm/mmc.h>
  13. #include <spi.h>
  14. #include <spi_flash.h>
  15. int checkboard(void)
  16. {
  17. puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
  18. return 0;
  19. }
  20. static void init_gpio(void)
  21. {
  22. struct gpio_regs *gpio = GPIO_BASE;
  23. struct sermux_regs *sermux = SERMUX_BASE;
  24. /* GPIO */
  25. writew(0x0000, &gpio->pacr); /* GETHER */
  26. writew(0x0001, &gpio->pbcr); /* INTC */
  27. writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  28. writew(0xeaff, &gpio->pecr); /* GPIO */
  29. writew(0x0000, &gpio->pfcr); /* WDT */
  30. writew(0x0000, &gpio->phcr); /* SPI1 */
  31. writew(0x0000, &gpio->picr); /* SDHI */
  32. writew(0x0003, &gpio->pkcr); /* SerMux */
  33. writew(0x0000, &gpio->plcr); /* SerMux */
  34. writew(0x0000, &gpio->pmcr); /* RIIC */
  35. writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  36. writew(0x0000, &gpio->pocr); /* SGPIO */
  37. writew(0xd555, &gpio->pqcr); /* GPIO */
  38. writew(0x0000, &gpio->prcr); /* RIIC */
  39. writew(0x0000, &gpio->pscr); /* RIIC */
  40. writeb(0x00, &gpio->pudr);
  41. writew(0x5555, &gpio->pucr); /* Debug LED */
  42. writew(0x0000, &gpio->pvcr); /* RSPI */
  43. writew(0x0000, &gpio->pwcr); /* EVC */
  44. writew(0x0000, &gpio->pxcr); /* LBSC */
  45. writew(0x0000, &gpio->pycr); /* LBSC */
  46. writew(0x0000, &gpio->pzcr); /* eMMC */
  47. writew(0xfe00, &gpio->psel0);
  48. writew(0xff00, &gpio->psel3);
  49. writew(0x771f, &gpio->psel4);
  50. writew(0x00ff, &gpio->psel6);
  51. writew(0xfc00, &gpio->psel7);
  52. writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  53. }
  54. static void init_usb_phy(void)
  55. {
  56. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  57. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  58. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  59. struct usb1_port_regs *port = USB1_PORT_BASE;
  60. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  61. writew(0x0100, &phy->reset); /* set reset */
  62. /* port0 = USB0, port1 = USB1 */
  63. writew(0x0002, &phy->portsel);
  64. writel(0x0001, &port->port1sel); /* port1 = Host */
  65. writew(0x0111, &phy->reset); /* clear reset */
  66. writew(0x4000, &common0->suspmode);
  67. writew(0x4000, &common1->suspmode);
  68. #if defined(__LITTLE_ENDIAN)
  69. writel(0x00000000, &align->ehcidatac);
  70. writel(0x00000000, &align->ohcidatac);
  71. #endif
  72. }
  73. static void init_gether_mdio(void)
  74. {
  75. struct gpio_regs *gpio = GPIO_BASE;
  76. writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  77. writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  78. }
  79. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  80. {
  81. struct ether_mac_regs *ether;
  82. unsigned char mac[6];
  83. unsigned long val;
  84. string_to_enetaddr(mac_string, mac);
  85. if (!channel)
  86. ether = GETHER0_MAC_BASE;
  87. else
  88. ether = GETHER1_MAC_BASE;
  89. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  90. writel(val, &ether->mahr);
  91. val = (mac[4] << 8) | mac[5];
  92. writel(val, &ether->malr);
  93. }
  94. /*****************************************************************
  95. * This PMB must be set on this timing. The lowlevel_init is run on
  96. * Area 0(phys 0x00000000), so we have to map it.
  97. *
  98. * The new PMB table is following:
  99. * ent virt phys v sz c wt
  100. * 0 0xa0000000 0x40000000 1 128M 0 1
  101. * 1 0xa8000000 0x48000000 1 128M 0 1
  102. * 2 0xb0000000 0x50000000 1 128M 0 1
  103. * 3 0xb8000000 0x58000000 1 128M 0 1
  104. * 4 0x80000000 0x40000000 1 128M 1 1
  105. * 5 0x88000000 0x48000000 1 128M 1 1
  106. * 6 0x90000000 0x50000000 1 128M 1 1
  107. * 7 0x98000000 0x58000000 1 128M 1 1
  108. */
  109. static void set_pmb_on_board_init(void)
  110. {
  111. struct mmu_regs *mmu = MMU_BASE;
  112. /* clear ITLB */
  113. writel(0x00000004, &mmu->mmucr);
  114. /* delete PMB for SPIBOOT */
  115. writel(0, PMB_ADDR_BASE(0));
  116. writel(0, PMB_DATA_BASE(0));
  117. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  118. /* ppn ub v s1 s0 c wt */
  119. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  120. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  121. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  122. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  123. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  124. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  125. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  126. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  127. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  128. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  129. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  130. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  131. }
  132. int board_init(void)
  133. {
  134. init_gpio();
  135. set_pmb_on_board_init();
  136. init_usb_phy();
  137. init_gether_mdio();
  138. return 0;
  139. }
  140. int board_mmc_init(bd_t *bis)
  141. {
  142. struct gpio_regs *gpio = GPIO_BASE;
  143. writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  144. writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  145. udelay(1);
  146. writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  147. udelay(200);
  148. return mmcif_mmc_init();
  149. }
  150. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  151. {
  152. #ifdef CONFIG_DEPRECATED
  153. struct spi_flash *spi;
  154. int ret;
  155. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  156. if (spi == NULL) {
  157. printf("%s: spi_flash probe failed.\n", __func__);
  158. return 1;
  159. }
  160. ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
  161. if (ret) {
  162. printf("%s: spi_flash read failed.\n", __func__);
  163. spi_flash_free(spi);
  164. return 1;
  165. }
  166. spi_flash_free(spi);
  167. #endif
  168. return 0;
  169. }
  170. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  171. {
  172. memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
  173. SH7752EVB_ETHERNET_MAC_SIZE);
  174. mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  175. return 0;
  176. }
  177. static void init_ethernet_mac(void)
  178. {
  179. char mac_string[64];
  180. char env_string[64];
  181. int i;
  182. unsigned char *buf;
  183. buf = malloc(256);
  184. if (!buf) {
  185. printf("%s: malloc failed.\n", __func__);
  186. return;
  187. }
  188. get_sh_eth_mac_raw(buf, 256);
  189. /* Gigabit Ethernet */
  190. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  191. get_sh_eth_mac(i, mac_string, buf);
  192. if (i == 0)
  193. env_set("ethaddr", mac_string);
  194. else {
  195. sprintf(env_string, "eth%daddr", i);
  196. env_set(env_string, mac_string);
  197. }
  198. set_mac_to_sh_giga_eth_register(i, mac_string);
  199. }
  200. free(buf);
  201. }
  202. int board_late_init(void)
  203. {
  204. init_ethernet_mac();
  205. return 0;
  206. }
  207. #ifdef CONFIG_DEPRECATED
  208. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  209. {
  210. int i, ret;
  211. char mac_string[256];
  212. struct spi_flash *spi;
  213. unsigned char *buf;
  214. if (argc != 3) {
  215. buf = malloc(256);
  216. if (!buf) {
  217. printf("%s: malloc failed.\n", __func__);
  218. return 1;
  219. }
  220. get_sh_eth_mac_raw(buf, 256);
  221. /* print current MAC address */
  222. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  223. get_sh_eth_mac(i, mac_string, buf);
  224. printf("GETHERC ch%d = %s\n", i, mac_string);
  225. }
  226. free(buf);
  227. return 0;
  228. }
  229. /* new setting */
  230. memset(mac_string, 0xff, sizeof(mac_string));
  231. sprintf(mac_string, "%s\t%s",
  232. argv[1], argv[2]);
  233. /* write MAC data to SPI rom */
  234. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  235. if (!spi) {
  236. printf("%s: spi_flash probe failed.\n", __func__);
  237. return 1;
  238. }
  239. ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  240. SH7752EVB_SPI_SECTOR_SIZE);
  241. if (ret) {
  242. printf("%s: spi_flash erase failed.\n", __func__);
  243. return 1;
  244. }
  245. ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  246. sizeof(mac_string), mac_string);
  247. if (ret) {
  248. printf("%s: spi_flash write failed.\n", __func__);
  249. spi_flash_free(spi);
  250. return 1;
  251. }
  252. spi_flash_free(spi);
  253. puts("The writing of the MAC address to SPI ROM was completed.\n");
  254. return 0;
  255. }
  256. U_BOOT_CMD(
  257. write_mac, 3, 1, do_write_mac,
  258. "write MAC address for GETHERC",
  259. "[GETHERC ch0] [GETHERC ch1]\n"
  260. );
  261. #endif