strider.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <flash.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <spi.h>
  13. #include <linux/libfdt.h>
  14. #include <fdt_support.h>
  15. #include <pci.h>
  16. #include <mpc83xx.h>
  17. #include <fsl_esdhc.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_serdes.h>
  20. #include <asm/fsl_mpc83xx_serdes.h>
  21. #include "mpc8308.h"
  22. #include <gdsys_fpga.h>
  23. #include "../common/adv7611.h"
  24. #include "../common/ch7301.h"
  25. #include "../common/dp501.h"
  26. #include "../common/ioep-fpga.h"
  27. #include "../common/mclink.h"
  28. #include "../common/osd.h"
  29. #include "../common/phy.h"
  30. #include "../common/fanctrl.h"
  31. #include <pca953x.h>
  32. #include <pca9698.h>
  33. #include <miiphy.h>
  34. #define MAX_MUX_CHANNELS 2
  35. enum {
  36. MCFPGA_DONE = 1 << 0,
  37. MCFPGA_INIT_N = 1 << 1,
  38. MCFPGA_PROGRAM_N = 1 << 2,
  39. MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  40. MCFPGA_RESET_N = 1 << 4,
  41. };
  42. enum {
  43. GPIO_MDC = 1 << 14,
  44. GPIO_MDIO = 1 << 15,
  45. };
  46. uint mclink_fpgacount;
  47. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  48. struct {
  49. u8 bus;
  50. u8 addr;
  51. } strider_fans[] = CONFIG_STRIDER_FANS;
  52. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  53. {
  54. int res;
  55. switch (fpga) {
  56. case 0:
  57. out_le16(reg, data);
  58. break;
  59. default:
  60. res = mclink_send(fpga - 1, regoff, data);
  61. if (res < 0) {
  62. printf("mclink_send reg %02lx data %04x returned %d\n",
  63. regoff, data, res);
  64. return res;
  65. }
  66. break;
  67. }
  68. return 0;
  69. }
  70. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  71. {
  72. int res;
  73. switch (fpga) {
  74. case 0:
  75. *data = in_le16(reg);
  76. break;
  77. default:
  78. if (fpga > mclink_fpgacount)
  79. return -EINVAL;
  80. res = mclink_receive(fpga - 1, regoff, data);
  81. if (res < 0) {
  82. printf("mclink_receive reg %02lx returned %d\n",
  83. regoff, res);
  84. return res;
  85. }
  86. }
  87. return 0;
  88. }
  89. int checkboard(void)
  90. {
  91. char *s = env_get("serial#");
  92. bool hw_type_cat = pca9698_get_value(0x20, 18);
  93. puts("Board: ");
  94. printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
  95. if (s) {
  96. puts(", serial# ");
  97. puts(s);
  98. }
  99. puts("\n");
  100. return 0;
  101. }
  102. int last_stage_init(void)
  103. {
  104. int slaves;
  105. uint k;
  106. uint mux_ch;
  107. uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
  108. #ifdef CONFIG_STRIDER_CPU
  109. uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
  110. #endif
  111. bool hw_type_cat = pca9698_get_value(0x20, 18);
  112. #ifdef CONFIG_STRIDER_CON_DP
  113. bool is_dh = pca9698_get_value(0x20, 25);
  114. #endif
  115. bool ch0_sgmii2_present;
  116. /* Turn on Analog Devices ADV7611 */
  117. pca9698_direction_output(0x20, 8, 0);
  118. /* Turn on Parade DP501 */
  119. pca9698_direction_output(0x20, 10, 1);
  120. pca9698_direction_output(0x20, 11, 1);
  121. ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
  122. /* wait for FPGA done, then reset FPGA */
  123. for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
  124. uint ctr = 0;
  125. uchar *mclink_controllers = mclink_controllers_dvi;
  126. #ifdef CONFIG_STRIDER_CPU
  127. if (i2c_probe(mclink_controllers[k])) {
  128. mclink_controllers = mclink_controllers_dp;
  129. if (i2c_probe(mclink_controllers[k]))
  130. continue;
  131. }
  132. #else
  133. if (i2c_probe(mclink_controllers[k]))
  134. continue;
  135. #endif
  136. while (!(pca953x_get_val(mclink_controllers[k])
  137. & MCFPGA_DONE)) {
  138. mdelay(100);
  139. if (ctr++ > 5) {
  140. printf("no done for mclink_controller %d\n", k);
  141. break;
  142. }
  143. }
  144. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  145. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  146. udelay(10);
  147. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  148. MCFPGA_RESET_N);
  149. }
  150. if (hw_type_cat) {
  151. int retval;
  152. struct mii_dev *mdiodev = mdio_alloc();
  153. if (!mdiodev)
  154. return -ENOMEM;
  155. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  156. mdiodev->read = bb_miiphy_read;
  157. mdiodev->write = bb_miiphy_write;
  158. retval = mdio_register(mdiodev);
  159. if (retval < 0)
  160. return retval;
  161. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  162. if ((mux_ch == 1) && !ch0_sgmii2_present)
  163. continue;
  164. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  165. }
  166. }
  167. /* give slave-PLLs and Parade DP501 some time to be up and running */
  168. mdelay(500);
  169. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  170. slaves = mclink_probe();
  171. mclink_fpgacount = 0;
  172. ioep_fpga_print_info(0);
  173. if (!adv7611_probe(0))
  174. printf(" Advantiv ADV7611 HDMI Receiver\n");
  175. #ifdef CONFIG_STRIDER_CON
  176. if (ioep_fpga_has_osd(0))
  177. osd_probe(0);
  178. #endif
  179. #ifdef CONFIG_STRIDER_CON_DP
  180. if (ioep_fpga_has_osd(0)) {
  181. osd_probe(0);
  182. if (is_dh)
  183. osd_probe(4);
  184. }
  185. #endif
  186. #ifdef CONFIG_STRIDER_CPU
  187. ch7301_probe(0, false);
  188. dp501_probe(0, false);
  189. #endif
  190. if (slaves <= 0)
  191. return 0;
  192. mclink_fpgacount = slaves;
  193. #ifdef CONFIG_STRIDER_CPU
  194. /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
  195. for (k = 1; k <= slaves; ++k)
  196. FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
  197. mdelay(500);
  198. #endif
  199. for (k = 1; k <= slaves; ++k) {
  200. ioep_fpga_print_info(k);
  201. #ifdef CONFIG_STRIDER_CON
  202. if (ioep_fpga_has_osd(k))
  203. osd_probe(k);
  204. #endif
  205. #ifdef CONFIG_STRIDER_CON_DP
  206. if (ioep_fpga_has_osd(k)) {
  207. osd_probe(k);
  208. if (is_dh)
  209. osd_probe(k + 4);
  210. }
  211. #endif
  212. #ifdef CONFIG_STRIDER_CPU
  213. if (!adv7611_probe(k))
  214. printf(" Advantiv ADV7611 HDMI Receiver\n");
  215. ch7301_probe(k, false);
  216. dp501_probe(k, false);
  217. #endif
  218. if (hw_type_cat) {
  219. int retval;
  220. struct mii_dev *mdiodev = mdio_alloc();
  221. if (!mdiodev)
  222. return -ENOMEM;
  223. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  224. MDIO_NAME_LEN);
  225. mdiodev->read = bb_miiphy_read;
  226. mdiodev->write = bb_miiphy_write;
  227. retval = mdio_register(mdiodev);
  228. if (retval < 0)
  229. return retval;
  230. setup_88e1514(bb_miiphy_buses[k].name, 0);
  231. }
  232. }
  233. for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
  234. i2c_set_bus_num(strider_fans[k].bus);
  235. init_fan_controller(strider_fans[k].addr);
  236. }
  237. return 0;
  238. }
  239. /*
  240. * provide access to fpga gpios (for I2C bitbang)
  241. * (these may look all too simple but make iocon.h much more readable)
  242. */
  243. void fpga_gpio_set(uint bus, int pin)
  244. {
  245. FPGA_SET_REG(bus, gpio.set, pin);
  246. }
  247. void fpga_gpio_clear(uint bus, int pin)
  248. {
  249. FPGA_SET_REG(bus, gpio.clear, pin);
  250. }
  251. int fpga_gpio_get(uint bus, int pin)
  252. {
  253. u16 val;
  254. FPGA_GET_REG(bus, gpio.read, &val);
  255. return val & pin;
  256. }
  257. #ifdef CONFIG_STRIDER_CON_DP
  258. void fpga_control_set(uint bus, int pin)
  259. {
  260. u16 val;
  261. FPGA_GET_REG(bus, control, &val);
  262. FPGA_SET_REG(bus, control, val | pin);
  263. }
  264. void fpga_control_clear(uint bus, int pin)
  265. {
  266. u16 val;
  267. FPGA_GET_REG(bus, control, &val);
  268. FPGA_SET_REG(bus, control, val & ~pin);
  269. }
  270. #endif
  271. void mpc8308_init(void)
  272. {
  273. pca9698_direction_output(0x20, 26, 1);
  274. }
  275. void mpc8308_set_fpga_reset(uint state)
  276. {
  277. pca9698_set_value(0x20, 26, state ? 0 : 1);
  278. }
  279. void mpc8308_setup_hw(void)
  280. {
  281. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  282. /*
  283. * set "startup-finished"-gpios
  284. */
  285. setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
  286. setbits_gpio0_out(BIT(31 - 12));
  287. }
  288. int mpc8308_get_fpga_done(uint fpga)
  289. {
  290. return pca9698_get_value(0x20, 20);
  291. }
  292. #ifdef CONFIG_FSL_ESDHC
  293. int board_mmc_init(bd_t *bd)
  294. {
  295. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  296. sysconf83xx_t *sysconf = &immr->sysconf;
  297. /* Enable cache snooping in eSDHC system configuration register */
  298. out_be32(&sysconf->sdhccr, 0x02000000);
  299. return fsl_esdhc_mmc_init(bd);
  300. }
  301. #endif
  302. static struct pci_region pcie_regions_0[] = {
  303. {
  304. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  305. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  306. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  307. .flags = PCI_REGION_MEM,
  308. },
  309. {
  310. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  311. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  312. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  313. .flags = PCI_REGION_IO,
  314. },
  315. };
  316. void pci_init_board(void)
  317. {
  318. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  319. sysconf83xx_t *sysconf = &immr->sysconf;
  320. law83xx_t *pcie_law = sysconf->pcielaw;
  321. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  322. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  323. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  324. /* Deassert the resets in the control register */
  325. out_be32(&sysconf->pecr1, 0xE0008000);
  326. udelay(2000);
  327. /* Configure PCI Express Local Access Windows */
  328. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  329. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  330. mpc83xx_pcie_init(1, pcie_reg);
  331. }
  332. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  333. {
  334. info->portwidth = FLASH_CFI_16BIT;
  335. info->chipwidth = FLASH_CFI_BY16;
  336. info->interface = FLASH_CFI_X16;
  337. return 1;
  338. }
  339. #if defined(CONFIG_OF_BOARD_SETUP)
  340. int ft_board_setup(void *blob, bd_t *bd)
  341. {
  342. ft_cpu_setup(blob, bd);
  343. fsl_fdt_fixup_dr_usb(blob, bd);
  344. fdt_fixup_esdhc(blob, bd);
  345. return 0;
  346. }
  347. #endif
  348. /*
  349. * FPGA MII bitbang implementation
  350. */
  351. struct fpga_mii {
  352. uint fpga;
  353. int mdio;
  354. } fpga_mii[] = {
  355. { 0, 1},
  356. { 1, 1},
  357. { 2, 1},
  358. { 3, 1},
  359. };
  360. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  361. {
  362. return 0;
  363. }
  364. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  365. {
  366. struct fpga_mii *fpga_mii = bus->priv;
  367. if (fpga_mii->mdio)
  368. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  369. else
  370. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  371. return 0;
  372. }
  373. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  374. {
  375. struct fpga_mii *fpga_mii = bus->priv;
  376. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  377. return 0;
  378. }
  379. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  380. {
  381. struct fpga_mii *fpga_mii = bus->priv;
  382. if (v)
  383. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  384. else
  385. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  386. fpga_mii->mdio = v;
  387. return 0;
  388. }
  389. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  390. {
  391. u16 gpio;
  392. struct fpga_mii *fpga_mii = bus->priv;
  393. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  394. *v = ((gpio & GPIO_MDIO) != 0);
  395. return 0;
  396. }
  397. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  398. {
  399. struct fpga_mii *fpga_mii = bus->priv;
  400. if (v)
  401. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  402. else
  403. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  404. return 0;
  405. }
  406. static int mii_delay(struct bb_miiphy_bus *bus)
  407. {
  408. udelay(1);
  409. return 0;
  410. }
  411. struct bb_miiphy_bus bb_miiphy_buses[] = {
  412. {
  413. .name = "board0",
  414. .init = mii_dummy_init,
  415. .mdio_active = mii_mdio_active,
  416. .mdio_tristate = mii_mdio_tristate,
  417. .set_mdio = mii_set_mdio,
  418. .get_mdio = mii_get_mdio,
  419. .set_mdc = mii_set_mdc,
  420. .delay = mii_delay,
  421. .priv = &fpga_mii[0],
  422. },
  423. {
  424. .name = "board1",
  425. .init = mii_dummy_init,
  426. .mdio_active = mii_mdio_active,
  427. .mdio_tristate = mii_mdio_tristate,
  428. .set_mdio = mii_set_mdio,
  429. .get_mdio = mii_get_mdio,
  430. .set_mdc = mii_set_mdc,
  431. .delay = mii_delay,
  432. .priv = &fpga_mii[1],
  433. },
  434. {
  435. .name = "board2",
  436. .init = mii_dummy_init,
  437. .mdio_active = mii_mdio_active,
  438. .mdio_tristate = mii_mdio_tristate,
  439. .set_mdio = mii_set_mdio,
  440. .get_mdio = mii_get_mdio,
  441. .set_mdc = mii_set_mdc,
  442. .delay = mii_delay,
  443. .priv = &fpga_mii[2],
  444. },
  445. {
  446. .name = "board3",
  447. .init = mii_dummy_init,
  448. .mdio_active = mii_mdio_active,
  449. .mdio_tristate = mii_mdio_tristate,
  450. .set_mdio = mii_set_mdio,
  451. .get_mdio = mii_get_mdio,
  452. .set_mdc = mii_set_mdc,
  453. .delay = mii_delay,
  454. .priv = &fpga_mii[3],
  455. },
  456. };
  457. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);