hrcon.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <flash.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <spi.h>
  13. #include <linux/libfdt.h>
  14. #include <fdt_support.h>
  15. #include <pci.h>
  16. #include <mpc83xx.h>
  17. #include <fsl_esdhc.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_serdes.h>
  20. #include <asm/fsl_mpc83xx_serdes.h>
  21. #include "mpc8308.h"
  22. #include <gdsys_fpga.h>
  23. #include "../common/ioep-fpga.h"
  24. #include "../common/osd.h"
  25. #include "../common/mclink.h"
  26. #include "../common/phy.h"
  27. #include "../common/fanctrl.h"
  28. #include <pca953x.h>
  29. #include <pca9698.h>
  30. #include <miiphy.h>
  31. #define MAX_MUX_CHANNELS 2
  32. enum {
  33. MCFPGA_DONE = BIT(0),
  34. MCFPGA_INIT_N = BIT(1),
  35. MCFPGA_PROGRAM_N = BIT(2),
  36. MCFPGA_UPDATE_ENABLE_N = BIT(3),
  37. MCFPGA_RESET_N = BIT(4),
  38. };
  39. enum {
  40. GPIO_MDC = 1 << 14,
  41. GPIO_MDIO = 1 << 15,
  42. };
  43. uint mclink_fpgacount;
  44. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  45. struct {
  46. u8 bus;
  47. u8 addr;
  48. } hrcon_fans[] = CONFIG_HRCON_FANS;
  49. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  50. {
  51. int res;
  52. switch (fpga) {
  53. case 0:
  54. out_le16(reg, data);
  55. break;
  56. default:
  57. res = mclink_send(fpga - 1, regoff, data);
  58. if (res < 0) {
  59. printf("mclink_send reg %02lx data %04x returned %d\n",
  60. regoff, data, res);
  61. return res;
  62. }
  63. break;
  64. }
  65. return 0;
  66. }
  67. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  68. {
  69. int res;
  70. switch (fpga) {
  71. case 0:
  72. *data = in_le16(reg);
  73. break;
  74. default:
  75. if (fpga > mclink_fpgacount)
  76. return -EINVAL;
  77. res = mclink_receive(fpga - 1, regoff, data);
  78. if (res < 0) {
  79. printf("mclink_receive reg %02lx returned %d\n",
  80. regoff, res);
  81. return res;
  82. }
  83. }
  84. return 0;
  85. }
  86. int checkboard(void)
  87. {
  88. char *s = env_get("serial#");
  89. bool hw_type_cat = pca9698_get_value(0x20, 20);
  90. puts("Board: ");
  91. printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
  92. if (s) {
  93. puts(", serial# ");
  94. puts(s);
  95. }
  96. puts("\n");
  97. return 0;
  98. }
  99. int last_stage_init(void)
  100. {
  101. int slaves;
  102. uint k;
  103. uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
  104. u16 fpga_features;
  105. bool hw_type_cat = pca9698_get_value(0x20, 20);
  106. bool ch0_rgmii2_present;
  107. FPGA_GET_REG(0, fpga_features, &fpga_features);
  108. /* Turn on Parade DP501 */
  109. pca9698_direction_output(0x20, 10, 1);
  110. pca9698_direction_output(0x20, 11, 1);
  111. ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  112. /* wait for FPGA done, then reset FPGA */
  113. for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
  114. uint ctr = 0;
  115. if (i2c_probe(mclink_controllers[k]))
  116. continue;
  117. while (!(pca953x_get_val(mclink_controllers[k])
  118. & MCFPGA_DONE)) {
  119. mdelay(100);
  120. if (ctr++ > 5) {
  121. printf("no done for mclink_controller %u\n", k);
  122. break;
  123. }
  124. }
  125. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  126. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  127. udelay(10);
  128. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  129. MCFPGA_RESET_N);
  130. }
  131. if (hw_type_cat) {
  132. uint mux_ch;
  133. int retval;
  134. struct mii_dev *mdiodev = mdio_alloc();
  135. if (!mdiodev)
  136. return -ENOMEM;
  137. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  138. mdiodev->read = bb_miiphy_read;
  139. mdiodev->write = bb_miiphy_write;
  140. retval = mdio_register(mdiodev);
  141. if (retval < 0)
  142. return retval;
  143. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  144. if ((mux_ch == 1) && !ch0_rgmii2_present)
  145. continue;
  146. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  147. }
  148. }
  149. /* give slave-PLLs and Parade DP501 some time to be up and running */
  150. mdelay(500);
  151. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  152. slaves = mclink_probe();
  153. mclink_fpgacount = 0;
  154. ioep_fpga_print_info(0);
  155. osd_probe(0);
  156. #ifdef CONFIG_SYS_OSD_DH
  157. osd_probe(4);
  158. #endif
  159. if (slaves <= 0)
  160. return 0;
  161. mclink_fpgacount = slaves;
  162. for (k = 1; k <= slaves; ++k) {
  163. FPGA_GET_REG(k, fpga_features, &fpga_features);
  164. ioep_fpga_print_info(k);
  165. osd_probe(k);
  166. #ifdef CONFIG_SYS_OSD_DH
  167. osd_probe(k + 4);
  168. #endif
  169. if (hw_type_cat) {
  170. int retval;
  171. struct mii_dev *mdiodev = mdio_alloc();
  172. if (!mdiodev)
  173. return -ENOMEM;
  174. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  175. MDIO_NAME_LEN);
  176. mdiodev->read = bb_miiphy_read;
  177. mdiodev->write = bb_miiphy_write;
  178. retval = mdio_register(mdiodev);
  179. if (retval < 0)
  180. return retval;
  181. setup_88e1514(bb_miiphy_buses[k].name, 0);
  182. }
  183. }
  184. for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
  185. i2c_set_bus_num(hrcon_fans[k].bus);
  186. init_fan_controller(hrcon_fans[k].addr);
  187. }
  188. return 0;
  189. }
  190. /*
  191. * provide access to fpga gpios and controls (for I2C bitbang)
  192. * (these may look all too simple but make iocon.h much more readable)
  193. */
  194. void fpga_gpio_set(uint bus, int pin)
  195. {
  196. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
  197. }
  198. void fpga_gpio_clear(uint bus, int pin)
  199. {
  200. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
  201. }
  202. int fpga_gpio_get(uint bus, int pin)
  203. {
  204. u16 val;
  205. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
  206. return val & pin;
  207. }
  208. void fpga_control_set(uint bus, int pin)
  209. {
  210. u16 val;
  211. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  212. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
  213. }
  214. void fpga_control_clear(uint bus, int pin)
  215. {
  216. u16 val;
  217. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  218. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
  219. }
  220. void mpc8308_init(void)
  221. {
  222. pca9698_direction_output(0x20, 4, 1);
  223. }
  224. void mpc8308_set_fpga_reset(uint state)
  225. {
  226. pca9698_set_value(0x20, 4, state ? 0 : 1);
  227. }
  228. void mpc8308_setup_hw(void)
  229. {
  230. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  231. /*
  232. * set "startup-finished"-gpios
  233. */
  234. setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
  235. setbits_gpio0_out(BIT(31 - 12));
  236. }
  237. int mpc8308_get_fpga_done(uint fpga)
  238. {
  239. return pca9698_get_value(0x20, 19);
  240. }
  241. #ifdef CONFIG_FSL_ESDHC
  242. int board_mmc_init(bd_t *bd)
  243. {
  244. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  245. sysconf83xx_t *sysconf = &immr->sysconf;
  246. /* Enable cache snooping in eSDHC system configuration register */
  247. out_be32(&sysconf->sdhccr, 0x02000000);
  248. return fsl_esdhc_mmc_init(bd);
  249. }
  250. #endif
  251. static struct pci_region pcie_regions_0[] = {
  252. {
  253. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  254. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  255. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  256. .flags = PCI_REGION_MEM,
  257. },
  258. {
  259. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  260. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  261. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  262. .flags = PCI_REGION_IO,
  263. },
  264. };
  265. void pci_init_board(void)
  266. {
  267. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  268. sysconf83xx_t *sysconf = &immr->sysconf;
  269. law83xx_t *pcie_law = sysconf->pcielaw;
  270. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  271. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  272. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  273. /* Deassert the resets in the control register */
  274. out_be32(&sysconf->pecr1, 0xE0008000);
  275. udelay(2000);
  276. /* Configure PCI Express Local Access Windows */
  277. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  278. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  279. mpc83xx_pcie_init(1, pcie_reg);
  280. }
  281. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  282. {
  283. info->portwidth = FLASH_CFI_16BIT;
  284. info->chipwidth = FLASH_CFI_BY16;
  285. info->interface = FLASH_CFI_X16;
  286. return 1;
  287. }
  288. #if defined(CONFIG_OF_BOARD_SETUP)
  289. int ft_board_setup(void *blob, bd_t *bd)
  290. {
  291. ft_cpu_setup(blob, bd);
  292. fsl_fdt_fixup_dr_usb(blob, bd);
  293. fdt_fixup_esdhc(blob, bd);
  294. return 0;
  295. }
  296. #endif
  297. /*
  298. * FPGA MII bitbang implementation
  299. */
  300. struct fpga_mii {
  301. uint fpga;
  302. int mdio;
  303. } fpga_mii[] = {
  304. { 0, 1},
  305. { 1, 1},
  306. { 2, 1},
  307. { 3, 1},
  308. };
  309. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  310. {
  311. return 0;
  312. }
  313. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  314. {
  315. struct fpga_mii *fpga_mii = bus->priv;
  316. if (fpga_mii->mdio)
  317. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  318. else
  319. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  320. return 0;
  321. }
  322. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  323. {
  324. struct fpga_mii *fpga_mii = bus->priv;
  325. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  326. return 0;
  327. }
  328. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  329. {
  330. struct fpga_mii *fpga_mii = bus->priv;
  331. if (v)
  332. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  333. else
  334. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  335. fpga_mii->mdio = v;
  336. return 0;
  337. }
  338. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  339. {
  340. u16 gpio;
  341. struct fpga_mii *fpga_mii = bus->priv;
  342. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  343. *v = ((gpio & GPIO_MDIO) != 0);
  344. return 0;
  345. }
  346. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  347. {
  348. struct fpga_mii *fpga_mii = bus->priv;
  349. if (v)
  350. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  351. else
  352. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  353. return 0;
  354. }
  355. static int mii_delay(struct bb_miiphy_bus *bus)
  356. {
  357. udelay(1);
  358. return 0;
  359. }
  360. struct bb_miiphy_bus bb_miiphy_buses[] = {
  361. {
  362. .name = "board0",
  363. .init = mii_dummy_init,
  364. .mdio_active = mii_mdio_active,
  365. .mdio_tristate = mii_mdio_tristate,
  366. .set_mdio = mii_set_mdio,
  367. .get_mdio = mii_get_mdio,
  368. .set_mdc = mii_set_mdc,
  369. .delay = mii_delay,
  370. .priv = &fpga_mii[0],
  371. },
  372. {
  373. .name = "board1",
  374. .init = mii_dummy_init,
  375. .mdio_active = mii_mdio_active,
  376. .mdio_tristate = mii_mdio_tristate,
  377. .set_mdio = mii_set_mdio,
  378. .get_mdio = mii_get_mdio,
  379. .set_mdc = mii_set_mdc,
  380. .delay = mii_delay,
  381. .priv = &fpga_mii[1],
  382. },
  383. {
  384. .name = "board2",
  385. .init = mii_dummy_init,
  386. .mdio_active = mii_mdio_active,
  387. .mdio_tristate = mii_mdio_tristate,
  388. .set_mdio = mii_set_mdio,
  389. .get_mdio = mii_get_mdio,
  390. .set_mdc = mii_set_mdc,
  391. .delay = mii_delay,
  392. .priv = &fpga_mii[2],
  393. },
  394. {
  395. .name = "board3",
  396. .init = mii_dummy_init,
  397. .mdio_active = mii_mdio_active,
  398. .mdio_tristate = mii_mdio_tristate,
  399. .set_mdio = mii_set_mdio,
  400. .get_mdio = mii_get_mdio,
  401. .set_mdc = mii_set_mdc,
  402. .delay = mii_delay,
  403. .priv = &fpga_mii[3],
  404. },
  405. };
  406. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);